US 6102528

I'll search for information on this patent number, including any litigation or docket activity.

US Patent 6,102,528 — Analyst Summary

Search scope note: I queried for the exact string 6102528 / 6,102,528 against patent-full-text, USPTO/PTO-adjacent, and Federal Circuit sources. I found no record of any litigation, PTAB proceeding, or CAFC 2026 docket involving US 6,102,528. That is a negative finding, not proof of absence — I cannot rule out a filing that did not surface in search results.

Also, flagging two literal-match artifacts (per the no-auto-correction rule, I report these as distinct documents rather than assuming a typo):

• JP Patent No. 6102528 B2 (Fujitsu Limited; "Signal processing device and signal processing method"; app. 2013-117358, registered 2017-03-29; pub. JP2014-235613A) — an unrelated Japanese patent whose numeric string coincidentally matches.
• The Google Patents family table lists US953656 with a priority date of 1978-10-23 in one row, which conflicts with the 1997-10-17 date used everywhere else. This appears to be a database artifact, but I am noting it as-is.

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Bibliographic Data

Abstract (as issued): A drive transistor for a high resolution ink jet printhead having a pocket implant in the gate region of the device. The pocket implant enables a reduced source-to-drain spacing without loss of breakdown voltage, so the transistor size may be reduced. Alternatively, the device is suitable for addressing 1200 spi resolution printheads. In one embodiment, the pocket implant extends about 1 µm beyond the gate region toward the drain region. Both embodiments produce a graded drift region.

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Technology Context (brief)

The patent addresses the layout problem for thermal ink jet printheads at ≥400 spots per inch (spi). As nozzle pitch shrinks (400 spi ≈ 63.5 µm pitch; 800 spi ≈ 31.75 µm; 1200 spi ≈ 21.17 µm), the MOSFET source-to-drain spacing must shrink, which causes the drain depletion region to reach the source and create a subsurface conduction path — "punch through" — that the gate can no longer control. The claimed fix is a p-type boron "pocket implant" under the channel (and optionally ~1 µm into the drift region), which extends the depletion path, raises breakdown voltage, and simultaneously grades the n− drift region (lower sheet resistance near the drain, higher near the gate). The patent reports that with G = 3 µm and LD = 3 µm, V_BD exceeds ~67 V, versus ~22 V for a comparable conventional device.

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Independent Claims — Plain-Language Overview

There are two independent claims (1 and 5); claims 2–4 depend from 1, and claims 6–9 depend from 5.

Claim 1 — The drive transistor itself

A MOSFET drive transistor for switching thermal ink jet heating elements, built on a p-type silicon substrate that already contains the printhead circuitry, comprising:

1. An elongated drain region connected to a respective heating element.
2. Source regions spaced from the drain and connected to ground.
3. An elongated, oval-shaped gate region with elongated parallel portions, connected to the printhead addressing circuitry; signals selectively applied to the gate turn the transistor on, allowing a current pulse to the selected heating element to eject an ink droplet.
4. Channel regions formed under the parallel portions of the gate, adjacent to and between the source and drain.
5. Drain structure: a lightly doped n− drift region offset from an n+ implanted contact region.
6. Source structure: each source is an n+ implanted region.
7. The key limitation: a p-type pocket implant underneath the entire channel region of each gate, extending from the channel into the substrate to an adjacent source and into the drift region for about 1 µm.
8. Stated result: shorter source-to-drain spacing without loss of breakdown voltage, enabling a suitable drive transistor for high-resolution printheads.

Claim 5 — The printhead incorporating the transistor

An improved high-resolution thermal ink jet printhead of the conventional type: an array of heating elements on a dielectric layer over a silicon substrate, with a channel plate bonded to it forming capillary-filled ink channels connecting nozzles to a reservoir, each channel having a nozzle and a heating element a set distance from that nozzle, each heating element fired by signals from on-substrate circuitry including switching driver transistors. The improvement is that the driver transistors each have:

• an elongated drain region with a lightly doped n− drift region offset from an n+ contact region, connected to a respective heating element;
• grounded source regions on opposing sides of the drain;
• an elongated gate region between the source and drain, connected to addressing means; and
• a channel region in the substrate beneath the gate;

and the driver transistor has a p-type pocket implant beneath at least the entire gate region, which extends into the drift region for about 1 µm.

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Dependent Claims (for completeness)

• Claim 2 — Pocket implant extends laterally past the drift region edge to overlap part of it, producing a graded drift region: lower sheet resistance in the un-overlapped portion, higher sheet resistance where overlapped.
• Claim 3 — Pocket implant is boron, above 1×10¹⁶ ions/cm³, depth at least 1.0 µm.
• Claim 4 — Gate length G = 3 µm, drift length LD = 3 µm, V_BD > 40 V.
• Claim 6 — Each heating element has two driver transistors with drains in parallel; sources parallel and on opposing sides of each drain.
• Claim 7 — Nozzle-to-nozzle spacing of at least 400 per inch.
• Claim 8 — Pocket implant is boron at about 2×10¹⁶ ions/cm³, depth about 1.8 µm.
• Claim 9 — G = 3 µm, LD = 3 µm, V_BD > 65 V.

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Procedural History (from the record)

• 1997-10-17: Filed and assigned to Xerox Corporation (assignment recorded 1997-10-17, reel/frame 008784/0216).
• 1998-07-03: EP application EP98305299 filed (published as EP0909649A2, extended EP0909649A3 on 1999-12-22); status withdrawn.
• 1998-10-15: JP application JP10293763 filed (published JPH11192704A on 1999-07-21); status withdrawn.
• 2000-08-15: US patent granted.
• 2002-06-28 / 2003-10-31: Security interests granted to Bank One, N.A. and JPMorgan Chase Bank (Xerox collateral arrangements).
• Maintenance fees paid at years 4, 8 (with surcharge for late year-7 payment), and 12.
• 2017-10-17: Anticipated expiration (max term, filed before June 8, 1995 rules; measured from 1997-10-17 filing, 20 years).
• 2022-09-07: Release by secured party (JPMorgan Chase, as successor to Bank One) recorded 2022, effective 2022-08-22 — a lien release, not an ownership change.

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Forward Citations of Note

The patent is cited in at least 41 later documents, including:

• US 6,274,896 B1 — Lexmark, "Drive transistor with fold gate" (2001).
• US 6,666,545 B2 / US 2004/0124449 A1 / US 6,841,830 B2 — ITRI, driver transistor structures for ink jet head chips.
• US 7,118,202 B2 and related Silverbrook Research filings — "Thermal ink jet printhead with drive circuitry offset from heater elements."
• US 6,976,185 B2 / US 6,883,894 B2 — Hewlett-Packard, printhead integrated circuits and looped gate transistor structures.
• EP 1 694 508 B1 (Lexmark, "Microfluid ejection device having efficient logic and driver circuitry") cites US 6,102,528 as background art.
• Later LDMOS citations (e.g., US 10,403,750 B2; US 10,622,474 B2, SMIC) show the pocket/graded-drift concept resonating outside ink jet.

Cited prior art (examiner): US 4,308,549; US 4,947,192; US 5,010,355; EP 0 494 076 A2; US 5,159,353; US 5,517,224; US 5,463,237; EP 0 717 448 A1; EP 0 736 898 A2; US 5,753,958; US 5,790,154. Non-patent literature: Silicon Processing for the VLSI Era, Stanley Wolf, Vol. 3, pp. 232–245 (1995).

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Confidence and Caveats

• High confidence on bibliographic data, abstract text, and claim scope — derived from the full issued specification and claims of US 6,102,528, corroborated by Justia, EveryPatent, and the issued PDF.
• High confidence that the patent is expired (anticipated expiration 2017-10-17), making it unenforceable now; no live infringement exposure exists.
• Explicit uncertainty: I found no evidence of any district court action, PTAB proceeding, or CAFC appeal involving this patent, including nothing on a 2026 CAFC docket. I am not able to affirm that no such proceeding exists — only that none surfaced in the sources queried.
• Do not confuse this document with JP Patent No. 6102528 B2 (Fujitsu, signal processing) or with similarly numbered US patents. The number was checked literally and only the Xerox ink jet patent matches the requested subject matter.
• Claim 4's "greater than 40 volts" recitation is notably lower than the specification's stated operational requirement (>60 V) and the reported data for G = 3 µm / LD = 3 µm (~67.5 V); this is a claim-drafting observation, not a correction.

Primary sources: https://patents.google.com/patent/US6102528/en · https://patents.justia.com/patent/6102528 · http://www.everypatent.com/comp/pat6102528.html · https://patentimages.storage.googleapis.com/93/69/d4/e5c82d46747f8f/US6102528.pdf

I'll research litigation involving US Patent 6,102,528. Let me run several searches.

Let me search more targeted litigation databases.

Litigation Search Results for US Patent 6,102,528

Bottom line: I found no litigation (district court, ITC, or CAFC) naming US Patent 6,102,528 as an asserted patent. Before concluding that, here is what I searched, what I found, and the important caveats.

What the patent is (context for the search)

US 6,102,528 ("Drive transistor for an ink jet printhead"), filed 1997-10-17, granted 2000-08-15, original assignee Xerox Corporation, inventors Cathie J. Burke, Biay-Cheng Hseih, and William G. Hawkins. It is a thermal-inkjet printhead drive-transistor patent (pocket implant beneath the channel region). It expired 2017-10-17 (anticipated expiration; "Expired - Lifetime" status). It has foreign family members EP0909649 and JPH11192704.

Results by source category

Near-miss results I deliberately excluded (they are not this patent)

1. Xerox v. Hewlett-Packard — Xerox sued HP in U.S. District Court in Rochester, NY, alleging certain HP DeskJet/PhotoSmart/OfficeJet printhead cartridges infringed a Xerox patent Xerox said it "filed in 1991." That priority/date does not match US 6,102,528 (filed 1997), so this is a different patent and is not a 6,102,528 case.
2. Dynamic Hosting Company LLC v. Xerox Corp., E.D. Tex. Case No. 2:14-cv-01079 — a Xerox defendant case over unrelated technology.
3. Monument Peak Ventures, LLC v. Xerox Corp., E.D. Tex. Case No. 2:21-cv-00345-JRG-RSP — unrelated portfolio assertions.
4. JP6102528B2 (Fujitsu) and DI 6102528-3 (Brazilian design) — different jurisdictions and different subject matter; not the U.S. patent.
5. IPR2023-00313 (Canon U.S.A., Inc.) — an IPR proceeding; the number appears only inside an exhibit's reference table (see caveat above).

Requested case-by-case table

Caveats and confidence

• Confidence that no litigation exists: moderate-to-high but not certain. I could not directly query the paywalled/registered litigation databases (Unified Patents Portal, Docket Navigator, PACER) in this session; my searches relied on indexed public web content. A full, negative-proof search would require running "6102528" (and the patent's continuations/family) directly in Docket Navigator, PACER, and the ITC EDIS database.
• The patent expired in 2017, which reduces (but does not eliminate) the likelihood of post-2017 assertions; any suit would most likely have been filed between 2000 and 2017.
• Because of the strict instruction not to auto-correct identifiers, I have treated "6102528" literally throughout and have flagged each same-numbered but distinct document (JP6102528B2, DI 6102528-3) rather than merging them.

If you need definitive confirmation, the recommended next steps are: (1) query PACER for "6,102,528" and "6102528"; (2) query the ITC EDIS for Section 337 investigations involving Xerox inkjet printhead patents; and (3) run the patent number in Docket Navigator or the Unified Patents litigation portal, which would surface any sealed or settled NPE suits that public web indexing may not capture.

I'll verify the ODP result with web searches before defaulting to "no PTAB activity."

Let me run a few more targeted searches to close out the possibility of unindexed proceedings.

Proceedings overview

Zero AIA trial proceedings on file. US 6,102,528 has never been the subject of an IPR, PGR, or CBM review: the USPTO Open Data Portal structured block returns no AIA trial proceedings, and targeted web searches (patent number alone; patent number + IPR/PGR/CBM prefixes; patent number + reexamination; PTAB E2E queries) surfaced no petition, institution decision, FWD, or reexam control number naming this patent. Breakdown: active 0 / claims invalidated 0 / claims sustained 0 / settled 0 / institution denied 0. I also found no ex parte or inter partes reexamination for it — though ODP's trial API does not cover reexams, so treat that second point as a search result rather than a certified absence.

Defensive posture: this is not "hardened by surviving PTAB attack" — it is untested at the PTAB and, more importantly, expired. The patent's anticipated expiration was 2017-10-17, and its legal status in the record is "Expired – Lifetime." That, not any PTAB outcome, is the fact that should drive your defense. Any demand letter asserting 6,102,528 against current conduct is asserting an expired patent; damages for direct infringement end at the expiration date, and the § 286 six-year lookback cannot reach past 2017-10-17. There is also no § 315(e)(2) estoppel against anyone, because no IPR was ever filed — every prior-art ground remains available in district court, including grounds an IPR petitioner could have raised.

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No proceedings to report

There are no proceeding numbers to populate here, and I will not manufacture any. For the record, the patent's only post-issuance activity in the file is administrative:

Family: US 08/953,656 (parent); EP 0909649 A2/A3 (withdrawn); JP H11192704 (withdrawn). Original and current assignee: Xerox Corporation. Inventors: Cathie J. Burke, Biay-Cheng Hseih, William G. Hawkins.

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Strategic summary

Claim status — CANCELED vs. SUSTAINED vs. UNTESTED. All nine claims — independent claims 1 and 5, and dependent claims 2–4 and 6–9 — remain as issued. Untested is the only accurate label: no claims were canceled, none were confirmed at the PTAB, and none were amended (no reissue and no reexam certificate appears on the record). Independent claim 1 covers the MOSFET drive transistor itself (pocket implant beneath the channel, extending into the drift region for about 1 µm); independent claim 5 covers an "improved high resolution thermal ink jet printhead" incorporating such a transistor, including the two-drivers-in-parallel configuration of claim 6 and the ≥400 nozzles-per-inch spacing of claim 7. There is no surviving-claim list to give you, because there is no narrowing — the claims are simply the original issued claims, and the patent is expired.

Estoppel landscape. There is none. Section 315(e)(2) estoppel attaches only to a petitioner (and its real parties in interest and privies) that obtained a final written decision — and no IPR was ever instituted, so no FWD exists and no party is statutorily estopped from anything. Practically, this cuts both ways and generally favors a defendant: the entire prior-art universe is on the table in district court, including art that would have been "reasonably could have raised" material in an IPR. The trade-off is that you also get no roadmap — there is no petition, no Board claim construction, and no FWD claim-construction holding to leverage. The references of record that were considered during prosecution (US 4,308,549; US 4,947,192; US 5,010,355 EP 0494076; US 5,159,353; US 5,517,224; US 5,463,237; EP 0717448; EP 0736898; US 5,753,958; US 5,790,154, plus Silicon Processing for the VLSI Era, Wolf, vol. 3, pp. 232–245 (1995)) are the baseline, not the ceiling.

Pattern signals. The absence of PTAB activity is real signal, and it is explained by context rather than by invalidity: 6,102,528 is a 1997-filed Xerox printhead driver patent that expired in 2017, and its active commercial life was spent inside Xerox's own cartridge business rather than in licensing campaigns. It drew no Unified Patents or other defensive-aggregator petition and no competitive IPR. What it did do is become heavily cited prior art — the "Cited By" set runs to 15 publications and then 41 family members, including Lexmark, HP, Canon, ITRI, BenQ, Silverbrook Research, Richtek, NXP and SMIC work on inkjet driver and LDMOS structures (e.g., US 6,274,896 "Drive transistor with fold gate"; US 6,666,545; US 7,118,202; US 9,741,793). So while 6,102,528 was never a PTAB defendant, its disclosure is thoroughly embedded in the field's prior art — which is a useful invalidity resource against other patents, and a useful backdrop if anyone ever claims this patent's pocket-implant teaching as novel in a later filing. I found no evidence of litigation asserting this patent; I cannot confirm the absence of such suits with high confidence, because district court dockets were not exhaustively searched here, and you should treat that point as unresolved rather than as verified.

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Recommended next steps

1. Lead with expiration, not invalidity. Confirm the check digit and issue data against US 6,102,528 on Google Patents and USPTO Patent Center. Filed 1997-10-17, granted 2000-08-15, ant anticipated expiration 2017-10-17. If a demand letter targets conduct occurring after that date, the patent provides no basis for direct infringement damages, and § 286 caps any lookback at six years before filing — which for a 2026 assertion still cannot reach post-expiration conduct. Also check for any term extension or reissue via the Patent Center "Post Issuance" tab; the ODP record shows none, but verify before relying on it.
2. There is no FWD to cite, so don't imply one. Unlike the usual posture, you cannot quote a Board disposition here. Your invalidity story must be built from scratch in district court or, if you are within the § 315(b) one-year window and have Article III standing despite expiration, from your own IPR petition — the Board does accept petitions against expired patents, and claim construction then follows Phillips. No time bar under § 315(b) exists for a defendant not yet served.
3. Mine the citation trail for § 102/§ 103 ammunition. The 11 examiner-cited references and the 15 forward citations listed on the Google Patents page are the obvious starting set, with Wolf vol. 3, pp. 232–245 as the background-teaching reference. Given the patent is expired, you are not defending against a live damages claim so much as cleaning up a portfolio-assertion threat — a validity challenge pursued for fee-shifting or declaratory posture should be weighed against the cost, since there is no ongoing royalty exposure to defeat.
4. Verify the "no PTAB activity" conclusion yourself before filing anything that depends on it. Run PTAB E2E and the USPTO PTAB Decisions search filtered on trial number and patent number, and check the CourtListener docket for any CAFC appeal that could only exist if a Board or district decision preceded it. Absent that, the operative statement for your file is: no AIA trial proceedings on file, no reexam found, and the patent is expired as of 2017-10-17.

I'll research this patent's ownership chain across multiple sources before assembling the report.

Let me search for litigation history and any NPE activity tied to this patent.

Let me check for any litigation or NPE assertion activity and confirm Xerox's corporate status.

I've hit my research step limit. Based on the authoritative patent text (Google Patents legal events) and the cross-references I was able to retrieve, here is the reconstructed chain. One caveat up front that materially affects the "repeat correspondent" signal: the record set I retrieved (Google Patents legal events, mirrored from USPTO) lists reel/frame, conveyance, parties, and dates — but does not expose the correspondent/attorney of record for any entry, and I was unable to pull the USPTO Assignment Center detail pages directly. I flag that where it matters rather than guessing.

Inventors

All three listed Rochester-area addresses trace to Xerox's Webster, NY / Rochester research-and-manufacturing footprint, and all three executed an assignment of interest to Xerox Corporation effective 1997-10-15 (recorded 1997-10-17, Reel 008784/0216). Employer is therefore determinable as Xerox Corporation for all three.

• Unusual patterns: None observed. There is no record of any inventor executing a later assignment or departure-related transfer, and no separate inventor-held interest was ever conveyed to a third party. The names are rendered slightly inconsistently across the US grant and the EP/JP family (e.g., "Hseih," "Hselh"), which is a transcription artifact, not an ownership signal.

Original assignee

Xerox Corporation (Connecticut; Rochester, NY / Stamford, CT), named on the face of the issued patent and as original assignee in the USPTO assignment record (Reel 008784/0216).

• Product embodiment: The patent claims a drive transistor for a high-resolution thermal ink jet printhead integrated on the silicon substrate with the heating elements and addressing circuitry. Xerox was an operating manufacturer of thermal ink jet printheads and inkjet printers in this era, so the claimed subject matter maps to Xerox's own printhead line rather than to a licensing abstraction. I could not, within my research budget, verify a specific commercial part number embodying the claims — that specific product-level confirmation is unclear.
• Primary line of business: Document technology — printers, multifunction devices, copiers, and related supplies/services.
• Current status: Operating. Xerox Corporation is now a wholly owned subsidiary of Xerox Holdings Corporation following a holding-company reorganization completed July 31, 2019 (per Xerox's 2019 Form 10-Q and Form 8-K). Publicly traded (NASDAQ: XRX). It is not dissolved and did not file Chapter 7/11. Note a financial-distress chapter adjacent in time to the security records below: Xerox negotiated large secured credit facilities around 2000–2002 (the Bank One and JPMorgan liens below), but this was a going-concern refinancing, not a bankruptcy sale of patents.

Assignment timeline

All four records below are the complete set of USPTO assignment events surfaced for US 6,102,528. Note the patent's normal term ran to 2017-10-17 (anticipated expiration), so any post-2017 assignment would relate to an expired right.

• 1997-10-15 (executed) / recorded 1997-10-17 — Reel 008784/0216

  • Conveyance: Assignment of assignors' interest
  • Assignor: Cathie J. Burke; Biay-Cheng Hseih; William G. Hawkins (individually)
  • Assignee: Xerox Corporation
  • Correspondent: Not available in the retrieved record set. The Google Patents legal-events mirror does not carry the correspondent/attorney of record, and I could not open the USPTO Assignment Center detail page to capture it. No recurrent-correspondent flag can be asserted for this chain on the available data.
  • Context: Original inventor-to-employer assignment at filing — the baseline ownership record.

• 2002-06-21 (executed) / recorded 2002-06-28 — Reel 013153/0001

  • Conveyance: Security Interest (not an ownership transfer)
  • Assignor: Xerox Corporation
  • Assignee: Bank One, NA, as Administrative Agent (Illinois)
  • Correspondent: Not available in the retrieved record set.
  • Context: Securitization — collateral grant of Xerox patent rights to a bank syndicate's administrative agent under a corporate credit facility. Xerox remains record owner; no title transfer.

• 2003-06-25 (executed) / recorded 2003-10-31 — Reel 015134/0476

  • Conveyance: Security Agreement (not an ownership transfer)
  • Assignor: Xerox Corporation
  • Assignee: JPMorgan Chase Bank, as Collateral Agent (Texas)
  • Correspondent: Not available in the retrieved record set.
  • Context: Securitization — a second, successor collateral lien covering the same Xerox patent estate, recording JPMorgan Chase as collateral agent.

• 2022-08-22 (executed) / recorded 2022-09-07 — Reel 066728/0193

  • Conveyance: Release by Secured Party
  • Assignor: JPMorgan Chase Bank, N.A., as successor-in-interest administrative agent and collateral agent to JPMorgan Chase Bank
  • Assignee: Xerox Corporation
  • Correspondent: Not available in the retrieved record set.
  • Context: Release of the prior security interests — extinguishment of the lien, restoring Xerox's record position free of encumbrance. This is a cleanup, not an acquisition.

Net ownership effect: the patent was never assigned away from Xerox Corporation. The only non-initial records are (a) two security interests granted by Xerox to its lenders, and (b) the lenders' later release back to Xerox. No entity other than Xerox and its secured lenders ever appears as assignee.

Timeline diagram

timeline
    title Ownership of US 6102528
    1997 : Inventors assign to Xerox Corporation
    2002 : Security interest granted to Bank One NA
    2003 : Security agreement to JPMorgan Chase
    2017 : Patent reaches full term expiry
    2022 : Lenders release security back to Xerox

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The chain contains no licensing-only LLC. The only assignees besides Xerox are Bank One, NA and JPMorgan Chase Bank, acting as secured lenders/agents, not owners. Reels 013153/0001 and 015134/0476 are lien records, and Reel 066728/0193 returns the encumbrance to Xerox.

2. Known asserter in the chain — Not present. Neither Bank One, NA (now part of JPMorgan Chase) nor JPMorgan Chase Bank appears on any NPE/asserter list; both are commercial banks. No Acacia, Marathon, IV, Wi-LAN, Conversant, Vringo, Pendrell, or similar entity appears at any reel/frame.

3. Repeat correspondent across the chain — Unclear / not determinable. If a single recording attorney recurs across Reels 008784/0216, 013153/0001, 015134/0476, and 066728/0193 that would normally be the sharpest tell, but the correspondent of record is not exposed in the record set I retrieved, and I could not open the Assignment Center detail views to capture it. I will not infer it. This is a data gap, not a negative finding — see the verification link below to pull the correspondent fields directly.

4. Cascading transfers — Not present. There are no chained LLC-to-LLC assignments. The events span 1997 → 2002 → 2003 → 2022, and only the 1997 entry changes ownership at all.

5. Pre-litigation transfer — Not present. No infringement suit naming US 6,102,528 was surfaced, and no assignment sits within six months of any suit. There is no litigated transfer window to assess.

6. Bankruptcy fire-sale — Not present. Xerox did not file Chapter 7/11, and no patent sale in bankruptcy proceedings is recorded. The 2002/2003 security interests correspond to secured corporate financings during Xerox's early-2000s distress, which is a refinancing, not a fire-sale conveyance.

7. Privateering — Not present. There is no transfer from Xerox to a third-party NPE asserting against Xerox's competitors. Title never left Xerox.

8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. It terminates at the original operating company following a lien release.

Verdict

Insufficient data (with the substantive finding that the chain evidences no NPE activity).

The complete recorded chain — Reel 008784/0216 (inventors → Xerox, 1997), Reel 013153/0001 and Reel 015134/0476 (security interests granted by Xerox to its lenders, 2002/2003), and Reel 066728/0193 (lender release back to Xerox, 2022) — contains no ownership transfer away from Xerox Corporation and matches no NPE signal. The patent ran to its full 2017-10-17 term still in Xerox's hands, so there is no asserter chain to evaluate. I rate this "Insufficient data" rather than "operating-company assertion" because the verdict rubric requires an active assertion by a product-shipping owner, which is absent; the honest characterization is "operating-company-owned, non-asserting, expired." The one open item is the correspondent of record, which I could not retrieve.

Verify (single source of record):

• USPTO Patent Assignment Search — search by patent number 6102528: https://assignmentcenter.uspto.gov/ (mirror: https://assignment.uspto.gov/patent/index.html)
• Google Patents legal-events view (the mirror used here): https://patents.google.com/patent/US6102528/en

Correction/grounding note: the correspondent (attorney/firm) field is the specific element the assignment requires for signal #3, and it is the one element I could not confirm from the available sources — I have deliberately left it as a data gap rather than speculating.

I'll search for the patent and its cited prior art references to ground my analysis.

Let me gather details on the remaining cited references.

Prior‑Art Analysis — U.S. Patent No. 6,102,528

1. The patent under review (record confirmed)

Sources: https://patents.google.com/patent/US6102528/en ; http://www.everypatent.com/comp/pat6102528.html ; USPTO patent images (US6102528.pdf).

The inventive core (claims 1, 5 + dependents 2–4, 8–9): a lateral NMOS drive transistor for a thermal ink‑jet printhead having an elongated drain with a lightly doped n⁻ drift region offset from the n⁺ contact region, grounded source regions flanking the drain, an elongated oval gate over the channel, and — the point of novelty — a p‑type "pocket implant" beneath the entire channel that extends into the drift region for about 1 µm, producing a graded drift region. This allows a shorter source‑to‑drain spacing (e.g., gate length G = 3 µm, drift length LD = 3 µm) while retaining breakdown voltage (V_BD > 65 V for claims 4/9) and preventing punch‑through.

2. The cited references (the § 102 art of record)

All of the following are listed under "Patent Citations" on the face of US 6,102,528 and in the USPTO record:

Sources: face of US 6,102,528 (Google Patents / EveryPatent citation tables); USPTO image bundle US6102528.pdf; corroborating records for US4308549, US4947192, US5159353, US5517224.

3. Anticipation analysis under 35 U.S.C. § 102

Bottom line up front: None of the cited references appears to anticipate any of claims 1–9. Under § 102 a single reference must disclose every element of the claim as arranged. The single element that is missing from every reference of record is the p‑type pocket implant beneath the entire channel region that extends into the drift region for about 1 µm (claim 1) / into the drift region (claim 5), together with the resulting graded drift region (claim 2) and the specified implant concentrations/depths (claims 3, 8). The references are § 102 background art and are far stronger as § 103 (obviousness) art.

Reference‑by‑reference:

US 4,308,549 (Yeh / Xerox) — Discloses a circular HVFET with a resistive/intermediate gate to spread the field. It teaches source/channel implants and geometry variation for voltage handling, but it is a discrete high‑voltage device, not an ink‑jet drive transistor, and it has no p‑type pocket implant under the channel extending into a drift region. It cannot anticipate claim 1 or 5 (no printhead/heating‑element environment, no pocket implant). It is relevant only to the general concept of field‑spreading in HV devices.

US 4,947,192 and US 5,010,355 (Hawkins et al. / Xerox) — These are the printhead‑environment references, expressly incorporated by reference. US 4,947,192 shows an n‑drift self‑aligned to the polysilicon gate (see its FIG. 3 discussion: "lightly doped source 80 and drain 82 … self‑aligning the n‑drift layer 82 to the polysilicon gate 78 … breakdown voltage … greater than 75 volts"). That discloses the n⁻ drift offset from the n⁺ contact and the printhead integration, but not the recited p‑type pocket implant extending under the channel into the drift region. US 5,010,355 is directed to ionic passivation, not transistor channel/drift structure. Neither anticipates claims 1–9.

EP 0 494 076 A2 (Xerox) — Monolithic printhead IC (logic + drivers + resistors). Same environment, no pocket implant. No anticipation.

US 5,159,353 (Fasen et al. / HP) — Integrated MOSFET drivers with an oxide/nitride gate scheme. It addresses gate‑oxide formation, not a channel/drift pocket implant. No anticipation.

US 5,463,237 (Funaki / Victor Company of Japan) — A MOSFET with a depletion layer. This is the closest of the "device‑physics" references because it concerns depletion‑region/drift engineering, but the record shows no disclosure of a p‑type pocket implant positioned beneath the entire channel and extending ~1 µm into an n⁻ drift region in a printhead driver. No anticipation of the claims.

US 5,517,224 (Kaizu et al. / Canon) — A heat‑generator driver in which the portion of the main electrode contacting the channel is a high‑resistance region. This is a drift/high‑resistance‑region teaching in the ink‑jet context, but it is a different structure from the claimed p‑type pocket implant; it does not disclose a p‑doped region beneath the channel extending laterally into the drift region for ~1 µm, nor the graded drift region of claim 2. No anticipation.

EP 0 717 448 A1 and US 5,753,958 (Sun Microsystems) — Asymmetric, low‑power MOS devices / back‑biasing of asymmetric MOS devices. These concern asymmetric source/drain and back‑bias architectures, not a printhead drive transistor with a channel‑underlying pocket implant grading the drift region. No anticipation.

EP 0 736 898 A2 (Matsushita) — BiCMOS process integration; unrelated to the claimed printhead drive‑transistor structure. No anticipation.

US 5,790,154 (Mitani et al. / Hitachi Koki) — Manufacturing an ink‑ejection recording head. Environment‑only; no pocket‑implant disclosure. No anticipation.

Wolf, Silicon Processing for the VLSI Era, Vol. 3 (1995) — A printed publication of record. A textbook cannot anticipate claims drawn to a specific printhead drive‑transistor layout unless it disclosed the exact claimed combination; it does not disclose the claimed pocket‑implant geometry/concentration parameters. It is background/teaching evidence at most.

4. What the cited art does support — and the correct statutory framing

• § 102: No cited reference anticipates any of claims 1–9. Each lacks the p‑type pocket implant beneath the entire channel region extending into the drift region for about 1 µm (claims 1 and 5) and the dependent limitations (concentration >1×10¹⁶ / ≈2×10¹⁶ cm⁻³, depth ≥1.0 µm / ≈1.8 µm, G=3 µm, LD=3 µm, V_BD > 40 V / > 65 V — claims 3, 4, 8, 9).
• § 103: The references of record (especially US 4,947,192, US 5,159,353, US 5,517,224, and US 5,463,237) collectively supply the printhead environment, the n⁻ drift offset from the n⁺ contact, and general HV/depletion engineering — the elements a PHOSITA would have known. The non‑obvious contribution of US 6,102,528 is the recognition that a single masked boron "pocket" implant (placed through the LOCOS mask before field oxidation and driven ~1.8–2 µm) simultaneously suppresses punch‑through and laterally counter‑dopes the drift region to grade it, shrinking the transistor to a 3 µm/3 µm G/LD device at >65 V. That is the strongest § 103 battleground, not § 102.
• The patent also distinguishes its structure from sub‑micron CMOS "punch‑through" implants (which run source‑to‑drain), stressing that its pocket implant stops short of the drain to preserve junction breakdown — a distinction that the cited art does not appear to teach against.

5. Confidence and caveats

• High confidence: the identity, dates, assignment, claims, and citation list of US 6,102,528 (verified against the Google Patents record and the USPTO/EveryPatent citation tables).
• High confidence: no reference of record discloses the claimed pocket‑implant feature; therefore no § 102 anticipation of claims 1–9.
• Lower confidence / not fully verified in this session: the internal disclosure details of US 5,463,237 (Funaki), EP 0 717 448 A1 and US 5,753,958 (Sun Microsystems), EP 0 736 898 A2 (Matsushita), EP 0 494 076 A2, and US 5,790,154 (Mitani). My characterizations of these rely on their titles and the snippets retrieved; a full‑text review would be needed before asserting definitively that they contain no pocket‑implant teaching. If you want, I can pull the full claim sets and drawings of those five and re‑run the element‑by‑element § 102/§ 103 matrix.
• Note the literal‑identifier rule: all numbers above are reproduced exactly as they appear (including "Hseih," "JPH11192704A," "US 5,463,237," and the two European "A1/A2/A3" kind codes); I have not normalized or corrected any of them.

Primary URLs: https://patents.google.com/patent/US6102528/en ; https://patents.google.com/patent/US4308549 ; https://patents.google.com/patent/US4947192 ; https://patents.google.com/patent/US5159353 ; https://patents.google.com/patent/US5517224 ; http://www.everypatent.com/comp/pat6102528.html

I'll ground this analysis by verifying the cited prior art references before building the § 103 combinations.

Let me verify the printhead-integration references and the Canon driver reference.

Obviousness Analysis — U.S. Patent 6,102,528

Patent: US 6,102,528 A, "Drive transistor for an ink jet printhead"
App. No.: US 08/953,656 · Filed/Priority: 1997-10-17 · Granted: 2000-08-15
Assignee: Xerox Corp. (original) · Inventors: Cathie J. Burke, Biay-Cheng Hseih, William G. Hawkins
Source of record: https://patents.google.com/patent/US6102528/en

Scope note / limits of this analysis. I worked only from the prior-art material listed on the patent page ("Patent Citations," 11 references; "Non-Patent Citations," 2 entries). I did not use any "Cited By" document as prior art — every item in that list has a priority date after 1997-10-17 and therefore postdates the critical date. I also did not have access to the actual file wrapper (Office Actions / applicant remarks), so this is a fresh reconstruction of § 103 grounds, not a restatement of what the examiner applied. Where I could not retrieve full text of a reference, I say so and rely on the '528 specification's own characterization of that reference (which is itself an admission as to its disclosure).

Note on identifiers, read literally: the specification uses reference numeral 38 for the drift region in one passage ("extending into the drift region 38") while using 36 for the drift region in the FIG. 4 discussion. I treat the claim term "drift region" as controlling and do not correct the numeral.

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I. Legal framework and level of ordinary skill

• Governing law: Pre-AIA 35 U.S.C. § 103(a) (application filed 1997-10-17). Obviousness is judged from the perspective of a person having ordinary skill in the art (PHOSITA) at the critical date, with the reference combinations and motivations assessed under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), and the predictable-result / known-technique rationales.
• PHOSITA (proposed): a B.S. in electrical engineering or materials science plus 3–5 years of experience in monolithic integration of power/lateral MOS devices and thermal ink jet printhead substrates, or equivalent; familiar with LOCOS isolation, LDD/drift-region engineering for high-voltage lateral MOSFETs, threshold/punchthrough implants, and printhead driver layout constraints.
• Prior-art status of the cited references (all pre-date 1997-10-17):
  • § 102(b): US 4,308,549 (1981-12-29); US 4,947,192 (1990-08-07); US 5,010,355 (1991-04-23); EP 0 494 076 A2 (1992-07-08); US 5,159,353 (1992-10-27); US 5,463,237 (1995-10-31); EP 0 717 448 A1 (1996-06-19); EP 0 736 898 A2 (1996-10-09); Wolf, Silicon Processing for the VLSI Era, Vol. 3 (1995).
  • § 102(a)/(e): US 5,517,224 (granted 1996-05-14); US 5,753,958 (filed 1995-10-16, granted 1998-05-19 — § 102(e) as of its filing date); US 5,790,154 (priority 1995-12-08, granted 1998-08-04 — § 102(e) as of its filing date).

Bottom line up front: no single reference discloses the pocket implant that extends from under the entire channel into the drift region (≈1 µm) to simultaneously suppress punchthrough and grade the drift, so the claims are not anticipated. Claims 1, 3, 4, 5, 7, 8 and 9 are, in my assessment, reasonably strong § 103 candidates on the combinations below. Claims 2 and 6 are progressively weaker for the reasons in § V.

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II. Claim 1 decomposed (independent claim, and the template for claims 3, 4)

Claims 2, 3, 4 depend from claim 1; claim 5 is an independent printhead-level claim reciting the same driver architecture plus "pocket implant beneath at least the entire gate region, wherein the p-type pocket implant extends into the drift region for about 1 µm"; claims 6–9 depend from claim 5.

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III. Prior-art reference map (from the page's Prior Art section)

Device-physics / power-MOS references

• US 4,308,549 (Xerox, 1981) — circular high-voltage FET; central drain, concentric annular field plate/gate/source; closed geometry to save area (per the '528 spec., col. describing the reference).
• US 5,463,237 (Victor Company of Japan, 1995-10-31) — MOSFET with an engineered depletion layer: a first-conductivity-type region beneath the gate insulating film, a second-conductivity-type region beneath it, and third regions defining depletion widths; expressly concerned with controlling the depth/lateral extent of depletion regions (https://patentimages.storage.googleapis.com/9a/fa/10/3398e4175276d4/US5463237.pdf).
• EP 0 717 448 A1 (Sun Microsystems, 1996-06-19) — asymmetric halo/pocket implants; pocket region of the same conductivity type as the bulk, opposite to source/drain; pocket dopant concentration "at least about 1 × 10¹⁶ atoms/cm³" (claims 9, 22); explicitly identifies punchthrough as the problem and proposes a "buried electrode" or "ground plane" extending underneath the channel region to suppress depletion growth (https://patents.google.com/patent/EP0717448A1/en). US counterpart disclosure: US 5,780,912 (Burr et al.), https://patentimages.storage.googleapis.com/b1/f2/3f/76a3b94bbcea73/US5780912.pdf.
• US 5,753,958 (Sun Microsystems) — back-biasing in asymmetric MOS devices; same pocket/halo device family.
• EP 0 736 898 A2 (Matsushita, 1996-10-09) — BICMOS fabrication.

Printhead-integration references

• US 4,947,192 (Xerox, 1990) — monolithic integration of MOS transistor switches with resistive heating elements on one silicon substrate; transistors and heaters from a single polysilicon layer over 1–4 µm field oxide (per the '528 spec.).
• US 5,010,355 (Xerox, 1991) — ionic passivation of the MOS circuitry exposed to ink.
• EP 0 494 076 A2 (Xerox, 1992) — monolithic integrated circuit chip for a thermal ink jet printhead.
• US 5,159,353 (Hewlett-Packard, 1992-10-27) — MOSFET drive transistors integrated into the printhead; gate oxide formed from the initial SiO₂/Si₃N₄ LOCOS stack.
• US 5,517,224 (Canon, 1996-05-14) — semiconductor device for driving a heat generator for an ink jet head; identifies the same problem the '528 patent addresses: with V⁺ of 30–40 V, "the electric field strength between a source and a drain is increased, and hot carriers thus occur… avalanche breakdown occurs" at the reverse-biased n-drain/p-type-well junction, and states an object of "decreasing the electric field strength between a source and a drain" (https://patents.google.com/patent/[US5517224A](/patent/US5517224A)/en; family EP 0 574 911 A3 describes a lateral DMOSFET in which "a portion of the first main electrode region which contacts the channel region is a high-resistance region").
• US 5,790,154 (Hitachi Koki) — ink ejection recording head manufacture.

Non-patent literature

• Wolf, Silicon Processing for the VLSI Era, Vol. 3: The Submicron MOSFET, pp. 232–245 (1995) — § 5.3, "Short-Channel Effects on Subthreshold Swing, S_t (Subsurface Punchthrough)," including experimental characterization, modeling, and the simultaneous surface-DIBL/subsurface-DIBL analysis (TOC confirmed at https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1558627](/patent/1558627)/download-documents?artifactId=KO-3z4mVqCQ450aCBzv380-apyBbbE4efOnq46LVdRgjORE6Qq0zBZc and https://www.docketalarm.com/cases/[PTAB](/ptab)/IPR2021-01321/).
  • Caveat: the cited page range covers the mechanism and modeling of subsurface punchthrough. The express "pocket-implant / LATIPS / halo" anti-punchthrough prescription sits in § 5.4 (immediately following), and Wolf Vol. 3 also covers hot-carrier-resistant structures (LDD) and well formation by shallow implant + drive-in. A petitioner relying on Wolf should cite the whole of Vol. 3, not just pp. 232–245, or pair pp. 232–245 with EP 0 717 448 A1 for the implant prescription. I flag this because it is the single most attackable link in Ground 1.

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IV. Proposed § 103 grounds

Ground 1 — US 5,517,224 + US 4,308,549 + Wolf Vol. 3 (claims 1, 3, 4)

Coverage. US 5,517,224 supplies the ink-jet-heat-generator driver context, the n-type drain / p-type well structure, the high-resistance (offset drift) region contacting the channel, and the express recognition that source-to-drain field strength and avalanche breakdown are the limiting problems in a 30–40 V driver. US 4,308,549 supplies the closed/oval high-voltage FET architecture with an elongated drain, spaced source, elongated gate, channel under the gate, and a dedicated drift region between channel and drain. Wolf Vol. 3, pp. 232–245 supplies the recognized physical phenomenon (subsurface punchthrough in short-channel devices) and the state of the art for suppressing it by placing additional dopant below the channel surface.

Motivation to combine (KSR factors).

1. Same field, same problem, same solution class. US 5,517,224 and US 4,308,549 are both lateral/high-voltage MOS structures for driving a thermal load; US 5,517,224 states the very problem (source-drain electric field, avalanche breakdown at the drain-well junction) that the '528 patent solves by shortening the drain-to-source spacing.
2. Design incentive / finite number of solutions. The '528 specification itself concedes the constraint that drives the combination: for 400 spi, transistor pitch P = 63.5 µm, and a prior-art double transistor requires ≥ 64 µm, so "the transistors must be fanned out behind the heaters." Once the objective of fitting the driver within the nozzle pitch is set, the available techniques for a lateral HV MOSFET are (i) shorten gate/drift, (ii) add a field plate, (iii) add a subsurface (punchthrough-suppressing) implant of the well conductivity type. Wolf documents (iii) as a standard technique; the closed/oval geometry of US 4,308,549 is expressly described as one that "occupies little space on a substrate."
3. Predictable result. Suppressing punchthrough by placing well-type dopant beneath the channel is a known technique with a known effect; a PHOSITA would expect improved punchthrough margin and hence the ability to shorten the channel/drift, and would expect the breakdown voltage to be maintained or improved.

Expected counter-argument. The ~1 µm extension of the pocket into the drift region and the resulting graded drift are not expressly disclosed in any single one of these three references (see Ground 2 and § V).

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Ground 2 — US 4,308,549 + EP 0 717 448 A1 (+ US 4,947,192 for the printhead context) (claims 1, 2, 3)

Coverage.

• The p-type pocket implant of claim 1 is taught by EP 0 717 448 A1: a "pocket region having the same conductivity type as the device's bulk region (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain," located "under" a source/drain region and proximate the channel region, expressly for punchthrough suppression, with a stated concentration of at least about 1 × 10¹⁶ atoms/cm³ (claim 22) — numerically satisfying claim 3's "above 1 × 10¹⁶ ions/cm³."
• EP 0 717 448 A1 additionally teaches the buried electrode / ground plane variant, "a region of relatively high dopant concentration extending underneath the channel region and having the same conductivity type as the well" for the express purpose of "suppress[ing] growth of depletion regions in the channel region and thereby prevent punch through." That is the closest art to claim 1's "pocket implant underneath the entire channel region."
• US 4,308,549 supplies the elongated/oval high-voltage gate and the n⁻ drift region offset from the n⁺ drain contact; US 4,947,192 supplies the p-type-substrate printhead containing both the heating elements and the addressing circuitry.
• Claim 2 (graded drift): EP 0 717 448 A1 also teaches intentional counterdoping — "at least a portion of said channel region includes counterdopant of the second conductivity type," "in a concentration of between about 10¹⁶ and 10¹⁸ cm⁻³" (claims 14–15), and that the counterdopant-bulk junction's depletion region is engineered not to reach the gate. Wolf Vol. 3 (well formation by shallow implant plus drive-in; LDD/hot-carrier-resistant structures) supplies the general knowledge that a graded dopant profile produces a more uniformly distributed lateral electric field.

Motivation. Both references address the same physical failure mode (punchthrough / drain depletion reach-through) created by reducing source-to-drain spacing; each proposes placing self-aligned dopant of the well type below the channel surface. Combining them to obtain a compact, high-breakdown driver is the predictable application of a known technique to a known device structure. For claim 2 specifically, the motivation is the classic one the '528 specification itself recites: "It is, of course, highly desirable to have a drift region sheet resistance which is low near the drain region and higher near the gate region because a graded n-drift region produces an electric field which is more evenly distributed," while admitting that "such a graded doping is difficult to manufacture because multiple masking and implant steps are required." That admission is a textbook KSR setup: the art recognized the desirable result; the alleged invention is the discovery that an implant step already being performed for punchthrough control can produce the grading by lateral diffusion.

Important limitation to brief honestly. EP 0 717 448 A1's own claim 11 states that the asymmetric halo region "does not extend into or under said channel region," and its summary says the pocket of the halo device "do[es] not extend underneath the entire channel region." A patentee will therefore argue that EP 0 717 448 A1 teaches away from the claim 1 configuration. The rebuttal is that (i) the buried-electrode/ground-plane embodiment of the same reference does extend underneath the channel region (so the reference as a whole, not selected claims, must be consulted), and (ii) the asymmetry restriction is a consequence of the reference's distinct objective — low-threshold-voltage, low-power logic devices — not a recognition of any incompatibility with high-voltage drivers, which is the standard for teaching away. This is a genuine fight, not a slam dunk.

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Ground 3 — US 5,463,237 + one printhead-integration reference (US 4,947,192, US 5,010,355, EP 0 494 076 A2, or US 5,159,353) (claims 1, 5)

Coverage. US 5,463,237 discloses a gate-insulating-film-covered structure in which a first-conductivity-type region extends below the gate insulating film (beneath the gate) with a second-conductivity-type region below it, plus third regions between that region and the source/drain, with the lateral widths of those third regions expressly specified relative to the depletion widths of the source and the pn junctions. This is a device whose operation is defined by engineered subsurface depletion geometry beneath the gate, i.e., the same physical design space as claim 1's pocket implant. Any one of US 4,947,192, US 5,010,355, EP 0 494 076 A2, or US 5,159,353 supplies the remaining printhead elements (heating elements on a dielectric on a silicon substrate, ink channels/nozzles, addressing circuitry, integrated MOS switches).

Motivation. US 5,463,237 is addressed to precisely the short-channel depletion-engineering problem that arises when a driver must be shrunk; the printhead references establish the same substrate-integration need. The combination of a depletion-engineered subsurface region with an integrated printhead driver is the predictable combination of a known device-design technique with a known integrated printhead platform.

Weakness. US 5,463,237's "first region" is not the same as a boron pocket implant driven to ~1.8–2 µm, and it does not describe drift-region counterdoping. This ground is stronger as a secondary/backup ground than as the primary one, and it is best used in a three-reference combination with Wolf or EP 0 717 448 A1.

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Ground 4 — Any of Grounds 1–3 + US 4,947,192 + EP 0 494 076 A2 + US 5,159,353 (claims 5, 6, 7)

Claim 5 is, in substance, claim 1 rewritten at the printhead level: heating elements on a dielectric layer on a silicon substrate, a channel plate with capillary-filled ink channels interconnecting nozzles with a reservoir, each heater a predetermined distance from its nozzle, addressing circuitry on the substrate, and a driver having an elongated drain with an n⁻ drift offset from an n⁺ contact, grounded source regions on opposing sides of the drain, an elongated gate between them, and a pocket implant "beneath at least the entire gate region, wherein the p-type pocket implant extends into the drift region for about 1 µm." US 4,947,192 supplies the monolithic heater + MOS switch + addressing integration on one substrate; US 5,010,355 and EP 0 494 076 A2 supply further printhead architecture detail; US 5,159,353 supplies the LOCOS-stack-based integrated drive transistor. The incremental subject matter of claim 5 is the pocket implant, addressed by EP 0 717 448 A1 (Ground 2).

Claim 6 (two driver transistors with drains connected in parallel; parallel source regions on opposite sides of each drain) is the weakest § 103 target in the patent. None of the eleven cited references is shown by the record here to disclose the two-transistor/three-source interdigitated arrangement for a printhead driver. The best available rationale is a KSR design-incentive / obvious-to-try argument: because drive current capability in a power MOSFET is increased by paralleling fingers, and because the '528 specification itself describes the alternative as a single transistor of doubled width W, a PHOSITA seeking to fit the driver inside the fixed nozzle pitch P would recognize paralleling devices as one of a finite number of predictable options (US 4,308,549's closed geometry is already premised on area minimization). That is a defensible but weaker argument, and dependent claim 6 is where I would expect a patentee to concentrate its non-obviousness rebuttal.

Claim 7 (nozzle-to-nozzle spacing ≥ 400 per inch) is a statement about the printhead's intended resolution rather than a structural difference from the art; the '528 specification's own numbers (400 spi = 63.5 µm pitch, 800 spi = 31.75 µm) are pure arithmetic consequences of resolution. It adds little independent weight.

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Ground 5 — Numeric/process limitations (claims 3, 4, 8, 9)

Claim 3 / claim 8 (boron; > 1 × 10¹⁶ ions/cm³; depth ≥ 1.0 µm / ≈2 × 10¹⁶ ions/cm³ at ≈1.8 µm): EP 0 717 448 A1 recites pocket dopant "at least about 1 × 10¹⁶ atoms/cm³" and, in a higher range, 1 × 10¹⁷ to 1 × 10¹⁸ atoms/cm³ (claims 9 and 22). The depth requirement is addressed by Wolf Vol. 3's treatment of well/region formation by shallow implant followed by drive-in — and the '528 specification itself concedes the practice: "it is not practical to implant to this depth with production implantation equipment. As a consequence, the pocket implant is implanted early in the fabrication process… and then driven to a depth of about 2 µm by the subsequent thermal cycles employed in wafer fabrication." Using the existing thermal cycle (here, the field oxidation step) as the drive-in, with no added mask or furnace step, is routine process integration.

Claim 4 / claim 9 (G = 3 µm, LD = 3 µm, V_BD > 40 V / > 65 V): these are results-effective amounts drawn from optimizations of known design variables. The '528 specification's own table shows that the prior-art transistor at G = 4 µm, LD = 3 µm already achieves V_BD = 64.5 V, and at G = 4.5/LD = 3 achieves 65.9 V. A claim to > 40 V (claim 4) is squarely met by the admitted prior art. A PHOSITA optimizing an HV driver for heater pulsing would arrive at a 3 µm/3 µm geometry by routine experimentation once the punchthrough constraint is removed; under In re Aller, a change in a known process parameter with a recognized result is prima facie obvious absent a showing of criticality.

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Ground 6 — Design-incentive ground cutting across all claims

The '528 specification supplies, on its face, the marketplace motivation that makes the whole family of claims obvious to try: increasing printed resolution (nozzles per inch) strictly reduces the space available behind each heater; the prior-art double driver needs ≥ 64 µm versus 63.5 µm available at 400 spi; fanned-out drivers increase die length by "4 µm multiplied by the number of heating elements," e.g. "+1024 µm" for a 256-nozzle array; and larger die reduce die-per-wafer yield and raise cost. Under KSR, a "design incentive" of this kind, coupled with a finite identified set of known techniques (shorten channel/drift; suppress punchthrough by subsurface implant; grade the drift), supports obviousness even without an express teaching to combine. Note that this is an admission in the specification, not an external reference.

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V. Rebuttal analysis — where the patentee's case is strongest

A careful analysis should not overstate the case. The following are genuine counterweights.

1. The single genuinely novel-seeming element is the ~1 µm lateral overlap of the pocket implant into the drift region, and the resulting graded drift region (claim 2). I found no cited reference that expressly discloses using the punchthrough/pocket implant's lateral diffusion to simultaneously (a) counterdope the LDD/drift and (b) form the punchthrough stopper. The '528 specification makes exactly this the inventive insight: "the pocket implant, owing to the extended lateral diffusion which takes place, can be used to counter dope the drift region, and this in turn, allows a graded drift region to be formed simultaneously with the punch through protection." A patentee will argue that the art taught separate implants/masks for these two functions and treated their merger as a manufacturing simplification that was not recognized as available. Assessment: claim 1 remains vulnerable because the overlap distance is recited as "about 1 µm" with no criticality showing, and because EP 0 717 448 A1's counterdoping teaching plus Wolf's drive-in teaching supply the mechanism; but claim 2 is the best candidate for survival, especially given the express claim-2 limitation on differentiated sheet resistances (first sheet resistance vs. higher second sheet resistance), which is a structural characterization of grading that the cited art does not expressly disclose.

2. Teaching away. Two doctrines are available to the patentee:

   • The '528 specification itself states: "The pocket implant does not extend to the drain of the device. If the pocket implant doping is extended to the drain, then the junction between the drain and the substrate would break down at a lower voltage." EP 0 717 448 A1's claim 11 ("said asymmetric halo region does not extend into or under said channel region") is likewise restrictive. A patentee will argue that the art's insistence on keeping the well-type pocket away from the drain/channel region would have deterred a PHOSITA from extending it toward the drift region.
   • Counter: claim 1 requires extension only into the drift region (the lightly doped n⁻ offset), not to the degenerately doped n⁺ drain contact, so the '528 specification's warning is consistent with, not contrary to, the claim. And EP 0 717 448 A1's asymmetric constraint is expressly tied to its own low-V_t logic objective ("a ratio of on current to off current that is at most about 10⁵," low threshold voltage), a context remote from a 40–60 V heater driver, which weakens the teaching-away inference.

3. Possible unexpected results. The '528 table is the patentee's best objective evidence: at G = 3 µm / LD = 3 µm the prior-art device shows V_BD = 22.4 V while the pocket-implant device shows 67.5 V — a roughly threefold improvement at that geometry, far more than the modest 2–17 V improvements seen at longer channel lengths. If the patentee can establish that this magnitude at the 3 µm/3 µm point reflects a different mechanism (punchthrough elimination rather than mere field shaping), that is a colorable In re Soni / unexpected-results argument directed especially at claims 4 and 9. Assessment: this is the strongest non-obviousness argument available, and any validity challenge should expect it. Note, however, that the specification never frames it as unexpected, which weakens it.

4. Secondary considerations. The record provided contains no evidence of commercial success, copying, licensing, industry praise, or long-felt-but-unmet need. The 1997-10-17 filing, follow-on filings (EP 0 909 649 A3; JP 11192704), and the maintenance-fee history (4th, 8th, and 12th year fees paid; patent expired 2017-10-17) are neutral on non-obviousness. Without Nexus evidence, the § 103 case rests on the art.

5. Reference-dating caveat. US 5,753,958 and US 5,790,154 were granted after the '528 filing date and are prior art only under pre-AIA § 102(e) as of their earlier effective filing dates (1995-10-16 and 1995-12-08 respectively). Any ground resting on them must establish the § 102(e) filing date and that the relied-upon disclosure was present in the originally filed application — otherwise that ground collapses.

6. Wolf page-range caveat. As noted in § III, pp. 232–245 of Wolf Vol. 3 are directed to the punchthrough mechanism and modeling (§ 5.3), with the express pocket-implant/LATIPS prescription in § 5.4. A ground that cites only pp. 232–245 for "the solution" overstates the citation. Correct the citation or supplement it with EP 0 717 448 A1.

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VI. Claim-by-claim conclusion

Overall. US 6,102,528 is, in my assessment, a probable-obvious patent with one credible island of non-obviousness: the recognition (claim 2's structural consequence) that the punchthrough pocket implant's lateral diffusion can be exploited to produce the graded drift region "simultaneously," eliminating the extra masks that the specification admits the art needed for graded doping. Claim 1 is vulnerable because the pocket implant itself, the high-voltage closed-geometry gate, the n⁻ drift region offset from the n⁺ contact, and the monolithically integrated printhead driver are each squarely in the cited art, and the ~1 µm overlap is recited without a showing of criticality. The strongest challenge brief would run US 5,517,224 + US 4,308,549 + EP 0 717 448 A1 + Wolf Vol. 3, with US 4,947,192 added against claims 5–7, and would pre-empt the unexpected-results argument by showing that the '528 specification's own data (the 64.5 V prior-art device at G = 4/LD = 3) already met claim 9's numeric threshold.

Where I am not confident: (a) I could not retrieve the full disclosure of US 4,947,192, US 5,010,355, US 5,159,353, US 5,790,154, or US 5,753,958 within this session, so my element mappings for those five rest on the '528 specification's own characterizations and the citation titles — verify against the full texts before relying on Ground 3 or Ground 4; (b) the exact page boundaries of the Wolf excerpt (whether pp. 232–245 include the pocket-implant prescription or only the punchthrough mechanism) should be confirmed against the physical volume, because that determines whether Wolf alone can supply the claim 1 pocket element or must be paired with EP 0 717 448 A1; and (c) I did not review the file wrapper, so I cannot say which of these grounds, if any, the examiner actually applied or why the claims issued.