Invalidity dossier
US 6006299
Apparatus and method for caching lock conditions in a multi-processor system
Current assignee: Intel Corp
Added 9/23/2026, 9:42:02 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 6006299 A
Title: Apparatus and method for caching lock conditions in a multi-processor system
Patent number / application: US 6006299 A; application US08/204,592
Assignee: Intel Corp (original assignee; a 1994-06-10 assignment to Intel Corporation from inventors Wang, Lai, Singh, Sarangdhar, Joshi, and Fisch is recorded)
Inventors: Wen-Hann Wang; Konrad K. Lai; Gurbir Singh; Mandar S. Joshi; Nitin V. Sarangdhar; Matthew A. Fisch
Dates: Priority/filing date 1994-03-01; granted and published 1999-12-21; anticipated expiration 2016-12-21. Status listed as "Expired - Lifetime" (a legal-status assumption, not a legal conclusion, per the source).
Purpose: To handle "lock conditions" in a multiprocessor system so that one processor's access to data shared with other processors is serialized. The abstract describes a "lock bit" set when a first processor begins an instruction operating on data common to a second processor, preventing the second processor from simultaneously executing an instruction on that same data; the second processor queues its request in a buffer; after completion the first processor clears the lock bit, checks the buffer, and signals the queued processor that the data is no longer locked. The description states the invention "allows external concurrent use of caches during an internal lock operation."
Plain-language scope: A described apparatus/method for caching lock conditions across processors, using a lock-in-progress bit plus a request buffer to defer competing requests until the lock is released. Illustrative architecture includes processors with L1/L2 caches, a processor-system bus, an I/O bridge, execution/retirement logic, and a M.E.S.I. cache-coherency scheme, with figures covering the computer system, an exemplary processor, a bus cluster, and a lock-handling flowchart.
What the excerpt does not establish: The provided text omits figures, the full description, and all claims, so claim scope, claim count, and specific claim limitations cannot be stated. It also does not establish prosecution history or any legal conclusions, and no prior-art references are identified or analyzed here.
Generated 10/1/2026, 9:34:05 PM
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Assignment history
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Prior art
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