US 5075250

I'll run searches to check for any litigation/docket activity and confirm the bibliographic data.

Let me do one more targeted check for any litigation or PTAB/Court of Appeals activity.

Search results: no litigation found

Before the summary, an important note on what the searches did and did not return:

• No CAFC 2026 docket activity was found for US 5,075,250. My queries for "5,075,250" / "5075250" against court/docket sources returned nothing involving this patent. For context, the record shows the patent expired 2011-01-02 (20 years from the 1991-01-02 filing), which makes 2026 appellate activity on this patent very unlikely.
• Caveat on my tooling: I do not have a direct connector to USPTO PatentCenter or to the CAFC docket system (PACER/CM-ECF). I ran general web searches instead. So my "no dockets" finding is a negative search result, not a verified query of the court's docket database. Treat it as such.
• Do not conflate identifiers. A search for "5075250" prominently returns JP 5075250 B2 — a different, unrelated Japanese patent (Panasonic, 記録再生装置及び記録再生システム / recording-and-reproduction apparatus, issued 2012-11-21, filed via PCT/JP2009/002779). It has no relationship to the US patent below. I have not auto-corrected or merged these; they are distinct documents that happen to share digits.

---

US 5,075,250 A — Bibliographic data

Abstract (as published): A thermal jet ink printing system is provided with an improved printhead. The printhead is formed by monolithic integration of MOS logic elements and drivers onto the same silicon substrate containing the resistive elements using a more efficient manufacturing process. In a preferred embodiment, the logic switches, logic drivers and resistive elements are formed from a single layer of polysilicon with the resistive element formed on a thermally grown field oxide layer. The integrated circuit chips are formed by a MOS fabrication technology which uses fewer processing steps than used in existing chips, and the resulting chips are thermally stable and can be operated at higher logic voltages.

---

Plain-language overview of the independent claims

The patent's core idea: replace the prior art's separate arsenic source-drain implant + phosphorous polysilicon implant (an eleven-mask flow, per Hawkins et al., US 4,947,192, incorporated by reference) with a single phosphorous masked implant, and additionally self-align the boron substrate contact to the etched vias — yielding a nine-mask process (~20% cost reduction claimed). Two mechanisms are offered for the lateral-diffusion problem that previously made the combined phosphorous implant unworkable: (1) an n⁻ drift implant, and (2) borophosphosilicate glass (BPSG) reflow at lower temperature/shorter time.

Claim 1 — the "combined n⁻ drift / n⁺ contact / resistor-end doping" method.
A method of making a thermal ink jet module where logic, drivers, and resistors sit monolithically on one silicon wafer surface. In plain terms:

1. Pattern polysilicon gate regions on gate oxide (these define the gate channels underneath).
2. At the same time, pattern polysilicon resistor regions on field oxide.
3. Form self-aligned n⁻ drift layers under all non-patterned gate-oxide areas — the drift layers are defined by the gates themselves — and simultaneously dope the polysilicon resistor regions.
4. Mask the areas you want to stay as n⁻ drift, because those n⁻ layers are what stop n-type dopant from laterally diffusing into the gate channels.
5. Form n⁺ contacts everywhere not masked; the n⁺ contact plus adjacent n⁻ drift together give a low-resistance path to the channel.
6. At the same time dope the ends of the polysilicon resistors, making those ends lower-resistance so they serve as the resistor's contact regions.
   The point of step 6 is stated in the spec: the "hot" central resistor region is where heat is efficiently transferred to ink, while the cooler ends prolong contact life.

Claim 10 — the BPSG variant.
A method of forming the n⁻ drift implants on a substrate that already has channel stops and field/gate oxides, in the same logic/driver/transducer module context. In plain terms: pattern gates on gate oxide (defining channels and adjacent source-drain contact regions) and, concurrently, pattern resistors on field oxide; simultaneously phosphorous-dope the resistor and gate polysilicon to a target resistivity; mask the polysilicon areas that should keep that resistivity; then phosphorous-dope the exposed polysilicon and silicon to create logic/driver source-drain contacts and lower-resistivity resistor contacts; then reflow BPSG over the substrate and etch vias down to the source-drain and resistor contact regions. The BPSG is the essential differentiator — its lower reflow temperature/time is what makes the single phosphorous implant tolerable in the logic.

Claim 12 — the full 44-step process claim.
A very detailed recitation of the entire fabrication sequence, numbered (1)–(44). Condensed flow:

1. Steps 1–8: thin oxide on wafer; mask 1 (photoresist) defines channel-stop areas; deposit insulating (nitride) layer; strip resist; ion-implant channel stops; etch thin oxide; grow field oxide (~≥1 µm, preferably 1.5 µm); strip nitride and underlying oxide.
2. Steps 9–14: grow sacrificial oxide; mask 2 defines depletion logic regions; arsenic (n-type) depletion-mode implant; strip resist and sacrificial oxide; grow gate oxide (~900 Å preferred); boron p-type enhancement implant.
3. Steps 15–18: deposit a single polysilicon layer (>4000 Å, ~4500 Å preferred); implant n-type (phosphorous) to set sheet resistance; mask 3 patterns polysilicon into gate and resistor regions (resistor sits on the field oxide); strip resist.
4. Steps 19–23: light n-type implant forming self-aligned drift layers; mask 4 masks parts of the gate/resistor polysilicon and parts of the drift layers (this "set-back" mask is the key to skipping the arsenic step); n-type implant creates n⁺ contacts and lower-resistivity polysilicon; strip resist; clean.
5. Steps 24–30: grow protective oxide; reflow glass (PSG ~1000 °C/90 min, or BPSG); mask 5 patterns the glass; etch vias through glass and oxide to the n-type contacts; self-aligned p-type (boron) implant through the vias to convert n-type contacts to source-drain contacts; clean; thermally activate (e.g., ~1000 °C/30 min).
6. Steps 31–40: apply contact metal; mask 6 patterns/etches interconnections; strip; deposit second insulating layer (Si₃N₄); deposit protective metal (Ta) over the resistor; mask 7 keeps Ta only over the central resistor portion; etch; strip; etch the nitride using the Ta as a mask.
7. Steps 41–44: deposit protective oxide; mask 8 exposes the resistor center; deposit polyimide; mask 9 exposes the resistor center.

Dependent claims (brief): Claims 2–9 add specifics such as ~4500 Å polysilicon and ~47 Ω/□ from phosphorous implant (cl. 2); phosphorous as the implant species (cl. 3); the glass reflow / via / boron implant / activation sequence (cl. 4); set-back distance being a function of reflow time and temperature (cl. 5); 7.5% PSG at ~1000 °C for ~90 min (cl. 6) with ~2.5 µm set-back (cl. 7); BPSG at ~950 °C for ~30 min (cl. 8); ~1000 °C/30 min boron activation (cl. 9). Claim 11 depends on claim 10 and specifies BPSG at ~950 °C for ~30 min.

---

Noteworthy technical points from the specification

• The set-back fourth mask (232/332) also masks roughly one in every six driver source contacts, reserving them for p⁺ substrate contacts so the substrate can be grounded from the top surface — eliminating the parasitic bipolar effect of back-side grounding.
• The self-aligned boron implant relies on boron diffusivity suppression in n⁺ silicon: in n⁻ regions boron diffuses deeply and converts to p⁺; in n⁺ regions boron is contained.
• Claimed benefits: higher breakdown voltage (80–90 V from self-aligning the n⁻ drift to the gate), ~20% cost saving from two eliminated masks, and reduced junction spiking at contacts because phosphorous suppresses aluminum–silicon reaction.

Explicit uncertainties

• Litigation/CAFC: I found nothing, but as noted I cannot directly query USPTO PatentCenter or the CAFC docket system. My conclusion of "no dockets" rests on negative general-web-search results, not an authoritative docket query.
• Assignee history: The record shows later security-interest assignments to Bank One (2002) and JPMorgan Chase (2003), and a 2022 release by JPMorgan as successor agent — these are financing/collateral records affecting Xerox, not transfers of this patent to a third party. Current assignee of record remains Xerox Corporation per the listing.
• Expiration: The record states "Expired – Lifetime" with anticipated expiration 2011-01-02. I have not independently verified whether any terminal disclaimer or adjustment altered that date; treat 2011-01-02 as the database's stated assumption, not a legal conclusion.
• All bibliographic details above are taken from the authoritative full text/Google Patents record supplied in the prompt, which in this instance is consistent with the independent search results (EP 0494076 A2 abstract and DOCDB family listing).

I'll search litigation databases for US patent 5075250.

Summary finding

No litigation specifically identifying U.S. Patent No. 5,075,250 was located. Across the sources searched (Google Patents litigation/legal-events data, the Unified Patents litigation caselist, PTAB/PTACTS filings, RPX Insight, Docket Alarm, CourtListener, and general press/CAFC reporting), I found no complaint, ITC investigation, or PTAB/IPR proceeding that names U.S. 5,075,250 as an asserted patent. I want to be explicit that this is a "not found," not a verified "none exists" — I could not run a docket-level numeric query against PACER or the Unified Patents caselist for the bare number, and Docket Alarm/CourtListener searches for the patent number returned no case hits.

Note also that US 5,075,250 (Method of fabricating a monolithic integrated circuit chip for a thermal ink jet printhead; Hawkins & Burke; Xerox Corp.; filed 1991-01-02; granted 1991-12-24) is recorded as "Expired – Lifetime" as of 2011-01-02 (anticipated expiration at the 20-year term). Any assertion would therefore have had to occur before early 2011, which narrows the plausible window and is consistent with finding nothing recent.

Related litigation — same technology, but a different patent number (do not conflate)

There is a well-documented family of Xerox v. Hewlett-Packard inkjet patent suits from the late 1990s that arose from the same thermal-inkjet printhead program that produced the '250 patent. Contemporaneous reporting, however, ties the inkjet printhead suit to U.S. Patent No. 5,030,971 — not 5,075,250 — and I found no source confirming that '250 was among the patents asserted. I flag this as a near-miss rather than a match:

• Xerox Corp. v. Hewlett-Packard Co. — U.S. District Court for the Western District of New York (Rochester, N.Y.), assigned to Judge Michael Telesca.
  • Filed: May 14, 1998 (some reports say May 13/14, 1998).
  • Subject: Xerox alleged HP's multicolor thermal inkjet printheads/cartridges (DeskJet, OfficeJet, PhotoSmart lines, Color Copier 110/120) infringed Xerox's 1991-filed printhead-cartridge patent — identified in reporting as U.S. 5,030,971 (not '250). Xerox sought a permanent injunction and unspecified (trebled) damages.
  • Outcome: On/about September 14–15, 1999, Judge Telesca granted HP summary judgment of no infringement and dismissed the case. Xerox stated it would appeal (I found no CAFC decision on the merits in the material reviewed).
  • Final disposition: The case was among six cross-suits between Xerox and HP filed between May 1998 and June 1999 that were settled and dismissed in a global settlement announced March 20, 2000.
  • Case number: Not confirmed from the sources retrieved — I will not supply a fabricated docket number.

Sources for the above: ZDNet, "Xerox files suit against HP" (identifying U.S. 5,030,971); CNET, "Xerox sues HP over ink jet printers" (May 14, 1998); NYT, "Metro Business; Xerox Sues Over Printers" (May 15, 1998); Tech Monitor, "Xerox Says It Will Appeal Against Inkjet Case Dismissal"; LA Times, "Judge Dismisses Xerox Patent Suit Against Hewlett-Packard" (Sept. 15, 1999); NYT/TheStreet.com, "Xerox and Hewlett-Packard Settle Litigation" (March 20, 2000).

Why the two patents are easy to confuse

• Both are Xerox thermal-inkjet printhead patents by the same inventors (William G. Hawkins and Cathie J. Burke) from the same 1991 timeframe.
• The '250 patent is the process counterpart to the structure disclosed in U.S. 4,947,192 (Hawkins et al.), which this patent expressly incorporates by reference as prior art.
• The '250 patent's own prosecution/family documents (e.g., the related EP 0 494 076 B1 / DE 69222192T2 / JP 3237881B2 family filings, and the later US 6,102,528 "Drive transistor for an ink jet printhead" by the same inventors) show continued Xerox activity in this area, but none of the citations or family data references litigation.

Bottom line

If you need a definitive negative, the checks to run directly are: (1) PACER docket search / CourtListener RECAP "patent number" field for 5075250, (2) the Unified Patents litigation caselist, and (3) RPX Insight's patent page for the '250. My open-web searches of those classes of sources did not surface a case, but I could not complete a direct docket-level query before running out of search steps.

I'll verify the structured "no PTAB proceedings" finding against public sources before writing the analysis.

Proceedings overview

There are zero AIA trial proceedings on U.S. Patent No. 5,075,250 — no IPR, no PGR, no CBM, and no PTAB proceeding of any kind is on file at the USPTO. The structured ODP-derived block states no AIA trials exist, and my independent web checks (Google Patents legal-events, PTAB/PTACTS document surface, Federal Circuit / CourtListener material, and general press coverage) surfaced nothing contradicting it. The defensive posture this gives a defendant is not "the patent is hardened" and not "the claims are canceled" — it is the rarer third posture: the patent is dead by expiry (2011-01-02) and was never challenged at the PTAB, so there is no PTAB record to rely on and none is needed. A demand letter citing the '250 as a live right is asserting an expired patent.

Because the proceedings list is empty, the per-proceeding template below is collapsed into a single "no proceedings" entry plus the negative-evidence workup a defendant actually needs.

---

No AIA trial proceedings on record

• Type: N/A — no IPR, PGR, or CBM petition was ever filed against US 5,075,250.
• Filed: N/A
• Status: Verbatim from the structured data: "The USPTO ODP API returns no AIA trial proceedings for this patent as of the most recent ingest." Plain-English gloss: the PTAB docket for this patent number is empty.
• Judge panel: None — no panel was ever assigned.
• Petition grounds: None. No petitioner ever advanced a § 102 / § 103 / § 112 challenge at the Board.
• Institution decision: None issued.
• Final Written Decision: None — no FWD exists, so no claim of this patent has ever been ruled unpatentable, and equally, no claim has ever been sustained by the Board. I will not invent claim-level outcomes.
• Settlement / termination: N/A.
• Appeal: None taken to the Federal Circuit, because there is no Board decision to appeal.

Why the emptiness is expected rather than anomalous. US 5,075,250 issued 1991-12-24, was filed 1991-01-02, and is recorded as "Expired – Lifetime" as of 2011-01-02 (the 20-year term from the earliest effective filing). The IPR regime only opened on 2012-09-16 (AIA § 6(c)), roughly twenty months after this patent lapsed. PGR was categorically unavailable (PGR reaches only first-inventor-to-file patents — the '250 is pre-AIA). CBM was legally available for pre-AIA patents but this is a semiconductor-fabrication process patent, not a "financial product or service" patent, so the CBM track never applied. An IPR against an already-expired patent is permitted in principle (the Board has entertained expired-patent IPRs), but nobody pays IPR fees to invalidate a lapsed right that no one is monetizing. The absence here is a timing fact, not a quality signal about the claims.

Two false positives I want to rule out explicitly, because they will burn you if you search the bare number:

1. JP 5075250 B2 (JP Patent No. 5075250, published 2012-11-21, Panasonic) is an unrelated Japanese recording/reproduction-device patent (AV copy-count management). It shares only the digits "5075250" and has no familial relationship to the '250.
2. The " '250 Patent" in Analog Devices v. Xilinx (D. Del., stay briefing re IPRs, institution decisions expected ~2021-01-27) is Analog Devices' U.S. Patent No. 8,xxx-series '250 — a different patent entirely. Note the coincidence that it did attract IPRs; the Xerox '250 attracted none. Do not import ADI's IPR record into a chart about this patent.

---

Strategic summary

Claim status: 12 claims, all UNTESTED, all EXPIRED. US 5,075,250 has claims 1–12, with independent claims 1, 10, and 12 (claim 10 is the n⁻-drift-implant sub-method; claim 12 is the 44-step full-process claim). Not one of them has been canceled, confirmed, or construed by the Board, because no petition was ever filed. Any statement that "claims X–Y were canceled in IPR" for this patent is false. The correct framing is that the entire claim set lapsed for failure to reach the end of the statutory term, not for invalidity.

Estoppel landscape: there is no IPR estoppel, because there is no IPR. § 315(e)(2) estoppel attaches only to a petitioner that obtained a final written decision under § 318(a). With no petition, no institution, and no FWD, no party anywhere is estopped as to this patent's claims, and no prior-art ground has been "used up." That said, the practical question is moot: you cannot infringe an expired patent. For any real-world dispute, the operative defenses are (i) expiry — the right to exclude ended 2011-01-02; (ii) § 286's six-year damages lookback, which means acts of infringement falling within a suit filed today could only reach back to roughly 2020, long after expiry, leaving no compensable pre-expiry window; and (iii) if a letter affirmatively threatens suit on an expired patent for post-expiry conduct, consider whether the assertion itself is actionable (e.g., inequitable conduct is unavailable against an expired patent, but state-law / Lanham Act theories sometimes are, depending on the facts). Antedating and invalidity workups would be a waste of budget.

Pattern signals: none exist, and the surrounding family does not change that. No serial petitioner, no defensive aggregator (Unified Patents is not in the chain), and no PTAB appeal activity by Xerox on this patent. The broader Xerox thermal-inkjet enforcement activity in the record is a different matter: the late-1990s Xerox v. Hewlett-Packard W.D.N.Y. (Rochester) printhead-cartridge suit, which contemporaneous reporting ties to U.S. 5,030,971 — not the '250 — was resolved by summary judgment of non-infringement for HP in September 1999 and a global settlement in March 2000. Xerox's later, much-larger PTAB footprint in this space is an artifact of a different workstream (the Xerox/MPHJ "Virtual Copier" campaign, e.g., IPR2014-00538 / -00539 and IPR2015-01178, where Xerox, Ricoh, and Lexmark were the petitioners), and the 2020s Xerox v. Meta/X campaign over U.S. 7,043,475 and 8,489,599 (IPR2021-01264, -01294; Fed. Cir. Nos. 2023-1714, -1985, affirmed 2025-06-17). None of those proceedings name this patent. So the honest pattern read is: Xerox litigates and gets IPR'd on other patents; this one was left alone and simply ran out.

One caution on the earlier litigation section supplied to me: it identifies Xerox's late-1990s inkjet suit as tied to U.S. 5,030,971. I did not independently verify the '971 attribution in this pass, and I did not locate a docket number. I flag it as unverified rather than endorsing it, and I note it is irrelevant to PTAB exposure for the '250 either way.

---

Recommended next steps

• If you are a defendant and a demand letter or complaint cites US 5,075,250: the defensive work is a one-page expiry argument, not an IPR. Point to the Google Patents legal-events entry recording "Anticipated expiration" on 2011-01-02 and the status "Expired – Lifetime" (https://patents.google.com/patent/US5075250/en). There is no FWD to link, because there is no FWD — and you should say exactly that rather than implying one exists.
• Do not budget for an IPR. A petition against an expired, unasserted method patent buys you nothing: the target claims are already unenforceable for lack of term, and the cost of an IPR vastly exceeds any exposure. If a plaintiff nevertheless presses a claim chart, the answer is § 286 (six-year pre-suit lookback against a 2011 expiry date) plus the expiry date itself.
• If a live proceeding is nonetheless reported to you: verify it before acting. Search PTAB E2E by patent number at https://ptacts.uspto.gov/ptacts/ and the Board's decisions page at https://www.uspto.gov/patents/ptab/decisions, and check CourtListener at https://www.courtlistener.com for any CAFC docket. I found nothing in those classes of sources; if a proceeding surfaces in a later ingest, the trial-stage milestones I would then track are the institution-decision deadline (≈6 months from the notice of filing date), the oral hearing, and the one-year statutory FWD deadline from institution under § 316(a)(11). Today that branch is hypothetical for this patent.
• Plainly stated: there is no PTAB activity on US 5,075,250. That absence is not evidence that the patent is clean or that prior art is weak — it is evidence that the right expired before the IPR window opened and was never worth attacking. Treat the patent as expired, not as adjudicated.

I'll research the assignment record and related ownership context for US 5,075,250.

Let me try to pin down the correspondent of record for the recordings on this patent.

Assignment & Ownership Analysis — US 5,075,250

Patent: Method of fabricating a monolithic integrated circuit chip for a thermal ink jet printhead
App. No. 07/636,826 · Filed 1991-01-02 · Granted 1991-12-24 · Status Expired – Lifetime (anticipated expiration 2011-01-02)

Methodological note up front: the four recorded entries below are taken from the Google Patents legal-events mirror of the USPTO assignment record, which reproduces the reel/frame, conveyance type, execution date, recording date, assignor and assignee for this patent. It does not expose the correspondent of record, and I was unable to retrieve the correspondent fields from the Assignment Center/PEDS record for this patent before exhausting my search budget. Where I do not have a correspondent, I say so rather than infer one. I also did not find any Assignment Center record that is absent from the Google Patents mirror — but I could not run a direct reel/frame-level query, so treat this as a high- but not perfect-confidence reconstruction.

---

Inventors

Unusual-pattern check — departure within 12 months: not present. Hawkins remained a named Xerox thermal-ink-jet inventor well past 1991 — Xerox's US 6,102,528 (Drive transistor for an ink jet printhead, priority 1997-10-17) is in the same citation family as the '250, and Hawkins appears across the Xerox inkjet portfolio through at least the late 1990s. That is inconsistent with the "all inventors out the door within a year" fire-sale precursor. I did not verify Burke's later filing record, so I flag that as unconfirmed rather than clean.

---

Original assignee

Xerox Corporation, Stamford, CT (as recited on the face of the assignment instrument: "XEROX CORPORATION, STAMFORD, CT A CORP. OF NY").

• Primary line of business: document management — copiers, printers, digital imaging systems and supplies. Not a licensing entity.
• Did they ship a product embodying the claims? The '250 claims a fabrication process for a monolithic thermal-ink-jet printhead chip (logic + drivers + polysilicon resistors on one wafer; see claims 1 and 12, esp. the 44-step sequence in claim 12). Xerox built thermal ink jet print elements and cartridges at Webster, NY in this period — corroborated by the SPIE 1994 paper "Print Element for Xerox Thermal Ink Jet Print Cartridge" (Courtney et al., Color Hard Copy and Graphic Arts III, Vol. 2171) and by Xerox's own May 1998 statement that it could not "allow [HP] to infringe the technology we developed and marketed." This is good evidence the assignee was practicing in the same technology, though I cannot tie a specific shipping SKU to these exact process claims.
• Current status: Operating. Xerox has never filed Chapter 7 or Chapter 11. The document-technology business continues under Xerox Holdings Corporation (Norwalk, CT), with Xerox Corporation as the operating/asset-holding entity; the business-services arm was spun off as Conduent in 2017. Xerox remains listed by Unified Patents as the parent company of this portfolio (cf. Unified's page for the sibling JP-H022009-A, "Parent Company: Xerox Holdings Corp").

---

Assignment timeline

Four records. Only one of them conveys title — the other three are a security interest, a security agreement, and a release of that security. This is the single most important structural fact about this patent's chain.

1. 1991-02-18 (executed) / recorded 1991-03-04 — Reel 005620/0323

• Conveyance: Assignment
• Assignor: William G. Hawkins and Cathie J. Burke (jointly, "ASSIGNMENT OF ASSIGNORS INTEREST")
• Assignee: Xerox Corporation, Stamford, CT (a New York corporation)
• Correspondent: Not exposed in the retrieved record. I could not retrieve the correspondent field for reel 005620/0323 and did not find it indexed anywhere else; I will not guess a name here.
• Context: Standard employment/obligation-to-assign assignment of the application filed 1991-01-02 — the origin of title, executed pre-grant.

2. 2002-06-21 (executed) / recorded 2002-06-28 — Reel 013153/0001

• Conveyance: Security Interest ("SECURITY INTEREST; ASSIGNOR: XEROX CORPORATION")
• Assignor: Xerox Corporation
• Assignee (secured party): Bank One, NA, as Administrative Agent, Illinois (One Bank One Plaza, IL1-0631, Chicago, IL 60670)
• Correspondent: Not exposed in the retrieved record for this patent. A closely analogous record exists on Xerox's trademark side for the same transaction (execution date Jun. 21, 2002, same Bank One address), reproduced in TTAB Opposition No. 91285890, which shows correspondent "ACCESS INFORMATION SERVICES, INC. / Jackie Lee, 1773 Western Avenue, Albany, NY 12203." I flag this as indicative only — trademark reels and patent reels are separate recordings and I have not confirmed the same agent on patent reel 013153/0001.
• Context: Securitization / collateral — the patent was pledged (along with other Xerox IP) under the 2002 Xerox credit facility. Does not transfer ownership.

3. 2003-06-25 (executed) / recorded 2003-10-31 — Reel 015134/0476

• Conveyance: Security Agreement ("SECURITY AGREEMENT; ASSIGNOR: XEROX CORPORATION")
• Assignor: Xerox Corporation
• Assignee (collateral agent): JPMorgan Chase Bank, as Collateral Agent, Texas (P.O. Box 2558, Lien Perfection Unit, Houston, TX 77252)
• Correspondent: Not exposed in the retrieved record for this patent. The parallel trademark record for this transaction likewise lists correspondent Jackie Lee, 1773 Western Avenue, Albany, NY 12203. ⚠️ Note for the "repeat correspondent" signal: this is the same recording agent appearing on the assignor's side across successive Xerox collateral filings — and, per the TTAB record, on behalf of both Xerox and the secured party. That is a Xerox-side collateral-recording function, not an NPE filer.
• Context: Securitization / collateral — refinancing/successor collateral package covering Xerox IP. Does not transfer ownership.

4. 2022-08-22 (executed) / recorded 2022-09-07 — Reel 066728/0193

• Conveyance: Release by Secured Party
• Assignor: JPMorgan Chase Bank, N.A., as successor-in-interest to JPMorgan Chase Bank as Collateral Agent (and successor to the Bank One administrative agency)
• Assignee: Xerox Corporation, Connecticut
• Correspondent: Not exposed in the retrieved record.
• Context: Termination of the 2002/2003 security interests after the underlying debt was satisfied — a cleanup/release, not a transfer. It confirms the collateral encumbrance is gone and that Xerox still held the asset at that date.

Ownership bottom line: title has moved exactly once — inventors → Xerox on 1991-03-04 — and has never left Xerox. The US family members EP 0 494 076 B1, JP 3237881 B2 and DE 69222192 T2 show no separate chain-of-title events of their own.

---

Timeline diagram

timeline
    title Ownership of US 5075250
    1991 : Filed by Hawkins and Burke
         : Assigned to Xerox Corporation
         : Patent issued
    2002 : Bank One security interest recorded
    2003 : JPMorgan Chase security agreement recorded
    2011 : Patent term expired
    2022 : Chase security interest released

---

NPE / troll-pattern signals

---

Verdict

Insufficient data — in the narrow, literal sense used in the rubric: only the original assignment transfers ownership, and there is no post-issuance ownership record to analyse.

Justification: the complete recorded chain is (i) inventors → Xerox Corporation, executed 1991-02-18, recorded 1991-03-04 at reel 005620/0323; (ii) Bank One, NA security interest, executed 2002-06-21, reel 013153/0001; (iii) JPMorgan Chase Bank security agreement, executed 2003-06-25, reel 015134/0476; and (iv) JPMorgan's release, effective 2022-08-22, reel 066728/0193. None of (ii)–(iv) conveys title, so no NPE-definitional element is satisfied: there is no shell-entity transfer, no known asserter, no cascade, and no pre-suit transfer. "Operating-company assertion" is also not the right box, because no infringement action naming US 5,075,250 was located and the one same-technology suit (Xerox v. HP, W.D.N.Y., filed 1998-05-14) is reported against US 5,030,971. The affirmative conclusion, stated plainly: this patent stayed with its original operating-company assignee for its entire life and was never asserted.

Verify at:

• USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (search patent number 5075250; also https://assignment.uspto.gov/patent/index.html)
• Google Patents legal events — https://patents.google.com/patent/US5075250/en

What I could not verify, and would run next: (1) the correspondent of record on each of the four reel/frame entries — the single highest-value field for this task and the one missing from the mirrored data; (2) whether the 2002/2003 patent-side recordings used the same agent as the trademark-side recordings (Access Information Services / Jackie Lee, Albany NY); and (3) a direct PACER/RECAP patent-number query to convert the "no litigation found" for the '250 from a not-found into a verified negative.

I'll verify the USPTO record and each cited reference. Running searches in parallel.

Now let me verify the remaining references.

Scope and method note

I queried the patent-number-specific record for US 5,075,250 and confirmed it resolves to Method of fabricating a monolithic integrated circuit chip for a thermal ink jet printhead (Hawkins & Burke; Xerox). Sources retrieved: the Google Patents full-text record, uspto.report/patent/grant/5,075,250, EveryPatent, and Justia. I do not have a direct connector to USPTO PatentCenter, so the record I used is the published USPTO-derived text — same caveat as the earlier sections. I did not auto-correct any identifier, and I did not fold in similarly numbered documents.

⚠️ Number-confusion flags (kept distinct, not merged):

• JP 5075250 B2 (Panasonic, 2012) is unrelated, as noted previously.
• US4429321A = U.S. Pat. No. 4,429,321 — these are the same document (the digits 4429321 match). The '250 specification's background section calls it "U.S. Pat. No. 4,429,321 to Matsumoto," while the citation table lists it as US4429321A. Same patent, two notation styles. I flag it so it isn't treated as two references.

---

The examiner-cited prior art ("Citations (9)")

These are the nine references of record against US 5,075,250, in the order they appear in the patent's citation table. Note up front: Applicable law is pre-AIA 35 U.S.C. § 102, because the application was filed 1991-01-02. The § 102(b) critical date is therefore 1990-01-02.

Note on reference 9: it published after the '250 filing date (1991-01-02), so it is not §102(a)/(b) art; it can only be relied on under §102(e) by virtue of its 1989-06-19 U.S. filing date.

Also a family-level item (not a §102 reference against '250 itself): DE 69109884 T2 — Canon K.K., "Inkjet recording system," priority 1990-02-09 — listed under "Family Cites Families."

---

Reference-by-reference analysis

1. US 4,080,618 A — Tokyo Shibaura Electric Co., Ltd. (1975-09-05 / 1978-03-21)

Subject: Insulated-gate field-effect transistor in which the source and drain are each formed by diffusion of two impurities of different diffusion depths — a shallow, low-diffusion-coefficient impurity (arsenic) adjacent the channel, and a deeper, higher-diffusion impurity (phosphorus) in the outer parts. The stated purpose is to control short-channel horizontal phosphorus diffusion / punch-through and improve reproducibility at ~5 µm channel lengths.

§102 potential: None. Not an ink-jet printhead and discloses no resistor-on-field-oxide, no single-polysilicon-layer integration, and no single phosphorous masked implant. It cannot anticipate independent claims 1, 10, or 12 (all of which require a thermal ink jet printing module), nor any dependent claim, since every dependent claim carries all independent-claim limitations.

§103 relevance: Its teaching of dual shallow/deep source-drain doping (arsenic-adjacent-channel + phosphorus) is squarely on point for claim 1 step (e) (n⁺ contact regions adjacent an n⁻ drift/low-resistivity path) and claim 3 (phosphorous as the n-type implant species). It is a natural obviousness reference against claims 1, 3, and 12.

2. JP S54-140488 A — Hitachi Ltd. (1978-04-24 / 1979-10-31)

Subject: Titled "Semiconductor device." Content not retrieved in my searches — I will not characterize its disclosure from the title alone. Japanese Kokai published 1979-10-31, so it is §102(b) printed-publication art by date.

§102 potential: Cannot be assessed without the text; on its face it is titled generically and is not an ink-jet printhead, so anticipation of claims 1/10/12 is improbable. Flagged as unverified.

3. US 4,265,685 A — Hitachi, Ltd. (1979-01-26 / 1981-05-05)

Subject: "Utilizing simultaneous masking and diffusion of peripheral substrate areas." A LOCOS silicon-gate MOSIC method in which an insulating film formed during formation of the polycrystalline-silicon resistor is used as the mask for forming a substrate electrode, thereby reducing the number of mask steps. The poly-silicon resistor, gate poly, and an interconnect are patterned from one poly deposition; a masking oxide is deposited on the drain-wiring poly region to block impurity introduction.

§102 potential: None. It is a DRAM/LOCOS MOSIC process, not a thermal ink jet printhead, and it does not disclose the claimed single-phosphorous masked implant or the self-aligned boron via implant. No independent claim is anticipated.

§103 relevance: Directly relevant to the mask-count-reduction rationale of claims 1, 4, and 12 (using a deposited insulating/masking layer over a poly resistor as a self-masking/implant-blocking element, so that contact/electrode formation and implantation proceed without an extra mask). Useful §103 art particularly against claims 4, 5, and 12.

4. US 4,290,185 A — Mostek Corporation (1978-11-03 / 1981-09-22)

Subject: "Method of making an extremely low current load device for integrated circuit." An isoplanar silicon-gate process producing an intrinsic–extrinsic junction load device formed as an integral part of a polycrystalline-silicon strip. An undoped poly layer (~3,000–6,000 Å) is masked with a nitride/oxide so that, when the source/drain/gate impurities are diffused or implanted, one portion of the poly is doped ("extrinsic") while the masked portion stays lightly/intrinsic — creating the load resistor. Gate oxide ~900 Å; field oxide ~8,000 Å.

§102 potential: None. Not an ink-jet device; no thermal transducer; no borophosphosilicate/phosphosilicate reflow; no self-aligned via implant.

§103 relevance: Strong on the "dope one portion of a poly layer while masking another portion that is to remain higher-resistivity" concept — i.e., the resistor-end doping of claim 1(f) and claim 2 (sheet resistance by phosphorous implant), and the single-poly-layer, mask-then-implant steps 15–18/20–21 of claim 12. Also relevant to the ~900 Å gate oxide and single-poly-deposition parameters recited in the dependent claims.

5. US 4,429,321 A (= US4429321A) — Canon K.K., Matsumoto (1980-10-23 / 1984-01-31)

Subject: "Liquid jet recording device." A liquid jet (thermal) recording device in which the electrothermal transducers and the driving-circuit "function elements" (signal-separating/ driving elements) are structurally formed in the surface of a common substrate, or the transducers are laminated onto a substrate having the function elements; multiple heat-actuating chambers communicate with ejecting orifices. The control unit is a bipolar-type transistor, and the resistor is formed by various implants.

§102 potential: None. This is the closest ink-jet-field reference, but it discloses bipolar drivers, not the MOS logic + driver + resistor-on-field-oxide single-polysilicon-layer structure, and it discloses none of the distinguishing process aspects of claims 1–12: no single phosphorous masked source-drain/poly implant, no n⁻ drift implant, no self-aligned boron via implant, no BPSG reflow. Notably, the '250 specification expressly criticizes this reference (bipolar "destructive thermal run away"), so it is positioned as background art, not as anticipating art.

§103 relevance: Background/general-art relevance for the motivation to monolithically integrate driver circuitry with the heat-generating transducers on a common substrate — a preamble-type element of claims 1, 10, and 12.

6. JP S59-25244 A — Hitachi Ltd. (1982-08-02 / 1984-02-09)

Subject: Titled "Semiconductor device." Content not retrieved. §102(b) printed-publication art by date (published 1984-02-09).

§102 potential: Unverifiable / improbable for the same reason as reference 2. Flagged as unverified.

7. US 4,602,421 A — U.S. Air Force (1985-04-24 / 1986-07-29)

Subject: "Low noise polycrystalline semiconductor resistors by hydrogen passivation." A method of hydrogen-passivating polycrystalline semiconductor (polysilicon) resistors to reduce their noise (e.g., 1/f) — a materials/processing treatment of the resistor body rather than device integration.

§102 potential: None. No ink-jet context; addresses resistor noise, not the integration, doping, or masking scheme claimed.

§103 relevance: Peripheral. It confirms that doped polysilicon resistors were a well-known integrated element (useful context for claim 1(b)/claim 2), but it does not help reach the claimed combination.

8. US 4,947,192 A — Xerox Corporation (Hawkins et al.) (1988-03-07 / 1990-08-07) — the closest reference

Subject: "Monolithic silicon integrated circuit chip for a thermal ink jet printer." A MOS transistor and a resistor formed monolithically on the same silicon substrate for a thermal ink jet printer, including a lightly doped source/drain layer, and contemplating added logic. This is the structure depicted in FIG. 3 of the '250 patent and the reference the '250 specification expressly incorporates by reference. Critically, the '250 background states that this Hawkins structure used a separate arsenic source-drain implant plus a phosphorous polysilicon implant and required an eleven-mask process.

§102 potential: No anticipation of any claim. Although it is §102(a)/(b) art (and §102(e) art) and is in the identical field, it teaches away from the invention's core: it does not disclose the single phosphorous masked implant replacing the arsenic step, the n⁻ drift compensation implant, the self-aligned boron via implant, or the BPSG reflow limitation. Because the '250 claims essentially recite the differences over this reference, it cannot anticipate claims 1, 10, or 12, nor any dependent claim.

§103 relevance: It is the primary §103 reference — the base structure over which the '250 invention is an improvement. Every independent claim is expressed as a modification of it.

9. US 5,013,677 A — Sony Corporation (1989-06-19 / 1991-05-07)

Subject: Titled "Method for manufacture of semiconductor device." Content not retrieved in my searches. Because it published 1991-05-07 (after the '250 filing date of 1991-01-02), it can only be relied on as §102(e) art by virtue of its earlier U.S. filing date of 1989-06-19.

§102 potential: Unverified — I could not obtain its disclosure, and I will not infer it. Given the generic title and non-ink-jet field, anticipation of claims 1/10/12 is improbable; likely a §103 process-art reference.

---

Most relevant prior art — ranked

1. US 4,947,192 (Xerox/Hawkins et al.) — the single most relevant reference. Same inventors' line, same field, expressly incorporated by reference, and the base structure the '250 claims improve upon. §103 anchor, not §102 art.
2. US 4,429,321 (=US4429321A) (Canon/Matsumoto) — closest ink-jet art (monolithic transducer + drive circuit); background only.
3. US 4,080,618 (Tokyo Shibaura) — closest on the dual shallow/deep source-drain doping chemistry (arsenic-adjacent-channel + phosphorus), directly bearing on claim 1(e)/claim 3.
4. US 4,265,685 (Hitachi) — closest on mask-step reduction via a masking film over a poly resistor (claims 4, 5, 12).
5. US 4,290,185 (Mostek) — closest on selectively doping one portion of a single poly layer while masking another (claims 1(f), 2, 12).
6. US 4,602,421 (USAF) — peripheral (poly resistor process).
7. JP S54-140488 (Hitachi), JP S59-25244 (Hitachi), US 5,013,677 (Sony) — cited but content not retrieved; cannot be characterized from the titles alone.

---

Bottom line on § 102

• No single reference of record anticipates any of claims 1–12. Claims 1, 10, and 12 are each drawn to a thermal ink jet printing module fabrication method, and the only cited references in that field (US 4,947,192 and US 4,429,321) do not disclose the claimed single-phosphorous masked implant, n⁻ drift compensation, self-aligned boron via implant, or BPSG reflow. The remaining references (DRAM/MOSIC/FET/poly-resistor process art) are outside the field and disclose at most isolated elements, so they cannot anticipate.
• The nine references function as §103 obviousness art, supplying individual claim elements (dual source-drain doping, masking-film-over-poly-resistor for mask reduction, selective poly doping, monolithic ink-jet integration), which is consistent with the '250 prosecution positioning its claims as an improvement over US 4,947,192.
• Caveats / explicit uncertainties: The disclosures of JP S54-140488 A, JP S59-25244 A, and US 5,013,677 A could not be retrieved, so my "no anticipation" conclusion is firm for six references and unverified for those three. US 5,013,677 A is §102(e)-only art given its post-filing publication date. I could not run a docket/PatentCenter-level query, so the citation list is taken from the authoritative published record supplied. If you need a definitive per-reference §102 check on the three unretrieved documents, the sources to pull directly are the JPO (J-PlatPat) English abstracts for JP S54-140488 and JP S59-25244, and the full text of US 5,013,677.

I'll ground this obviousness analysis by pulling details on the key prior-art references listed in the patent's Prior Art section.

Let me pull details on the remaining key references.

Let me check the two Japanese references and the Sony reference.

Obviousness Analysis — U.S. 5,075,250 under 35 U.S.C. § 103

Building on the prior summary/claim-mapping and litigation sections; not repeating them. One cross-reference flag appears in §7 below.

---

1. Framework and level of ordinary skill

Legal standard. Pre-AIA § 103(a) with Graham v. John Deere factors and KSR Int'l v. Teleflex (550 U.S. 398 (2007)): (i) scope/content of the prior art; (ii) differences between the art and the claims; (iii) PHOSITA level; (iv) secondary considerations. Under KSR, a combination is obvious where prior-art elements are used "according to their established functions" with a "reasonable expectation of success," where there is a "design incentive" or "market pressure," where the patentee's own framing presents "a finite number of identified, predictable solutions," or where the variation is a "predictable use" of a known technique to improve a similar device in the same way.

POSITA (as of the 1991-01-02 filing date). A B.S. in electrical engineering, materials science, or physics plus ~2–4 years of NMOS/CMOS process-integration experience, or an M.S. plus ~1–2 years — including familiarity with LOCOS field isolation, self-aligned polysilicon-gate processing, ion-implantation masking practice, PSG/BPSG glass reflow, lightly doped drain (LDD) engineering, and polysilicon resistor fabrication. This is a mature, well-documented field; the references relied on are all analogous art (semiconductor processing, and inkjet printhead fabrication, which the patent itself treats as a routine application of NMOS processing).

---

2. The prior art of record (the "Prior Art" section)

Nine references are cited on the face of the patent, plus one family document:

Supplementary art located during this analysis (NOT in the '250 record — flagged as such): the EP 0187016 A3 search report also cites Takeda et al., "An As–P (n⁺–n⁻) double diffused drain MOSFET for VLSI's," IEEE Trans. Electron Devices, ED-30(6), June 1983 — direct evidence that substituting phosphorous for arsenic to form the n⁺ contact with an adjacent n⁻ region was known; and EP 0 164 449 A3 (Hitachi), expressly reciting that "boron having a high diffusion velocity is suppressed from diffusing below the gate electrode" — the same diffusivity-suppression physics the '250 spec relies on for its self-aligned boron contact.

---

3. What Hawkins '192 already discloses

Verified against the '192 specification:

• Field oxide ≥ 1 µm on a P-type wafer, channel-stop boron implant, gate oxide — i.e., the starting structure of '250 claims 1 and 12.
• A single polysilicon layer forming both the transistor gates 78 and the resistors 79, with a poly sheet resistance of 5 Ω/□–5 kΩ/□ — the poly layer of '250 claims 2 and 12(15)–(17).
• Polysilicon resistors sitting on the thermally grown field oxide — claim 1(b), claim 12(17).
• Use of the polysilicon gate as a self-aligned implant mask while a lightly doped source 80 / drain 82 implant is performed, giving 500 Ω/□–20 kΩ/□ ("~4 kΩ/□") — the self-aligned n⁻ drift layer of claim 1(c) and claim 12(19).
• Self-alignment of that drift layer to the gate to raise breakdown voltage above 75 V — '250 claims the same benefit at 80–90 V.
• Phosphorous-doped (PSG) glass reflow, via etch, and a further n⁺ implant (90, 92) through the vias to allow ohmic contact to the lightly doped source/drain, followed by a thermal activation cycle and Al metallization — the reflow/via/activation sequence of claims 4 and 12(24)–(33).
• Express motivation: "it is, of course, desirable and cost effective to have a resistor structure which is immediately and simply integrated on the same wafer with MOS drive electronics, preferably without additional process steps."

The '192 European counterpart is EP 0 401 440 B1, same inventors (Hawkins/Burke), same abstract ("single layer of polysilicon… resistive element formed on a thermally grown field oxide layer").

Net difference over '192. Claim 1 differs principally in (i) forming the n⁻ drift layers while simultaneously doping the polysilicon resistor regions and masking selected drift regions so they remain n⁻ specifically to block lateral n-type diffusion; (ii) using a single n-type (phosphorous) implant that produces both the n⁺ source/drain contacts and the lower-resistivity resistor ends; and (iii) the express masking of poly regions that are to retain higher resistivity. Claims 10/11 add BPSG; claims 4–9 add the glass-reflow/via/self-aligned boron sequence and its process parameters.

---

4. Grounds of rejection (combinations and the motivation to combine)

Ground 1 — Claim 1 (and claims 2, 3) over '192 in view of '421 and '618/JP S59-25244

• '192 supplies every structural and most process elements (above).
• '421 supplies the missing resistor-specific steps with unusual directness: it teaches (a) a polysilicon resistor on an oxidized layer, (b) doping the poly resistor by ion implantation naming phosphorous, and (c) "heavy doping of the end-contact regions of the polysilicon film by high-dose ion implantation" — i.e., precisely claim 1(f) ("simultaneously doping the ends of the polysilicon resistor regions to produce localized areas of lower resistivity") and its stated rationale (a high-resistance "hot" body with low-resistance cooler ends).
• '618 (and/or JP S59-25244) supplies the n⁻ drift/LDD concept — a lightly doped region between the channel and the n⁺ contact, formed self-aligned to the gate — which is the very structure '192 already used and which claim 1(c)–(d) recites.
• Motivation: '192's own text demands integration "without additional process steps"; the '250 Background concedes the sole obstacle to merging the arsenic and phosphorous implants is the known problem of phosphorous lateral diffusion under 5 µm gates during reflow. Consolidating two same-conductivity-type n⁺ implants into one is the archetypal "predictable use of a prior-art element according to its established function," and LDD/drift layers were the standard 1980s remedy for precisely this class of short-channel/diffusion problem.
• Reasonable expectation of success: '192 already demonstrated the drift layer raising breakdown to >75 V in this exact device; '421 already demonstrated implanted, end-doped polysilicon resistors.

Ground 2 — Claim 1 over '192 in view of '185 (Mostek)

'185 is arguably the single most on-point secondary reference for the masking-plus-simultaneous-doping concept. Verified: in its isoplanar silicon-gate flow, a diffusion-impervious mask is placed over part of an undoped polysilicon strip, and a single diffusion step then simultaneously dopes the gate strip, the strip's unmasked portions, and the substrate source/drain regions — creating a low-resistivity region adjacent a masked, higher-resistivity region in the same poly layer. That is the operative logic of claim 1(c)–(f): one implant, a mask that sets back selected regions, and simultaneous doping of poly and substrate. The motivation is express and structural (reduce area/steps; a single poly layer serving multiple functions).

Ground 3 — Claim 1 over '192 in view of '265,685 (Hitachi)

The Hitachi reference's very title — "Utilizing simultaneous masking and diffusion of peripheral substrate areas" — teaches the general technique of combining masking and diffusion operations for peripheral regions, providing the design incentive to consolidate mask/implant levels (the "set-back" masking strategy of the '250 mask 232/332). Even at title level this supports the motivation leg of Ground 1.

Ground 4 — Claim 12 (the 44-step process claim)

Claim 12 is a compilation of (a) '192's flow (field oxide, single-poly gates-and-resistors, self-aligned lightly doped source/drain, PSG reflow at high temperature, vias, n⁺ ohmic implant, activation, Al, Si₃N₄/Ta transducer stack, protective oxide/nitride/polyimide), plus (b) the consolidated phosphorous implant and set-back masking (Grounds 1–3), plus (c) the self-aligned p-type implant through the vias (step 28). Each numbered step is a conventional NMOS step. Note that claim 12 recites "reflowing glass" generically (step 25) — so the BPSG gap discussed below does not rescue claim 12; '192's PSG reflow literally covers it. Claim 12 is therefore obvious over '192 + '421 + '185/'618.

Ground 5 — Claims 4–7 and 9 (glass reflow, vias, self-aligned boron, activation, parameters)

'192 discloses PSG reflow, via formation, a contact implant through the vias, thermal activation, and Al metallization. The delta is that the via-region implant is boron and self-aligned to the etched vias. Two lines of reasoning make this obvious:

1. Self-alignment to existing features to eliminate a mask level is a routine, recognized technique; the vias are themselves a mask ("the BPSG acts as the patterning mechanism" in the '250 spec is presented as an economy, not a discovery).
2. The mechanism relied on (boron diffuses deeply in n⁻ regions but is suppressed in n⁺ regions) was known — see EP 0 164 449 A3 (Hitachi), which states the same diffusivity-suppression proposition for boron (supplementary art; a POSITA in 1991 would also have known preferential boron diffusion through PSG/BPSG from the glass).

• Claim 5 ("set-back distance is a function of the time and temperature of subsequent glass reflow") is the definition of a result-effective variable — In re Aller / In re Boesch optimization, obvious as a matter of routine process-window engineering.
• Claim 6 (7.5% PSG, ~1000 °C, 90 min) tracks '192's high-temperature PSG flow directly.
• Claim 7 (2.5 µm set-back) is a working example of the optimization in claim 5; obvious absent evidence the specific value is critical and unexpected.
• Claim 9 (~1000 °C, 30 min activation) is a routine activation anneal, disclosed in substance by '192.

Ground 6 — Claims 8, 10, 11 (BPSG) — the weak ground

None of the nine cited references discloses borophosphosilicate glass, let alone BPSG reflow at "~950 °C for ~30 minutes." '192 discloses only "phosphorus doped glass." Rescuing these claims would require art outside the '250 record teaching (a) BPSG as a reflow/planarization glass with a lower flow temperature and shorter flow time than PSG, and (b) that PSG reflow drives phosphorous into underlying silicon (dopant out-diffusion) — which is the mechanism by which the merged implant causes lateral encroachment. BPSG was in commercial use for planarization well before 1991, so an examiner or challenger with the right secondary reference would likely prevail under KSR ("simple substitution of a known glass for a known purpose, with predictable results"); but on the record as cited, claims 8, 10 and 11 are the most defensible. Claim 10 is additionally the only independent claim that makes BPSG an express step, so it carries the same vulnerability/strength.

---

5. Why a POSITA would have combined these (the KSR motivation, consolidated)

1. Same field, same problem, same assignee. All primary art is directed to thermally stable MOS-on-printhead integration where high driver breakdown and low cost dominate ('192; '321; and the patent's own Background).
2. Express design incentive in the primary reference. '192 itself states the desirability of integrating the resistor "without additional process steps." The '250 patent's own stated object — replacing the separate arsenic and phosphorous mask/implant steps with one — is the direct and predictable consequence.
3. Market pressure. Both the '250 spec and its family members recite the driver: reducing mask levels (~20% cost saving; 11 masks → 9) and lead count for high-nozzle-count arrays. Cost/step reduction is a recognized design driver (KSR), and mask-count reduction is the predictable result of consolidating two same-type implants.
4. Finite, identified solutions. The '250 spec itself says the lateral-diffusion problem was solved by "one method… a n⁻ drift layer implant" and "a second method… borophosphosilicate glass," and that "the combination of the two… produces no deleterious effects." That is KSR's "finite number of identified, predictable solutions" almost verbatim — the patentee framed its contribution as choosing among two known options.
5. Established function of each element. LDD/drift layers prevent channel encroachment by high-concentration drain dopants ('618, JP S59-25244, and acknowledged in '192); masked simultaneous diffusion/implant into poly and substrate is standard ('185, '265,685); heavy end-doping of a poly resistor is standard ('421). Each is used for exactly its known purpose.
6. Predictable variation of a known technique to a similar device. KSR step 3 (a known technique improving one device would be recognized to improve similar devices in the same way): moving LDD/drift-layer engineering from generic MOSFETs into the printhead driver MOSFETs of '192 is that step.

---

6. Best non-obviousness / patentability arguments (and their weakness)

---

7. Claim-by-claim conclusion

---

8. Caveats, flags, and issues I will not paper over

1. § 103 availability of '192 is legally delicate — this nuances the prior section's characterization of '192 as "prior art." US 4,947,192 names the same two inventors (Hawkins & Burke) as '250, and issued 1990-08-07, less than one year before the 1991-01-02 '250 filing. It therefore appears not to qualify as prior art under pre-AIA § 102(a), (b), or (e) (no "by another" for § 102(e); no § 102(b) one-year bar). Its practical availability rests on (i) applicant's express incorporation by reference and Background characterization (an admission), and/or (ii) obviousness-type double patenting — which is consistent with the EP search report citing it as "D,A" rather than as X/Y art. A rigorous rejection should either rely on the remaining genuinely third-party references ('421, '185, '265,685, '618, '677) to supply the missing elements, or expressly invoke the admission. The combinations in §4 survive this because '421, '185, '618 and '265,685 are all indisputably by another and all pre-date the critical date — but the primary reference changes from '192 to a combination built on those references (e.g., Matsumoto '321 for the monolithic printhead context plus '185/'421/'618 for the process elements).
2. Unverified references. I could not retrieve content for JP S54-140488, JP S59-25244, US 5,013,677, or US 4,265,685 (only the title) or US 4,429,321 (only the '250 Background's own description of it). Statements above about those are correspondingly qualified; nothing in the core analysis depends solely on them.
3. US 5,013,677 (Sony) issued after the '250 filing date (1991-05-07) but claims a 1989-06-19 priority — it would be § 102(e)-type art only.
4. Claim-drafting ambiguity in claim 12, step (28), which recites implanting a "self-aligned p-type dopant to convert the n-type contacts to source-drain contacts." Read literally that converts the n-type contacts to p-type, whereas the specification applies the self-aligned boron implant only through vias over n⁻ drift regions to form p⁺ substrate contacts, leaving n⁺ sources/drains intact. This ambiguity broadens the claim and, if anything, helps an obviousness rejection (fewer structural constraints to distinguish). It is also a § 112(b) issue worth noting.
5. BPSG is the crux of any contested § 103 case. If coverage of claims 8, 10, and 11 is needed, the analysis cannot be completed from the patent's own Prior Art section; a BPSG/PSG-reflow secondary reference is required. I have not located or verified one within the record supplied.