US 11402413

I'll search for this specific patent and any related litigation.

US 11,402,413 B1 — "Droop detection and mitigation"

Bibliographic data (from the authoritative full text)

Assignment chain: MOHAN, NITIN and XANTHOPOULOS, THUCYDIDES → MARVELL SEMICONDUCTOR, INC. (2019-12-16) → MARVELL INTERNATIONAL LTD. (2019-12-16) → MARVELL ASIA PTE, LTD. (2020-10-15).

Litigation / PTAB search result: I found no CAFC 2026 docket, IPR, or district-court action naming patent 11,402,413. Searches for the bare string "11402413" returned an unrelated UK Companies House entry (HONED LIMITED, company no. 11402413) and unrelated litigation PDFs; these are false positives and I am not treating them as patent-related. Uncertainty note: the absence of a hit is not proof that no proceeding exists — CAFC dockets and PACER were not exhaustively queried, and my search tools returned no authoritative USPTO docket record for this patent beyond the grant, a certificate of correction, and the maintenance-fee payment.

Abstract (verbatim)

"In an embodiment, a method includes filtering, with a low-pass filter, a voltage signal (Vdd) of a chip to create a filtered signal (Vref). The method further includes dividing Vref by a given factor. The method further includes determining whether a voltage droop occurred in Vdd by comparing Vdd to the divided Vref. The method further includes outputting a droop detection signal if Vdd is less than the divided Vref. In an embodiment, dividing Vref by the given factor includes selecting, with a multiplexer, one of a plurality of divided Vref signals outputted by a voltage divider. The selecting is based on a selection signal."

⚠️ Analytic flag: the abstract (and much of the Summary/Detailed Description) is written in terms of a single generic Vdd/Vref pair, but the issued claims recite a dual-channel Vdd-1/Vdd-2 (root clock / local clock) architecture. The claims are therefore notably narrower than the abstract. Anyone relying on the abstract to characterize claim scope would be misled; the prosecution history likely shows amendment to distinguish prior art such as US 10,162,373 (Ampere Computing, "Variation immune on-die voltage droop detector") and US 10,784,874 (Intel).

Plain-language overview of the independent claims

Claim 1 — Method (dual-channel droop detection)
Filter two supply-voltage signals with a low-pass filter: Vdd-1 associated with the root clock of a chip and Vdd-2 associated with a local clock of the chip. This produces two clean references, Vref-1 (root) and Vref-2 (local). Divide both references by a given factor. Then compare the noisy Vdd-1 against the divided Vref-1, and Vdd-2 against the divided Vref-2. Emit a droop-detection signal if either comparison trips — i.e., Vdd-1 < divided Vref-1 or Vdd-2 < divided Vref-2. In short: a filtered-reference threshold detector covering both a global/root power domain and a local power domain, with an OR-ed output.

Claim 9 — Droop detection circuit (apparatus counterpart)
The same dual-channel concept in hardware: a low-pass filter that produces Vref-1 (root-clock domain) and Vref-2 (local-clock domain); a voltage divider that divides both references by a given factor; and a sense amplifier that performs both comparisons and outputs a droop-detection signal if either Vdd-1 < divided Vref-1 or Vdd-2 < divided Vref-2. The recited technique is thus slow-filtered reference vs. fast/noisy rail, sensed differentially, multiplexed threshold selection being left to dependent claim 10.

Claim 16 — Processor (system-level combination)
A processor comprising: a root clock; at least one local clock; a first droop detection circuit coupled to the root clock to detect a global voltage droop in a source voltage; a second droop detection circuit coupled to the local clock to detect a local voltage droop in the source voltage; and a droop mitigation circuit that, in response to either detector firing, reduces the frequency of the processor's root clock. This is the closed-loop aspect: detect (root or local) → throttle the root clock.

Dependent-claim highlights (context for scope)

• Cl. 2 / cl. 10: the "given factor" is set by a multiplexer selecting among voltage-divider taps under a selection signal (the vref_sel / VRef-Select input of FIGS. 1A–1B).
• Cl. 3–4 / cl. 11–12: the droop signal is latched in at least one SR latch, with a local SR latch cleared by a local FSM and a global SR latch cleared by a chip-global FSM.
• Cl. 5–6 / cl. 13–14: on detection, drop the chip from full frequency to a lower frequency, then ramp back up through at least one intermediate frequency between the two (the specification's f/2 → 2f/3 → 5f/6 → f stair-step).
• Cl. 7: comparison performed by a sense amplifier; sampled on both clock edges via a high-speed RCLK.
• Cl. 8 / cl. 15: droop events stored to a database (supporting the described monitor-only mode where mitigation is disabled but events are logged).
• Cl. 17: at least one local droop detection circuit located on the processor die.
• Cl. 18–19: the first/second droop detection circuits each include the low-pass filter, voltage divider, sense amplifier, and (cl. 19) the threshold-selecting multiplexer.

Minor drafting informalities worth noting: claim 14 recites "The system of claim 13" (premise mismatch — cl. 13 is a circuit claim); claim 17's "at least one local droop detection circuit being located on a die" is largely subsumed by claim 16's second droop detection circuit. These are form issues, not scope-defining, and may explain the 2023-01-24 certificate of correction.

Related Marvell family members surfaced

• US 11,545,987 B1 — "Traversing a variable delay line in a deterministic number of clock cycles" (priority 2018-12-12; Marvell Asia Pte)
• US 11,545,981 B1 / US 12,519,476 B1 — "DLL-based clocking architecture with programmable delay at phase detector inputs" (priority 2018-12-31; Marvell Asia Pte)
• US 10,784,871 B1 — "Clocking architecture for DVFS with low-frequency DLL locking" (Marvell Asia Pte)
• US 10,530,370 B1 — "Glitch-free PLL multiplexer" (Marvell International Ltd.)

Bottom line: US 11,402,413 is an active, Marvell-owned patent on dual-domain (root-clock + local-clock) on-die voltage-droop detection using a filtered reference divided and compared by a sense amplifier, paired with an FSM-driven frequency-throttle-and-restore mitigation loop. No CaFC 2026 appeal or other post-grant challenge to this patent was located in my searches; treat that as "not found" rather than "confirmed absent."

I'll research this patent's litigation history across the sources you specified.

Let me target the litigation-specific databases and the patent owner.

Summary of Findings

No litigation involving U.S. Patent No. 11,402,413 was found. Based on the searches performed, there does not appear to be any known federal district court action, appeal, or PTAB proceeding in which this patent has been asserted or challenged.

Searches Performed

I ran multiple searches targeting the litigation-tracking sources you named (Unified Patents litigation portal, PACER/CAFC-oriented queries) plus general web and patent-database searches:

• Direct queries on the patent number ("11402413", "11,402,413") in litigation contexts
• Queries combining the number with the owner ("Marvell") and litigation terms ("complaint," "infringement," "lawsuit," "District Court")
• Queries for PTAB/IPR challenges referencing the patent

What the Results Showed

Every result returned was unrelated to any asserted litigation for this patent. The hits fell into three categories:

1. Distinct patents with similar or overlapping digits — e.g., Wyeth/Merck vaccine patents referred to as "'024 patent" (a different patent, from the Pfizer v. Merck BLA litigation), and Delaware corporate-registration records containing the string "11402413." Per your instruction, I did not treat these as the patent at issue.
2. Marvell litigation involving other patents — the well-known Carnegie Mellon University v. Marvell Technology Group litigation (W.D. Pa. No. 2:09-cv-00290, Fed. Cir. 14-1492) concerned U.S. Patents 6,201,839 and 6,438,180, not 11,402,413.
3. The patent's own prosecution/PTAB-adjacent record — the Google Patents page for US11402413B1 lists its cited prior art (37 references), a few third-party citations to it, and non-patent literature, but shows no litigation tab entries, no PTAB proceedings, and no asserted-case list.

Patent Details for Reference

Force/technology: voltage-droop detection using a low-pass filter (V_ref), voltage divider/multiplexer, and sense amplifier, with SR-latch capture and clock-frequency mitigation (f/2, 2f/3, 5f/6). Classifications include G01R19/165, G06F1/28, G06F1/30.

Important Caveats

• This is a negative finding, not a certified clearance search. I could not directly authenticate into PACER, Docket Navigator, Lex Machina, or the Unified Patents litigation portal during this session; my conclusion rests on public search results and the patent's own record.
• The patent granted only in August 2022 and is still within the early portion of its term, so assertions could exist or arise that are not yet well indexed. Court dockets (especially recently filed complaints) may not surface in general web search.
• Recommended verification: run the number directly in Unified Patents' litigation case list (portal.unifiedpatents.com/litigation), Docket Navigator/Lex Machina "Patent" search, and the USPTO PTAB API, and confirm against Marvell's 10-K/10-Q litigation disclosures (which historically enumerate pending matters). If you want, I can draft the exact query strings for those systems.

Conclusion: On the evidence available, no known litigation exists for US 11,402,413, and no plaintiff, defendant, jurisdiction, case number, filing date, or outcome can be reported because no case was identified.

I'll verify the structured "no proceedings" signal with targeted searches before reporting.

Let me run additional targeted queries to be thorough.

No hits yet. A few final targeted checks before reporting.

PTAB proceedings on file — US 11,402,413

Bottom line up front: I found no AIA trial proceedings against US 11,402,413 in the USPTO Open Data Portal structured block, and my independent web searches (Google Patents, PTAB document repositories, CourtListener-indexed materials) surfaced none either. This is a zero-proceeding report, not a summary of outcomes. Everything below that is descriptive of the patent comes from the authoritative full text; everything about PTAB is an absence finding.

Proceedings overview

Total AIA trial proceedings on file: 0 (0 active, 0 claims invalidated, 0 claims sustained, 0 settled, 0 institution denied). The patent is therefore completely untested at the PTAB — all 19 claims, including independents 1, 9, and 16, stand as issued and unamended, and a defendant has no ready-made invalidity shield to import from a prior Board decision. The defensive posture is the opposite of "hardened by surviving IPRs": it is a blank slate, which cuts both ways — no estoppel binds you, but also no FWD gives you free claim cancellations.

Search methodology and confidence

Confidence: high that no PTAB proceeding exists as of the ingest date. I could not query PTAB E2E directly, so I flag the residual possibility of a very recently filed petition not yet indexed — but the ODP block is the canonical list and it is empty.

Important non-hits to rule out confusion: Marvell is an active PTAB petitioner in 2025, but in the opposite role and in unrelated technology — e.g., Marvell challenging Credo's active-electrical-cable patents (the '111 patent, IPR2025-00913 area), where Credo raised Fintiv/discretionary-denial arguments. Those proceedings involve different patents (Credo's, not Marvell's) and are not about the '413. Do not cite them as proceedings "on" this patent.

No per-proceeding entries follow, because there are no proceedings to describe. Per the constraints, I will not manufacture proceeding numbers, panels, or dispositions.

Strategic summary

Claim status. All of claims 1–19 are UNTESTED and INTACT. There is no IPR certificate, no disclaimer, no reissue, and no ex parte reexamination in the record that I could find. The three independents are:

• Claim 1 — a method reciting filtering both "a first voltage signal (V_dd-1) of a root clock of a chip" and "a second voltage signal (V_dd-2) of a local clock of the chip," dividing both, comparing both, and outputting a droop detection signal if either falls below its divided reference.
• Claim 9 — the circuit counterpart (low-pass filter + voltage divider + sense amplifier) covering the same dual root/local signal pair.
• Claim 16 — a processor with a root clock, at least one local clock, a first droop detection circuit on the root clock, a second on the local clock, and a droop mitigation circuit that reduces the root-clock frequency in response to either detection.

Note the prosecution narrowing: the abstract and specification describe a single V_dd/V_ref scheme, while the granted independent claims were written to require the root-clock/local-clock pair. Dependents 2–8 and 10–15 and 17–19 add the multiplexer-selected divided V_ref, SR latches (local vs. global, cleared by local vs. global FSM), the cascade of frequency steps (f/2 → 2f/3 → 5f/6 → f), the sense amplifier, and database logging. The dual-clock pairing in every independent claim is the most promising claim-construction and § 103 battleground — a prior-art system that detects droop on a single supply rail, without separately filtering and comparing a root-clock rail and a local-clock rail, may fall outside the claims or render them obvious depending on how "of a root clock" and "of a local clock" are construed.

Estoppel landscape. With no prior IPR/PGR, § 315(e)(2) estoppel is empty — no petitioner, privy, or real party in interest is barred from raising anything. Every ground is available to you: § 102 and § 103 on the art already cited during prosecution (including US 10,162,373 (Ampere Computing, "variation immune on-die voltage droop detector") and US 10,784,874 (Intel, "All-digital voltage monitor with single-cycle latency")) plus art neither the examiner nor any petitioner considered, and any § 112 written-description/enablement attack on the root-clock/local-clock claim language. Caveat: if you are a privy of Marvell or otherwise in privity with the patent owner, § 315(e)(1)/§ 325(e)(1) may still bar you from filing — check the real-party-in-interest chain before filing.

Pattern signals. No defensive aggregator (Unified Patents or similar) appears anywhere in the chain — consistent with no IPRs existing. Marvell Asia Pte Ltd is the assignee through a clean chain (Mohan/Xanthopoulos → Marvell Semiconductor → Marvell International → Marvell Asia, 2019-12-16 and 2020-10-15). This is an operating-company portfolio patent in a dense family (siblings US 11,927,612 "Digital droop detector," US 11,545,987, US 11,545,981), including a 2022-filed continuation — a signal that Marvell values the droop-detection line and may keep filing, though not that it is asserting the '413.

Absence-is-a-signal caveat (per your framing): with NPE-asserted patents you can usually expect IPRs eventually. The '413 shows no assertion activity and no IPR activity, which is most consistent with this being a portfolio/unused asset rather than a serial-litigation patent. That is a defensibility advantage for Marvell in one sense (no adverse record), but it also means no one has tested the claims — so a well-funded defendant today could plausibly be the first to file, with no institution-stage precedent to work around.

Recommended next steps

1. Confirm the null result at the source before relying on it. Run the patent number through PTAB Patent Trial and Appeal Board End-to-End (E2E) and the USPTO PatentCenter "Patent Trial" tab for US 11,402,413, and cross-check CourtListener's docket for any appeal styled Marvell Asia Pte, Ltd. v. … or any In re appeal. My searches could not reach these directly. Link: https://ptacts.uspto.gov/ptabweb/ and https://patents.google.com/patent/US11402413B1/en.
2. Check the family, not just this patent. The '413 is in a family with US 11,927,612, US 11,545,987, and US 11,545,981. A defendant served on the '413 should search PTAB for those numbers too — a proceeding there, even if not on the '413, can yield claim-construction and art that carries over, and privity relationships can create estoppel that spills into a later '413 IPR.
3. If no assertion has occurred, do nothing PTAB-wise yet. A pre-assertion IPR is often premature and can be mooted by claim amendments or a covenant not to sue. Instead, build the invalidity record now (claim chart against US 10,162,373 and US 10,784,874; claim-construction positions on "voltage signal … of a root clock"/"of a local clock") so a petition can be filed fast if a demand letter arrives.
4. Watch the § 315(b) clock. If you are sued or served with a complaint alleging infringement of the '413, the one-year bar under 35 U.S.C. § 315(b) starts on service. With a totally untested patent, the strategic question is whether to file IPR defensively at the one-year mark or rely on district-court invalidity — a decision that should be made with the dual-clock claim limitation as the centerpiece.
5. If a proceeding does exist that I could not find, treat this report as superseded and pull the institution decision and any FWD immediately; the analysis in "Strategic summary" would need to be redone at the claim level.

Explicit unknowns: I cannot confirm the existence or absence of (a) a petition filed in the last few weeks before the ingest date, (b) any ex parte reexamination or reissue, (c) any district-court assertion or ITC investigation involving the '413, or (d) any litigation-driven invalidity contention that has not reached the Board. I found nothing on any of these, but absence in web search is weaker evidence than absence in ODP, and I am stating it as such rather than asserting a verified negative.

I'll research the assignment record and litigation history for US 11402413 before assembling the report.

Let me dig deeper for the specific assignment records tied to application 16/704,483.

Ownership & Assignment Analysis — US 11,402,413 B1 ("Droop detection and mitigation")

Scope note / data limitation (read first). The Google Patents record for this patent reproduces three assignment legal events with parties and dates, but the capture provided to me does not include reel/frame numbers, execution dates, or correspondent data for those three events. I could not retrieve the Assignment Center record directly (https://assignmentcenter.uspto.gov/). I therefore report reel/frame below as "not retrieved — verify at Assignment Center" rather than inventing numbers. Every place where I substitute analogous Marvell evidence for missing record data, I label it explicitly as circumstantial.

Inventors

Unusual-pattern check — no red flags.

• No evidence of any inventor departing the original assignee within 12 months of filing; both inventors continued filing Marvell work product (Mohan on 16/709,367 filed five days after this application).
• No inventor-to-individual or inventor-to-third-party assignments appear anywhere in the chain — the inventors assigned directly and only to the operating company's U.S. subsidiary.
• Small two-inventor team on a single large operating company's internal clocking/IP program is the opposite of the pre-fire-sale pattern (which typically shows a broad inventor list, immediate abandonment, or withdrawal of prosecution).

Original assignee

Marvell Asia Pte Ltd (Singapore) is the assignee named on the face of the issued patent, as reflected in both the "Current Assignee" and "Original Assignee" fields of the Google Patents record.

Product/practice status. Marvell is an operating, publicly traded semiconductor company (NASDAQ: MRVL) that ships data-infrastructure silicon — custom/accelerated compute ASICs, OCTEON/ARM server processors, storage controllers, Ethernet PHYs and switches. Droop detection with adaptive root-clock throttling is a real, shipping-technology area for that product line: the claims recite exactly the root-clock/local-clock droop detection plus clock division that appears in high-performance SoC clocking — the same design space Marvell litigates in (see the Credo/Marvell ITC and PTAB matters in which Marvell appears as a defending party and petitioner, e.g. Credo's ITC complaint and Marvell's IPR petitions on the '252 patent).

Corporate status. Operating. The immediate legal-entity history is that Marvell Technology Group Ltd (Bermuda) held the group through Marvell International Ltd (Bermuda) and Marvell Semiconductor, Inc. (California), and after the Cavium acquisition (closed 2018) the group consolidated IP into Marvell Asia Pte Ltd (Singapore) and later redomiciled into Delaware (Marvell Technology, Inc.). No bankruptcy, receivership, or wind-down.

Assignment timeline

All three post-filing events appear in the Google Patents "Assigned to…" legal-event feed. Reel/frame, execution dates and correspondent are not present in the source I have; treat the entries below as party/date-verified only.

• execution date not retrieved / recorded 2019-12-16 — Reel not retrieved — verify at Assignment Center

  • Conveyance: Assignment (inventor-to-company, employment/obligation assignment)
  • Assignor: Mohan, Nitin; Xanthopoulos, Thucydides (individual inventors)
  • Assignee: Marvell Semiconductor, Inc. (California)
  • Correspondent: not retrieved for this patent. Circumstantial: Marvell's recordings for other applications in the same docket window repeatedly name Kelvin Vivian, 5488 Marvell Lane, Santa Clara, CA 95054 as correspondent/submitter (reels 043106/0117, 045187/0722, 045553/0868, 050807/0225, all Marvell in-house recordations, executed 2017–2019). If the same correspondent appears on this reel it is routine in-house corporate IP-department filing, not an NPE tell — this is the patent owner's own legal department, not a third-party recording agent.
  • Context: Standard inventor assignment to the operating company's U.S. subsidiary; not a sale.

• execution date not retrieved / recorded 2019-12-16 — Reel not retrieved — verify at Assignment Center

  • Conveyance: Assignment
  • Assignor: Marvell Semiconductor, Inc.
  • Assignee: Marvell International Ltd. (Canon's Court, 22 Victoria Street, Hamilton HM12, Bermuda)
  • Correspondent: not retrieved for this patent. Circumstantial: the identical assignor→assignee pair and Bermuda address appear on Marvell reel 045187/0722 (executed 2017-12-20, recorded 2018-03-13, correspondent Kelvin Vivian, Marvell Semiconductor docket series "MP…"), confirming this is the group's standard MSI→MIL domestic-to-Bermuda IP-stacking flow.
  • Context: Internal corporate reorganization / IP holding-structure transfer inside the Marvell group. Consideration of US$1.00 plus other good and valuable consideration is the standard form used on Marvell's intra-group deeds (compare reel 043106/0117 and 045553/0868).

• execution date not retrieved / recorded 2020-10-15 — Reel not retrieved — verify at Assignment Center

  • Conveyance: Assignment (group IP consolidation)
  • Assignor: Marvell International Ltd.
  • Assignee: Marvell Asia Pte, Ltd. (Singapore)
  • Correspondent: not retrieved for this patent.
  • Context: Internal corporate reorganization — the post-Cavium migration of the Marvell patent estate to the Singapore IP-holding entity. Corroborated outside the U.S. record: the Canadian IP Office change-in-title register shows Marvell International Ltd → Marvell Asia Pte, Ltd., date of change 2019-12-31, registered 2021-01-14. A single global entity migration dated end-of-2019 that shows up as a 2020 U.S. recording is the signature of a corporate IP-housekeeping sweep, not a sale and not a transfer to an asserter.

No other recorded assignments exist for this patent in the sources I could reach — no security agreement, no license recordation against the patent itself, no release, no change-of-name, no transfer to any third party. The patent has never left the Marvell corporate family. Note that Marvell does record exclusive licenses between group entities on other applications (e.g. reels 045553/0868 and 050807/0225, Marvell World Trade Ltd → Marvell International Ltd, conveying "the right to sue and recover damages for past, present and future infringement"). Those license-conveyance records are worth checking at the Assignment Center for this patent specifically, because a recorded exclusive license with standing-to-sue language can matter for standing — but even if present, it is an intra-group license, not an NPE transfer.

Timeline diagram

timeline
    title Ownership of US 11402413
    2018 : Provisional application filed
    2019 : Non provisional filed
    2019 : Inventors assign to Marvell Semiconductor Inc
         : Marvell Semiconductor assigns to Marvell International Ltd
    2020 : Marvell International assigns to Marvell Asia Pte Ltd
    2022 : Patent issued
    2023 : Certificate of correction

NPE / troll-pattern signals

Complementary check on the citation neighborhood (not ownership evidence, but useful for the "is this a troll patent" question): the patents citing/cited around US 11,402,413 belong to operating and academic entities — Ampere Computing (US 10,162,373, "Variation immune on-die voltage droop detector"), Synopsys (US 12,504,449, "Supply voltage droop detector"), Samsung, Qualcomm (WO2026080179A1), Bar Ilan University. No NPE citation clustering.

Verdict

Insufficient data — with the affirmative finding being that all eight NPE signals are not present and the chain is a clean intra-group corporate reorganization.

The entire recorded chain is three intra-family events: inventors → Marvell Semiconductor, Inc. (recorded 2019-12-16), Marvell Semiconductor, Inc. → Marvell International Ltd. (recorded 2019-12-16), and Marvell International Ltd. → Marvell Asia Pte, Ltd. (recorded 2020-10-15, corroborated by a parallel Canadian change-in-title dated 2019-12-31). That last step is the post-Cavium migration of the Marvell estate to its Singapore IP holder, and Marvell Asia Pte, Ltd. remains the assignee today and is still paying maintenance fees (2026-01-20) with the patent live to 2040-11-25. I deliberately did not elect "Operating-company assertion" because that verdict requires evidence the current owner is suing competitors on these claims, and no suit naming US 11,402,413 was found.

Verification links:

• USPTO Assignment Center: https://assignmentcenter.uspto.gov/ (search patent number 11402413 to retrieve reel/frame, execution dates and correspondents — the three items I could not confirm)
• Legacy assignment search (where the Marvell cover sheets I cite live): https://assignment.uspto.gov/patent/index.html
• Patent page: https://patents.google.com/patent/[US11402413B1](/patent/US11402413B1)/en

Two concrete follow-ups worth running, since my reel/frame fields are blank rather than negative:

1. Pull the three reel/frame entries for 16/704,483 and confirm (a) the correspondent on each, and (b) whether any is a License conveyance rather than an Assignment — Marvell records intra-group exclusive licenses with the right to sue on some applications (see reel 050807/0225, docket MP11083), and a standing-to-sue license on this patent would be a materially relevant fact.
2. Confirm at the Assignment Center whether an event falls between 2019-12-16 and 2020-10-15 that Google's legal-events feed did not surface.

I'll search for the patent and examine its citations.

Let me examine the key cited references in more detail.

Let me characterize several more of the cited references.

Prior-Art Analysis — US 11,402,413 B1 ("Droop detection and mitigation")

1. Search scope and confirmation of the record for 11402413

I searched for the specific number 11402413. The authoritative result is the Google Patents rendering of the USPTO record for US 11,402,413 B1, application 16/704,483, Marvell Asia Pte Ltd, filed 2019-12-05, priority 2018-12-12, granted 2022-08-02 — matching the previously generated bibliographic section exactly. I did not locate a separate USPTO PatentCenter/PatFT or USPTO "Patent Public Search" HTML page in my tool results; the citation lists below are taken from the USPTO-sourced full text already supplied (which reproduces the front-page "References Cited"), so I treat that list as the ground truth. Note the bare string 11402413 also matches a UK Companies House number (per the earlier section) — a false positive I am not using.

Important procedural caveat repeated from the earlier section: the record shows a certificate of correction dated 2023-01-24. If claim text was corrected there, any claim-mapping below should be re-verified against the corrected claim set; the full text used here is the pre/post-correction rendering available from Google Patents.

2. Analytical framing (why this matters for a § 102 answer)

Two things must be kept in view, because they determine whether a citation is anticipatory (§ 102) or merely combinable (§ 103):

1. The critical date. The effective filing date is 2018-12-12 (provisional 62/778,375). Under AIA § 102:
   • a reference published/patented before 2018-12-12 is § 102(a)(1) art;
   • a US patent/application effectively filed before 2018-12-12 but published later is § 102(a)(2) art;
   • a reference whose earliest US filing date is after 2018-12-12 is not § 102 prior art at all.
2. The claims are narrower than the specification. As flagged in the prior section, independent claims 1, 9 and 16 all recite a dual-channel (Vdd‑1 root clock / Vdd‑2 local clock) architecture plus low-pass filtering of each rail. Any anticipation theory must disclose both channels and the filtering. No reference on the face of the patent does.

Bottom-line up front: No listed reference appears to disclose every element of independent claim 1, 9 or 16. Accordingly, the citations are best characterized as § 103 obviousness art (and as art against individual dependent claims if the dual-channel limitation were read out), not as clean § 102 anticipators. I have flagged, for each reference, the specific claim(s) it is most relevant to, and my confidence.

3. Tier A — References that most closely approach the droop-detection claims

3.1 US 10,162,373 B1 — "Variation immune on-die voltage droop detector"

• Full citation: Yan Chong, Luca Ravezzi, Alfred Yeung, Hamid Partovi; US 10,162,373 B1; App. 15/444,780; assignee Ampere Computing LLC.
• Dates: priority/filed 2017-02-28; granted/published 2018-12-25.
• § 102 status: § 102(a)(1) and (a)(2) art (granted before, and filed before, 2018-12-12).
• Description: An on-die droop detector in which a voltage calibrator converts a first (PDN) supply voltage to a second supply voltage via a resistance ladder circuit; a voltage selection circuit selects one voltage value from the set produced by the ladder; a comparator emits a comparison output when the selected voltage vs. a reference voltage satisfies a defined criterion; a sampler synchronously samples the comparison output to produce a droop-detection signal; and a logic control component modifies the frequency of the system clock in response to detection. Its companion (see §3.4) generates the reference from the supply via voltage divider → low-pass filter → unity-gain buffer.
• Claims it potentially anticipates / is most relevant to:
  • Claim 2 / claim 10 — "selecting, with a multiplexer, one of a plurality of divided Vref signals outputted by a voltage divider … based on a selection signal": the '373 "voltage selection circuit … select a voltage value from the set of voltage values" is a strong, potentially anticipating disclosure of the divider + selectable tap concept (moderate confidence; the labels are ladder/selection-circuit rather than divider/multiplexer).
  • Claim 7 — comparison by a comparator/sense amplifier: strong mapping.
  • Claim 5 / claim 13 — reduce clock frequency on detection: strong mapping ("modify a frequency of a system clock signal in response to detection of the droop detection signal").
  • Claim 1 / claim 9 / claim 16: Not anticipated — '373 discloses a single detection path and uses a resistance-ladder reference generator; it does not disclose low-pass-filtering of two rails (Vdd‑1 root / Vdd‑2 local), nor two detector circuits respectively coupled to a root clock and a local clock.
• Net: the single most relevant droop-detector reference, but as § 103 art against claims 1/9, and as possible § 102 art against the more specific dependent claims only if the preamble limitations are met.

3.2 US 2004/0017234 A1 — "VCC adaptive dynamically variable frequency clock system for high performance low power microprocessors" (granted as US 6,762,629 B2, Tam et al.)

• Full citation: Simon M. Tam, Stefan Rusu; US 2004/0017234 A1 (granted US 6,762,629 B2); App. 10/206,610; assignee Intel Corporation.
• Dates: filed 2002-07-26; published 2004-01-29; granted 2004-07-13.
• § 102 status: § 102(a)(1) art (published 2004).
• Description: A processor samples supply voltage at a plurality of locations on the die using distributed voltage sensors (e.g., ring-oscillator sensors) plus a local reference sensor adjacent the clock generator; the sensor values are communicated to a clock generator whose output frequency is adjusted in response to evaluation of the sampled values, expressly "to avoid performance errors" from voltage droops/transients and "to continue to operate despite non-optimal voltage conditions at certain locations on the die."
• Claims it potentially anticipates / is most relevant to:
  • Claim 16 (processor) — the closest conceptual match: multiple voltage sensors (local + reference) feeding a clock generator that varies the root clock frequency when a droop is sensed somewhere on the die. A § 103 combination of Tam's architecture with a filtered-reference comparator (§3.1) is the natural examiner theory. As a bare § 102 anticipation it is weak, because Tam's sensors are delay/ring-oscillator transducers, not a low-pass-filtered, divided reference compared in a sense amplifier, and Tam does not recite a "first droop detection circuit coupled to the root clock" distinct from a "second … coupled to the local clock."
  • Claim 5 / claim 13 — reducing clock frequency responsive to a sensed droop: moderate mapping (Tam ramps frequency to the highest value the sensed voltage supports rather than the f→f/2 stair-step of §3.4-claims 6/14).
  • Claim 17 — local detectors on the die: good mapping.
• Net: the most relevant "system-level / closed-loop mitigation" reference, principally a § 103 reference for claim 16.

3.3 US 10,162,373's sibling — US 10,145,868 B2, "Self-referenced on-die voltage droop detector" (same inventors/assignee)

• Dates: filed 2016-03-14, granted 2018-12-04.
• Why I raise it: it is not on the face of 11,402,413, yet it is arguably the closest single reference to the disclosure of 11,402,413's Figures 1A–1B, because it discloses voltage divider → low-pass filter → unity-gain buffer (Vref) → comparator vs. transient supply → synchronously sampled droop output → DVFS logic. That is essentially the single-channel version of the 11,402,413 droop detector.
• Claims it is most relevant to: claim 1's filter/divide/compare sequence (if read on one channel) and claim 9's filter + divider + comparator; claim 5/13 mitigation.
• § 102 caveat: it is single-channel; like §3.1 it does not anticipate the dual root/local-channel limitation of claims 1/9/16. Worth raising with the applicant/examiner because a § 103 combination (Chong '868/'373 + Tam) squarely covers claims 1/5/7/9/13/16.

3.4 US 10,784,874 B1 — "All-digital voltage monitor (ADVM) with single-cycle latency" (Intel) — listed, but chronologically impossible as § 102 art

• Full citation: Muhammad Khellah, Eric Samson, Charles Augustine, Suyoung Bang, Wootaek Lim; US 10,784,874 B1; App. 16/783,096; assignee Intel Corporation.
• Dates: filed 2020-02-05; granted 2020-09-22. (Continuation published as US 2021/0242872 A1, granted US 11,211,935 B2.)
• Description: An all-digital droop monitor that uses the Vcc-dependence of gate delay — a delay chain/time-to-digital converter converting the rail voltage to a thermometer code each cycle (single-cycle latency) — rather than a filtered analog reference.
• § 102 conclusion: It cannot be prior art to 11,402,413. Its earliest filing (2020-02-05) postdates both the 2018-12-12 priority date and the 2019-12-05 filing date. It is therefore neither § 102(a)(1) nor § 102(a)(2) art and is not usable in an obviousness combination either. Flag: its appearance in the patent's citation list is anomalous and suggests the citation set includes art cited in related Marvell filings or is otherwise aggregated — see §6. Confidence: high on the date analysis; moderate on why it appears in the list.

4. Tier B — Mitigation / DVFS-throttling references (relevant to claims 5–6, 13–14, 16)

None of these discloses the filtered-reference/dual-channel detection of claim 1/9/16; they bear on the mitigation half of the invention (claims 5–6, 13–14) and on the general background of frequency throttling.

5. Tier C — Clock-generation / DLL-PLL references (largely peripheral to the droop claims)

The remaining ~25 citations are directed to delay-locked-loop, PLL, clock-distribution and phase-detector art. They are not anticipatory of any droop-detection claim and appear to relate instead to the sibling Marvell patents in the same family (US 11,545,987; US 11,545,981 / US 12,519,476; US 10,784,871; US 10,530,370 — see §6). Representative entries:

• US 6,285,230 B1 — Input buffer circuit with adjustable delay via external power voltage (Hyundai Electronics) — filed 1999-04-07, pub. 2001-09-04.
• US 2002/0079937 A1 — Digital delay-locked loop with wide dynamic range and fine precision (Thucydides Xanthopoulos — a named co-inventor of 11,402,413) — filed 2000-09-05, pub. 2002-06-27. Notable: applicant's own prior work.
• US 2002/0097592 A1 — Frequency voltage converter (Hiroshi Komurasaki) — filed 2001-01-24, pub. 2002-07-25.
• US 6,600,345 B1 — Glitch-free clock-select switch (Analog Devices) — filed 2001-11-15, pub. 2003-07-29. Potentially relevant to the clock multiplexer 342/344 of the specification, not to the droop claims.
• US 6,686,785 B2 — Deskewing global clock skew using localized DLLs (Sun Microsystems) — filed 2001-10-11, pub. 2004-02-03.
• US 7,145,831 B2 — Data synchronization arrangement (Texas Instruments Deutschland) — filed 2004-03-10, pub. 2006-12-05.
• US 2007/0170967 A1 — Multi-phase clock generator (Postech Foundation) — filed 2006-01-23, pub. 2007-07-26.
• US 2007/0194815 A1 — Enhanced delay-matching buffer circuit (Dale Nelson) — filed 2006-02-23, pub. 2007-08-23.
• US 7,551,909 B1 — CMOS transceiver with dual current-path VCO (Silicon Image) — filed 2002-08-29, pub. 2009-06-23.
• US 7,764,095 B2 — Clock distribution network supporting low-power mode (Rambus) — filed 2005-12-22, pub. 2010-07-27.
• US 7,952,404 B2 — Modeling coarse step-size delay element; DLL using same (Mosaid) — filed 2008-08-15, pub. 2011-05-31.
• US 7,971,088 B2 — Clock-skew controller and IC including the same (Samsung) — filed 2007-02-27, pub. 2011-06-28.
• US 2012/0068748 A1 — Phase detection method and phase detector (Cisco) — filed 2009-05-12, pub. 2012-03-22.
• US 2013/…, US 2014/0347107 A1 (Magnachip DLL), US 2014/0327478 A1 (National Sun Yat-Sen synthesizer), US 2015/0162921 A1 (TSMC PLL), US 2015/0213873 A1 (Samsung injection-locked PLL), US 9,425,779 B2 (SK Hynix delay circuit), US 9,654,121 B1 (IDT PLL calibration), US 2018/0351770 A1 (Regents of Univ. of Minnesota, time-based DFE) — all clock/phase/delay art.
• Later-published US applications (all § 102(a)(2)-eligible because their US filing predates 2018-12-12, but only if the disclosure supports the mapping): US 2018/0351770 A1 (2017-06-02), US 2019/0007055 A1 (Analog Devices, 2017-06-28), US 2020/0044657 A1 (Newcosemi, 2017-11-10), US 2020/0076439 A1 (Analog Devices Intl., 2017-06-28), US 2020/0083891 A1 (Anapass, 2017-11-27), US 2020/0076440 A1 (IHP GmbH, 2018-09-03).
• US 2014/0195081 A1 — slow-charger / system and method for a vehicle with electric motor (Hyundai Motor) — filed 2012-12-28, pub. 2014-07-10. This citation appears to be an irrelevant/erroneous citation for a droop-detection patent; I flag it as likely a noise entry in the citation set. Confidence: moderate.

§ 102 conclusion for Tier C: no Tier-C reference is anticipatory of claims 1, 9 or 16; several are § 103-relevant only to incidental features (e.g., glitch-free clock multiplexing for the clock-division module, or DLL-based clock distribution).

6. Cross-reference, contradictions and anomalies to flag

1. Contradiction / anomaly — the citation list contains post-critical-date references. Two entries cannot be prior art to 11,402,413:

   • US 10,784,874 B1 (Intel): earliest filing 2020-02-05 — after both the 2018-12-12 priority and the 2019-12-05 filing.
   • US 10,784,871 B1 (Marvell Asia Pte, "Clocking architecture for DVFS with low-frequency DLL locking"): priority 2018-12-31 — after the 2018-12-12 priority date.

   Because the list also contains a large body of DLL/PLL art matching the sibling Marvell patents (US 11,545,987; US 11,545,981 / US 12,519,476), my assessment is that the fetched "Patent Citations (37)" set is a family/aggregated citation set rather than the strict front-page "References Cited" of this patent. Do not rely on this list verbatim as the IDS of 16/704,483 without confirming against the USPTO PatentCenter "References Cited" tab. Confidence: moderate; the date arithmetic is certain, the explanation for it is inferred.

2. Sibling Marvell patents cited in the same list (US 10,530,370 B1 priority 2018-11-21 → § 102(a)(2)-eligible; US 11,545,987 / US 11,545,981 — priority 2018-12-31 → not § 102 art) are commonly owned and are the relevant § 102(b)(2)(C)/§ 103(c) "commonly owned" set to check for double-patenting and for obviousness-type double patenting rather than anticipation.

3. Non-patent citations on the face (Senger ISCAS 2006; Sidiropoulos JSSC 1997; Zoni DVFS framework 2015; and the two Marvell co-pending applications 16/528,311 and 16/709,367) are likewise clock/DVFS background; only Zoni touches DVFS power-performance, and none discloses the claimed dual-channel detector. These are not § 102 art for claims 1/9/16 on their face.

4. Claim 14 premise defect ("The system of claim 13" — cl. 13 is a circuit claim) and claim 17's overlap with claim 16, noted in the prior section, are relevant here because they affect which dependent claims a given reference must be mapped against; the 2023-01-24 certificate of correction may have addressed them.

7. Bottom line answers to the task

• Most relevant prior art: US 10,162,373 B1 (Ampere Computing) and its sibling US 10,145,868 B2 for the detection architecture (divided/selectable reference → comparator → synchronously sampled droop signal → clock-frequency modification), and US 2004/0017234 A1 / US 6,762,629 B2 (Tam, Intel) for the system/closed-loop concept (multiple on-die voltage sensors + local reference sensor → adjust root clock frequency to ride through droops at specific die locations).
• Which claims they potentially anticipate under § 102: On the face of the record, none of the 37 citations anticipates independent claim 1, 9 or 16, because none discloses the claimed dual root-clock/local-clock channel (Vdd‑1 / Vdd‑2) combined with low-pass filtering of each rail. The strongest § 102 candidates against dependent limitations are:
  • US 10,162,373 B1 → claims 2/10 (divider + selection circuit/multiplexer) and 7 (comparator); and 5/13 (frequency modification on detection) — moderate confidence.
  • US 2004/0017234 A1 → claim 16 and 17 (multiple/local sensors + frequency adjustment) — weak-to-moderate as § 102; strong as § 103.
  • US 10,145,868 B2 → claims 1/9 on a single-channel reading — moderate, defeated by the dual-channel limitation.
• Every other citation maps, at best, to the mitigation/DVFS or clock-generation background and is § 103 art only, or is not prior art at all (US 10,784,874; US 10,784,871).

Confidence and honesty statement: I have high confidence in the bibliographic dates quoted (they come from the authoritative full text and corroborating search hits) and in the § 102 date classification. I have moderate confidence in the detailed element mapping for the three Tier-A references, because my searches returned their abstracts/specification excerpts but not full claim charts, and I could not retrieve an independent USPTO PatentCenter "References Cited" page within my search budget — and because the supplied citation list appears to be an aggregated/family set (see §6). If claim text was changed by the 2023-01-24 certificate of correction, re-map against the corrected claims before relying on any anticipation call.

I'll ground this § 103 analysis in the specific references listed in the "Prior Art" section of the Google Patents page, and pull their actual disclosures where I can.

Obviousness Analysis — U.S. Patent No. 11,402,413 B1 (35 U.S.C. § 103)

0. Frame of this analysis (building on the earlier sections)

The earlier summary flagged the central fact I rely on here: the issued claims recite a dual-channel Vdd-1/Vdd-2 (root-clock / local-clock) architecture, while the specification and abstract describe a single generic Vdd/Vref pair. That divergence almost certainly reflects prosecution amendments made to escape single-detector art — most plausibly the self-referenced on-die detector art appearing in this patent's own prior-art section. Accordingly, the § 103 inquiry below is not "is a filtered-reference droop detector obvious?" (it plainly is — the patent's own cited art says so) but rather "would it have been obvious to replicate that known detector across a root/global domain and a local domain and OR the outputs?"

Legal framework applied: Graham v. John Deere, 383 U.S. 1 (1966); KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007) (predictable combination of known elements; "obvious to try"; design incentives/market demand); In re Harza (duplication of parts); MPEP § 2143 (articulated reasoning requirement).

Caveat on sources: I have verified the disclosures of the principal references below from their texts. I have not re-read every one of the 37 cited references in full; where I extrapolate from title/known subject matter I say so. This is an analyst's prima facie case, not a legal opinion or a validity clearance.

1. Independent claim 1 — element-by-element prior-art map

Result: Every element of claim 1 is disclosed or rendered obvious by the combination of the Ampere self-referenced detector ('868/CN109477861B) and Ampere '373, plus Tam for the dual-domain/OR aspect. No single reference anticipates claim 1 (each Ampere detector is single-channel; Tam does not use a filtered-reference sense-amp detector), so this is a § 103 case, not § 102.

2. Combination 1 (primary): Ampere '373 + Tam '234 [+ Ampere self-referenced '868 / CN109477861B]

This is the strongest three-reference combination.

What each teaches (verified):

• U.S. 10,162,373 B1 — Ampere, "Variation immune on-die voltage droop detector" (https://patents.google.com/patent/US10162373B1/en). Resistance-ladder voltage conversion of the on-die supply; comparator against a self-generated reference; synchronous sampler; droop-detection output; and — critically for claim 16 — "MODIFY, VIA A LOGIC CONTROL COMPONENT, A FREQUENCY OF A SYSTEM CLOCK SIGNAL IN RESPONSE TO DETECTION OF THE DROOP DETECTION SIGNAL." It also recites a "voltage selection circuit … select a voltage value from the set of voltage values" (the multiplexer-over-divider of claims 2/10).

• Ampere "Self-referenced on-die voltage droop detector" (U.S. 10,145,868 B2; sibling CN109477861B appears on the '413 page under Similar Documents) (https://patentimages.storage.googleapis.com/dd/fa/9d/956d5f3b77950c/US10145868.pdf). On-die voltage divider → low-pass filter (cutoff below droop resonant frequency) → unity-gain amplifier → reference voltage → comparator against transient supply → synchronous sample → droop output. This supplies claim 1 element (a) verbatim, including the low-pass filter the '413 patent treats as a point of novelty.

• Tam, U.S. 2004/0017234 A1 / U.S. 6,762,629 (Intel) (https://patents.google.com/patent/US20040017234A1/en). Expressly teaches multiple voltage sensors distributed at different locations on the die plus a reference sensor at the clock generator, evaluating them together and reducing the clock frequency so it is "sufficiently low to avoid timing errors at said lowest value for said supply voltage." Tam's specification is unusually on-point as a motivation statement: a "local sensor in a high activity area such as the FPU … can better indicate the existence of a critical low voltage condition in that circuitry and inform the clock generator of a need to lower the operating frequency."

Motivation to combine (KSR/PQIA):

1. Same field, same problem, same solution family. All three address on-die supply-voltage droop in high-performance/low-power processors and adaptive clock throttling.
2. Tam expressly supplies the design incentive to add local detectors to a reference/global detector — i.e., the very root clock vs. local clock dichotomy the claims recite. Tam's claim 17 (first sensor at a logic block + reference sensor at a reference location + clock generator responsive to both) is a near-literal template for claim 16.
3. Duplication of a known part at known locations (In re Harza). Once a single on-die filtered-reference detector is known ('868/'373), replicating it at the die locations where droop is expected is a predictable, mechanical duplication.
4. Applicant's own admissions reinforce obviousness: the '413 specification states "[t]he droop detection circuit can be placed at multiple places on a chip" and describes "local droop detector circuits … placed at other places on the chip that may experience local droop voltages." The specification itself concedes the multi-detector topology as conventional.

Reasonable expectation of success: Both Ampere and Tam detectors are silicon-proven on-die circuits; combining two droop detectors and OR-ing their outputs (min/lowest-value selection in Tam) is a purely aggregative result.

3. Combination 2 (alternative): Qualcomm VTCG + Tam + Ampere (targets claims 5–6/13–14)

WO 2017/222620 A1 / U.S. 9,628,089 (Qualcomm), "Supply voltage tracking clock generator in adaptive clock distribution systems" — listed on the '413 page under Similar Documents (https://patents.justia.com/patent/9628089). It discloses a voltage droop detector and a clock generator whose "frequency … is finely tuned to one of two or more values to correspond to a magnitude of the supply voltage during the voltage droop," i.e., intermediate frequencies between full frequency and a reduced frequency — the precise subject matter of claims 6/14 (f/2 → 2f/3 → 5f/6 → f stair-step). Tam independently teaches that the adjustment should "gradually follow the voltage changes" without "large adjustments to catch up with big voltage steps," which supplies the motivation to ramp rather than jump.

Toshiba U.S. 9,531,269 B2 (""Semiconductor device,"https://patentimages.storage.googleapis.com/92/36/ab/54a5b6098630df/US9531269.pdf) adds corroboration for the mitigation leg: an error-calculation circuit comparing VDD to Vref, a compensation circuit, and a frequency/phase adjustment circuit for the SoC clock — i.e., comparator-on-supply → throttle-clock.

4. Combination 3: dependent-claim specifics

5. Anticipation note (§ 102)

No cited reference, taken alone, appears to anticipate independent claims 1, 9, or 16:

• Ampere '373 and the '868/CN109477861B family are single-reference-domain detectors.
• Tam is multi-sensor, but its sensors are ring-oscillator/A-D types, not a low-pass-filtered-reference sense-amp comparator.
• WO'620/'089 is a track-and-select architecture, not a dual filtered-reference detector.

So the viable attack is § 103, which is what was asked.

6. Anomalies and counter-arguments to flag

1. U.S. 10,784,874 B1 (Intel, "All-digital voltage monitor (ADVM) with single-cycle latency") is listed in the '413 prior-art section, but its stated priority/filing date (2020-02-05) postdates the '413 priority date (2018-12-12) and filing date (2019-12-05). As listed, it is not available as § 102(a)(1)/(a)(2) art and should not be relied on unless it proves entitlement to an earlier effective filing date. I flag this as a data anomaly rather than treating the listing as proof of prior-art status. (The other Marvell-family citations — U.S. 10,530,370 and U.S. 10,784,871 — are same-assignee art and are at most § 102(e)/(a)(2) candidates depending on dates.)
2. Patentee's best nonobviousness arguments: (i) Tam's sensors are ring-oscillator/ADC-based, arguably teaching away from a filtered-reference sense-amp detector; (ii) the self-referenced Ampere art emphasizes a single supply-derived reference, arguably teaching against per-domain references; (iii) the OR-ed dual-channel architecture with independent local/global latch-clearing FSMs is not squarely shown in any one reference. Each is a "teaching away"/"no suggestion" argument that the KSR-sanctioned motivation evidence in Tam (local FPU sensor informing the clock generator) and the applicant's own specification admissions tend to rebut.
3. Procedural posture: These references were before the examiner, and the claims issued in their presence. A § 103 challenge is therefore strongest if it is framed as a combination not made of record — specifically Ampere '373 (or '868) in view of Tam for the dual root/local domain, which the file history does not appear to have squarely addressed.
4. No demonstrated secondary considerations (commercial success, nexus, unexpected results) are of record in the material reviewed.

7. Bottom line

The independent claims are reasonably likely to be invalid under § 103 over Ampere U.S. 10,162,373 B1 (resistance-ladder divider + comparator + sampler + droop signal + system-clock-frequency modification) in view of Tam U.S. 2004/0017234 A1 / 6,762,629 (distributed local sensors plus a reference sensor, evaluated to the lowest supply value, driving clock frequency reduction), optionally with the Ampere self-referenced detector (U.S. 10,145,868 / CN109477861B) supplying the express low-pass-filtered Vref. The dependent claims fall with Qualcomm WO 2017/222620 / U.S. 9,628,089 (intermediate-frequency values → claims 6/14) and Toshiba U.S. 9,531,269 (VDD-vs-Vref error → clock adjustment → claims 5/13). The claim 4/12 local-vs-global FSM latch-clearing and claim 8/15 "database" storage limitations are the least-well-met and constitute the patentee's most defensible positions.

Confidence: high that a prima facie § 103 case exists against claims 1, 9, 16 and most dependents; moderate against claims 4, 8, 12, and 15. This is an analyst's assessment based on the prior-art section of the Google Patents page plus verified reference texts, not a legal opinion.