Prior art

Analysis of Prior Art Cited in U.S. Patent 11,121,222

An analysis of the prior art cited during the examination of U.S. Patent 11,121,222, "Semiconductor devices with graded dopant regions," provides insight into the patent landscape at the time of invention and the specific documents considered by the USPTO examiner. Under 35 U.S.C. § 102, a patent claim is anticipated if every element and limitation of the claim is found, either explicitly or inherently, in a single prior art reference. The following is an evaluation of the most relevant cited references and their potential to anticipate the independent claims of the '222 patent.

Key Cited Prior Art References

The following patents and patent applications were cited by the examiner and are considered relevant to the core concepts of the '222 patent.

1. U.S. Patent No. 6,310,366 B1

• Full Citation: Rhodes, Howard E. Retrograde well structure for a CMOS imager. Micron Technology, Inc., assignee. 30 Oct. 2001.
• Filing Date: June 16, 1999.
• Brief Description: This patent describes a CMOS active pixel sensor that utilizes a retrograde well to reduce dark current generation. The retrograde well has a higher dopant concentration at the bottom than at the surface. This creates an electric field that directs minority charge carriers (which contribute to dark current) away from the charge collection region of the photodiode, thereby improving image quality.
• Potential Anticipation of Claims:
  • Claims 1, 21, 39, and 44: The '366 patent discloses a CMOS device (relevant to claims 1, 21, and 44) with a specific type of graded dopant region—a retrograde well. This well is designed to aid carrier movement away from an active region (the photodiode's charge collection node) toward the substrate, which aligns with the core concept of these claims. The '366 patent's well could be interpreted as anticipating the "graded dopant concentration to aid carrier movement" and the "well region adjacent to the... active region containing at least one graded dopant region" recited in these claims. Specifically for claim 44, the retrograde well acts as a "drift field" to move carriers.

2. U.S. Patent No. 6,696,314 B2

• Full Citation: Rhodes, Howard E. CMOS imager and method of formation. Micron Technology, Inc., assignee. 24 Feb. 2004.
• Filing Date: Aug. 30, 2001.
• Brief Description: A continuation of the '366 patent, this reference further details CMOS imager cells with retrograde wells to suppress dark current. It elaborates on forming a p-n-p structure where a p-type substrate contains an n-type retrograde well and a p-type photodiode region. The graded concentration of the n-well creates a potential barrier that repels electrons from the surface.
• Potential Anticipation of Claims:
  • Claims 1, 21, 39, 41, and 43: Similar to its parent patent, the '314 patent discloses a graded dopant region (the retrograde n-well) in a CMOS device to direct unwanted carriers. It specifies the use of both p-type (substrate, photodiode) and n-type (well) regions, making it relevant to claims specifying acceptor dopants (claim 41) and a combination of acceptor and donor dopants (claim 43). The fundamental principle of using a graded dopant profile to sweep carriers away from an active surface region is clearly taught.

3. U.S. Patent Application Publication No. 2003/0183856 A1

• Full Citation: Wieczorek, Karsten, et al. Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same. Infineon Technologies AG, assignee. 2 Oct. 2003.
• Filing Date: Mar. 28, 2002.
• Brief Description: This application describes a MOS transistor with a retrograde dopant profile directly in the channel region. The concentration of dopants is higher deeper in the substrate and lower near the surface. This is designed to improve the transistor's electrical characteristics, such as reducing short-channel effects and improving threshold voltage control, rather than sweeping minority carriers away from active regions for purposes like refresh time or dark current reduction.
• Potential Anticipation of Claims:
  • Claims 39, 41, 42, 43: While focused on the channel itself, the '856 application teaches a "graded dopant concentration" in an active region (the channel) of a semiconductor device. It could be argued that this anticipates the broader independent claims (39, 41, 42, 43) which do not strictly limit the purpose of the graded region to sweeping spurious carriers. The reference discloses grading both acceptor and donor dopants. However, it may not anticipate claims 1, 21, and 44, as its stated purpose is not to move carriers "towards an area of the substrate where there are no active regions" but rather to control transistor behavior within the channel.

4. U.S. Patent No. 6,831,292 B2

• Full Citation: Currie, Marc T., et al. Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same. AmberWave Systems Corporation, assignee. 14 Dec. 2004.
• Filing Date: Sep. 21, 2001.
• Brief Description: This patent focuses on creating high-performance transistors by using strained silicon layers. A key aspect of the invention is the creation of defined impurity (dopant) gradients within these strained layers. These gradients are used to form a built-in electric field that can enhance carrier mobility and thus transistor speed.
• Potential Anticipation of Claims:
  • Claims 39, 41, 42, 43: The '292 patent explicitly teaches "defined impurity gradients" (i.e., graded dopant concentrations) within active regions of a semiconductor device to aid carrier movement (enhance mobility). This directly maps to the language of the broader independent claims. It describes grading both n-type and p-type dopants. The motivation is to improve performance by accelerating majority carriers, which is one of the applications mentioned in the '222 patent's specification. This reference presents a strong case for anticipating the more general claims. It is less likely to anticipate claims 1, 21, and 44 because its focus is on accelerating carriers within the channel to improve transistor speed, not sweeping spurious minority carriers away from active regions into an inactive substrate area.

5. U.S. Patent No. 4,481,522 A

• Full Citation: Savoye, Eugene D., et al. CCD Imagers with substrates having drift field. RCA Corporation, assignee. 6 Nov. 1984.
• Filing Date: Mar. 24, 1982.
• Brief Description: This older patent describes a Charge-Coupled Device (CCD) imager built on a substrate that has a graded dopant concentration, such as a lightly doped epitaxial layer on a heavily doped substrate. This grading creates a "drift field" that accelerates charge carriers generated deep within the substrate towards the charge collection wells at the surface. This enhances the quantum efficiency of the sensor, particularly for longer-wavelength light.
• Potential Anticipation of Claims:
  • Claims 39, 42, and 44: The '522 patent clearly discloses a semiconductor device with a graded dopant concentration that creates an electric "drift field" to "aid the movement of carriers." While the purpose is to move carriers towards the active region (the collection well) rather than away from it, the fundamental mechanism is the same as described in several of the '222 patent's claims. Claim 44, which recites a "drift field to aid the movement of carriers," is particularly relevant. The direction of carrier movement is specified in claim 44 as "from the surface layer to an area of the substrate," which is the opposite of the '522 patent's teaching. Therefore, it would not anticipate claim 44, but it could be argued to anticipate the broader claim 39, which only requires aiding carrier movement from the active region to a substrate area without specifying direction relative to the surface.

Summary of Anticipation Analysis

While several cited references disclose the use of graded dopant profiles, their specific implementation and purpose are key to determining anticipation. The Rhodes patents ('366 and '314) appear to be the most relevant prior art, particularly against the claims directed at VLSI and CMOS devices (1, 21, 44), as they teach using graded wells to move unwanted minority carriers away from active surface regions into the substrate. The Currie ('292) and Wieczorek ('856) references also disclose graded dopants in active regions but focus on enhancing transistor channel performance rather than clearing spurious carriers, making them strong anticipatory references for the broader independent claims (39, 41, 42, 43). The Savoye ('522) patent teaches the core concept of a graded drift field but for the opposite purpose of collecting carriers at the surface, which weakens its case for direct anticipation of claims specifying carrier movement away from the surface.