Obviousness

An analysis of US patent 11,121,222 in light of the cited prior art suggests that its claims would have been obvious to a person of ordinary skill in the art (POSA) at the time of the invention, with a priority date of September 3, 2004.

Definition of a Person of Ordinary Skill in the Art (POSA)

A person of ordinary skill in the art (POSA) for this patent would be an individual with a Bachelor's or Master's degree in Electrical Engineering or a related field like Physics. This person would have several years of practical experience in the design and fabrication of semiconductor devices, including knowledge of device physics, ion implantation, epitaxial growth, and the common challenges in VLSI, CMOS, DRAM, and power device technologies circa 2004. A POSA would be familiar with the effects of dopant profiles on carrier transport and device performance.

Obviousness Analysis of Claims

The core inventive concept of the '222 patent is the use of graded dopant concentrations to create a built-in electric drift field. This field is engineered to actively sweep unwanted charge carriers away from sensitive areas (like the device surface, channel regions, or charge storage nodes) and into the substrate, thereby improving device performance. An examination of the prior art reveals that both the problem and the proposed solution were well-established concepts.

Combination 1: Rhodes (US 2003/0042511) and RCA (US 4,481,522)

This combination renders the VLSI-specific claims (e.g., Claims 1, 14, 15, 19, and 21) obvious.

• Rhodes (US 2003/0042511 A1): Published in March 2003, Rhodes teaches a CMOS imager and methods for its formation. Crucially, it addresses the problem of unwanted minority carriers (noise) degrading image quality. Rhodes discloses using a substrate with an epitaxial layer and forming p-wells and n-wells for the CMOS transistors. This reference establishes the foundational VLSI/CMOS structure with active regions and wells, as recited in the '222 patent's claims. Rhodes explicitly discusses the problem of collecting photogenerated carriers efficiently while rejecting unwanted carriers (crosstalk and dark current).

• RCA (US 4,481,522): Issued in 1984, this patent directly teaches the solution to the problem identified in Rhodes and addressed by the '222 patent. The RCA patent describes CCD imagers where a drift field is intentionally created in the substrate. The abstract states, "CCD Imagers with substrates having drift field," and the patent details how this field sweeps signal carriers towards the potential wells for collection while pushing unwanted, thermally generated carriers deep into the substrate where they can recombine. This is precisely the mechanism claimed in the '222 patent: aiding carrier movement from the surface towards an area of the substrate.

• Motivation to Combine: A POSA, when faced with the problem of managing stray minority carriers in a CMOS device as described by Rhodes, would have been motivated to look for solutions in related fields, such as CCD imagers, which faced similar challenges. The RCA patent provides a clear and direct teaching of using a drift field in the substrate for this exact purpose. The POSA would have found it obvious to apply the drift-field concept from RCA to the CMOS structure of Rhodes. Implementing a drift field via a graded dopant profile (as opposed to a uniform one) was a known technique, as the '222 patent itself acknowledges in the context of graded-base bipolar transistors. Therefore, creating graded doping in the wells and/or substrate of the Rhodes CMOS device to generate the carrier-sweeping drift field taught by RCA would have been a predictable and obvious design choice to improve performance by reducing noise and improving charge collection.

Combination 2: Sanken (US 6,737,722) and General Device Knowledge

This combination renders the broader device claims (e.g., Claims 39, 41, 42, 43) obvious.

• Sanken (US 6,737,722 B2): Issued in May 2004, this patent discloses a lateral transistor with a "graded base region." The patent explains that this graded dopant concentration creates an accelerating electric field for minority carriers in the base, which shortens the carrier transit time and improves the high-frequency characteristics of the transistor. This directly teaches the core element of Claim 39: an active region with a graded dopant concentration to aid carrier movement.

• Motivation to Apply: The Sanken patent demonstrates the known benefits of applying a graded dopant profile to an active region of a transistor to improve performance. For a POSA, it would have been an obvious extension to apply this established technique to other semiconductor devices and active regions beyond the specific lateral transistor shown. The principle that a dopant gradient creates a field that aids carrier movement is fundamental device physics. Applying this principle to different device structures to achieve predictable improvements in carrier transport is a standard engineering approach. The dependent claims specifying the dopant type (acceptor for p-type, donor for n-type, or both) simply cover the fundamental and necessary design choices for creating any semiconductor region and do not add a non-obvious element.

Combination 3: Micron (US 6,310,366) and RCA (US 4,481,522)

This combination renders Claim 44, which is specific to a CMOS device with a drift layer and a graded well, obvious.

• Micron (US 6,310,366 B1): Issued in 2001, this patent describes a "Retrograde well structure for a CMOS imager." It directly addresses the problem of dark current and pixel crosstalk by using a non-uniform dopant profile (a retrograde well) to "provide an electric field which directs photogenerated electrons toward the photodiode and away from the channel stop regions." This teaches the use of a specially profiled well in a CMOS device to create a field that directs carriers.

• RCA (US 4,481,522): As described previously, RCA teaches creating a "drift field" in the bulk of the substrate (what Claim 44 calls a "single drift layer") to create a "unidirectional electric drift field" that moves carriers from the surface layer towards the substrate.

• Motivation to Combine: The POSA is presented with two complementary techniques for managing unwanted carriers in CMOS-type imagers. The Micron patent teaches engineering the well region with a non-uniform profile to create a localized field, while the RCA patent teaches engineering the entire substrate to create a global, unidirectional field. A POSA would have found it obvious to combine these two techniques into a single device to achieve superior carrier management. This would involve implementing the substrate-wide drift field from RCA along with the profiled well structure from Micron. The combination directly results in the device of Claim 44: a CMOS device with a drift layer (from RCA) and a graded well region (from Micron), both creating electric fields to aid the movement of carriers away from the surface.

Conclusion

The claims of US patent 11,121,222 appear to be obvious under 35 U.S.C. § 103. The core concept—using a graded dopant profile to create a drift field for sweeping away unwanted minority carriers—was a known principle. Prior art references from the relevant timeframe, such as RCA (US 4,481,522), Sanken (US 6,737,722), Rhodes (US 2003/0042511), and Micron (US 6,310,366), teach the necessary components: the problem of spurious carriers in VLSI devices, the standard CMOS structures, and the use of graded/non-uniform doping in both substrate and well regions to create electric fields for carrier management. A person of ordinary skill in the art would have been motivated to combine these known elements to achieve the predictable performance improvements described in the '222 patent.