Derivative works — US Patent 11121222

Defensive Disclosure and Prior Art Derivations for U.S. Patent 11,121,222

Publication Date: May 10, 2026
Subject: Derivative Embodiments of Semiconductor Devices with Graded Dopant Regions
Reference Patent: U.S. Patent 11,121,222 B2 ("the '222 patent")
Core Technology: The use of a non-uniform, or "graded," dopant concentration profile within a semiconductor substrate or well to create a static, built-in electric field. This field is engineered to accelerate the movement of undesirable charge carriers (e.g., minority carriers generated by noise or radiation) away from sensitive active device regions on the surface and toward an inactive region of the substrate, thereby improving device performance, reliability, and noise immunity.

This document discloses a series of derivative works, alternative embodiments, and novel applications of the core technology described in the '222 patent. The purpose of this disclosure is to establish prior art for subsequent inventions that may be considered obvious extensions or variations of the foundational concept.

Axis 1: Material & Component Substitution

Derivative 1.1: Graded Doping in Wide-Bandgap Compound Semiconductors

Enabling Description: The principles of the '222 patent are applied to Gallium Nitride (GaN) or Silicon Carbide (SiC) High-Electron-Mobility Transistors (HEMTs). A graded p-type region is formed below the 2D-electron gas (2DEG) channel using selective ion implantation of Magnesium (Mg) in GaN or Aluminum (Al) in SiC. The grading is achieved through a sequence of multi-energy implants followed by a controlled thermal activation anneal. This graded field actively extracts charge carriers trapped in the GaN buffer or SiC substrate, reducing current collapse and improving dynamic on-resistance (Ron), which are critical performance limiters in high-power switching applications. The gradient is established from a low concentration (e.g., 1x1016 cm-3) near the channel to a high concentration (e.g., 5x1017 cm-3) at the substrate interface.

Mermaid Diagram:

classDiagram
    direction LR
    class Substrate {
        +Material: SiC or Sapphire
    }
    class BufferLayer {
        +Material: GaN
        +Function: Isolate channel
    }
    class GradedP_Region {
        +Dopant: Magnesium (Mg)
        +Concentration: 1e16 to 5e17 cm^-3
        +Function: Create E-field to extract trapped charge
    }
    class AlGaN_Barrier {
        +Function: Induce 2DEG
    }
    class Channel_2DEG {
        +Location: AlGaN/GaN Interface
        +Function: Primary conduction path
    }
    class Gate {
        +Type: Schottky or MOS
    }
    class Source_Drain {
        +Type: Ohmic contacts
    }

    Substrate --|> BufferLayer : Supports
    BufferLayer --|> GradedP_Region : Contains
    GradedP_Region --|> AlGaN_Barrier : Below
    AlGaN_Barrier --|> Channel_2DEG : Creates
    Gate -- Channel_2DEG : Modulates
    Source_Drain -- Channel_2DEG : Accesses

Derivative 1.2: Electrically Induced Graded Fields in Ferroelectric Stacks

Enabling Description: This embodiment replaces the fixed, implanted dopant gradient with a dynamically controllable electric field generated by a ferroelectric layer, such as Hafnium Zirconium Oxide (HZO), integrated below the device's channel region. By applying a bias voltage to a buried control gate, the polarization of the HZO layer can be partially and non-volatilely set, creating a remnant polarization gradient. This gradient induces a corresponding electric field in the underlying silicon substrate, which functions to sweep minority carriers away. The strength and profile of this "clearing field" can be programmed post-fabrication, allowing for performance tuning based on the application's noise environment.

Mermaid Diagram:

flowchart TD
    subgraph Device_Stack
        A[Source/Drain Contacts] --> B{Active Channel Region};
        C[Top Gate] --> B;
        B --> D[Silicon Substrate];
        D --> E[Ferroelectric Layer (HZO)];
        E --> F[Buried Control Gate];
    end

    subgraph Control
        G(Voltage Control Unit) -- Program/Erase Pulses --> F;
    end

    subgraph Physics
        F -- Bias Voltage --> E;
        E -- Creates Polarization Gradient --> D;
        D -- Induces E-Field --> B;
        B -- Sweeps Minority Carriers --> D;
    end

    style E fill:#f9f,stroke:#333,stroke-width:2px

Axis 2: Operational Parameter Expansion

Derivative 2.1: Cryogenic Graded-Well Structures for Quantum Processors

Enabling Description: The invention is implemented in control circuitry for silicon-based quantum bits (qubits) operating at milli-Kelvin (mK) temperatures. Spurious charge carriers, generated by environmental radiation or control line noise, can cause qubit decoherence. A graded dopant well is formed around the qubit array using low-energy arsenic and phosphorus implantation. The gradient profile is specifically optimized using cryogenic TCAD simulations to maximize the clearing field strength while minimizing dopant freeze-out effects. The resulting structure creates a potential gradient that directs stray electrons away from the quantum dot locations, increasing qubit coherence times (T2) by an order of magnitude or more compared to uniformly doped wells.

Mermaid Diagram:

sequenceDiagram
    participant Env as Environment (Noise/Radiation)
    participant Substrate as Silicon Substrate
    participant GWell as Graded Well
    participant Qubit as Quantum Dot Qubit

    Env->>Substrate: Generates spurious e-h pair
    Substrate->>GWell: Electron drifts into well
    GWell->>GWell: E-Field accelerates electron away from surface
    Note right of GWell: Field optimized for T < 1K
    GWell->>Substrate: Electron collected at deep substrate contact
    Qubit->>Qubit: Coherence state (T2) maintained

Derivative 2.2: High-Pressure Graded-Channel Piezoresistive Sensors

Enabling Description: This disclosure describes a MEMS pressure sensor where the sensing element is a silicon nanowire with a graded dopant profile along its length. The device operates at pressures exceeding 1 GPa. The graded doping (e.g., boron, from 1018 cm-3 to 1020 cm-3) serves two purposes. First, it creates a built-in electric field that improves carrier velocity and signal response time. Second, under extreme pressure, the piezoresistive coefficient of silicon becomes highly dependent on carrier concentration. The graded profile linearizes the sensor's response across a wide pressure range, compensating for non-linear stress-mobility effects that would otherwise saturate a uniformly doped device.

Mermaid Diagram:

graph LR
    subgraph Sensor
        A[Contact 1] <--> B(Si Nanowire);
        B <--> C[Contact 2];
    end
    subgraph Doping_Profile
        direction BT
        D1(10^18 cm^-3) --> D2(10^19 cm^-3) --> D3(10^20 cm^-3);
    end
    subgraph Physics
        P(High Pressure ~1 GPa) -- Induces Stress --> B;
        B -- Changes Resistivity --> S(Electrical Signal Out);
        G(Graded Doping) -- Linearizes Response --> B;
    end
    B -- Contains --> G;
    style B fill:#bbf,stroke:#333,stroke-width:2px

Axis 3: Cross-Domain Application

Derivative 3.1: Aerospace - Single Event Upset (SEU) Hardened FPGA

Enabling Description: The invention is applied to Field-Programmable Gate Arrays (FPGAs) for use in high-radiation environments like space. A deep, retro-graded subterranean well is formed beneath the entire FPGA fabric using a high-energy (MeV) Boron implant. The doping concentration is highest at the bottom of the well and decreases towards the surface. When a high-energy particle strikes the silicon, it generates a dense cloud of electron-hole pairs. The strong vertical electric field within the graded well rapidly separates these pairs, shunting the charge deep into the substrate before it can diffuse laterally into the configuration memory cells (SRAM) or logic blocks, thus preventing a bit-flip (SEU).

Mermaid Diagram:

flowchart TD
    A[High-Energy Particle Strike] --> B{Charge Cloud Generation (e-h pairs)};
    subgraph FPGA_Fabric
        C[Configuration SRAM Cell]
        D[Logic Block (LUT)]
    end
    subgraph Substructure
        E[Active Device Layer]
        F[Deep Graded Well]
        G[P+ Substrate Contact]
    end
    B -- Charge Spreads --> F;
    F -- E-Field Shunts Charge Vertically --> G;
    B -.-> |Charge Path Blocked| C;
    B -.-> |Charge Path Blocked| D;
    style F fill:#cde,stroke:#333,stroke-width:4px

Derivative 3.2: AgTech - Soil Nutrient Ion-Selective FET (ISFET) Sensor Array

Enabling Description: A multi-channel sensor for precision agriculture applications. An array of ISFETs is fabricated, where each gate dielectric is functionalized to be sensitive to a specific soil nutrient (e.g., nitrate, potassium, phosphate). The underlying substrate contains a graded well structure as per the '222 patent. In the electrically noisy environment of the soil, stray ionic currents can inject minority carriers into the substrate, causing drift in the ISFET threshold voltage and inaccurate readings. The graded well's built-in field actively clears these injected carriers, stabilizing the sensor baseline and dramatically improving the signal-to-noise ratio, allowing for ppb (parts-per-billion) level detection of nutrients directly in the field.

Mermaid Diagram:

    graph BT
    subgraph In_Soil
        A(Soil Environment) -- Nutrients & Noise --> B{ISFET Sensor Array};
    end
    subgraph Chip_Cross_Section
        C[Functionalized Gate Dielectric] -- Modulates --> D[ISFET Channel];
        D -- Is Above --> E[Graded Well];
        E -- Sweeps Injected Carriers --> F[Substrate];
    end
    B -- Comprises --> C;
    B -- Comprises --> D;
    B -- Comprises --> E;
    B -- Comprises --> F;
    E -- Stabilizes --> D;
    D -- Produces --> G(Sensor Signal);

Axis 4: Integration with Emerging Tech

Derivative 4.1: AI-Optimized Adaptive Clearing Field for Image Sensors

Enabling Description: A CMOS image sensor incorporates the graded well structure of the '222 patent. The well bias is controlled by an on-chip AI accelerator. An embedded neural network analyzes the image histogram and scene content in real-time. For low-light scenes requiring long exposures, the AI increases the reverse bias on the well, strengthening the clearing field to aggressively sweep away dark current carriers and reduce noise. For bright, fast-moving scenes, the AI reduces the well bias to save power, as dark current is less significant. This creates a closed-loop system that dynamically optimizes the trade-off between image quality and power consumption on a frame-by-frame basis.

Mermaid Diagram:

sequenceDiagram
    participant Sensor as Image Sensor
    participant AI as On-Chip NN Accelerator
    participant VCtrl as Voltage Controller
    participant GWell as Graded Well

    loop Frame-by-Frame Analysis
        Sensor->>AI: Send image data/histogram
        AI->>AI: Analyze scene (e.g., low-light vs. bright)
        AI->>VCtrl: Calculate optimal bias voltage
        VCtrl->>GWell: Apply new bias
        GWell->>Sensor: Adjust clearing field strength
    end

Derivative 4.2: Blockchain-Verified Physically Unclonable Function (PUF)

Enabling Description: The inherent, uncontrollable process variations in ion implantation mean that the exact dopant profile of a graded region is unique to each individual chip. This uniqueness is harnessed to create a PUF for cryptographic authentication. A challenge-response mechanism is implemented where specific voltages are applied to contacts within the graded region, and the resulting current flow (a complex function of the unique dopant profile) is measured. This response is digitized to form a unique device ID or cryptographic key. During manufacturing, this key is registered on a private blockchain, creating an immutable record that ties the physical device to its digital identity, preventing counterfeiting and ensuring supply chain integrity.

Mermaid Diagram:

flowchart LR
    subgraph Device
        A[Challenge Generator] -- Applies Voltages --> B(Graded Dopant Region);
        B -- Produces Unique IV Curve --> C[Response Measurement];
        C -- Digitization --> D{Device-Unique Key};
    end
    subgraph Secure_System
        D -- Stored During Mfg --> E[Blockchain Ledger];
        F[Authenticator] -- Sends Challenge --> A;
        D -- Compared With --> E;
        E -- Verifies --> F;
    end
    style B fill:#ffc,stroke:#333,stroke-width:2px

Axis 5: The "Inverse" or Failure Mode

Derivative 5.1: Fail-Safe Mode via Field Reversal in Automotive SoCs

Enabling Description: A system-on-chip (SoC) for an automotive safety-critical application (e.g., braking control) uses a graded n-well in a p-substrate. Under normal operation, the well is reverse-biased to sweep away minority carriers (electrons). The system includes a charge-pump and monitoring circuit. If an over-voltage event or radiation-induced damage is detected that could compromise the integrity of the clearing field, the monitoring circuit triggers a fail-safe state. In this state, the charge pump is reconfigured to forward-bias the n-well/p-substrate junction. This intentionally floods the active area with carriers, effectively clamping logic levels to a known, safe state (e.g., logic low) and preventing unpredictable behavior, allowing the system to enter a controlled shutdown.

Mermaid Diagram:

stateDiagram-v2
    [*] --> Normal_Operation
    Normal_Operation: Well is reverse-biased.
    Normal_Operation: Clearing field is active.
    Normal_Operation --> Fail_Safe : Fault Detected (Overvoltage)
    Fail_Safe: Charge pump reverses bias.
    Fail_Safe: Well is forward-biased.
    Fail_Safe: Active area is flooded with carriers.
    Fail_Safe: Logic state is clamped.
    Fail_Safe --> [*] : System Reset

Combination Prior Art Scenarios with Open-Source Standards

RISC-V Processor Core Hardening: The graded dopant well technology of the '222 patent is integrated into the physical design (GDSII layout) of an open-source RISC-V processor core, such as the "Rocket" or "BOOM" core. The graded well is selectively implemented under critical components identified through fault-injection analysis, including the L1 cache SRAM, the instruction decode pipeline registers, and the floating-point unit. The open-source nature of the core allows for tight co-design, where the well geometry and gradient profile are optimized for the specific layout of these sensitive blocks to maximize protection against soft errors, with the final hardened layout being released under an open-source hardware license like CERN-OHL.
CXL I/O Substrate Noise Isolation: In a chiplet-based system using the open-source Compute Express Link (CXL) protocol for high-speed interconnects, the '222 patent's graded drift region is implemented in the I/O chiplet's substrate. The high-speed SerDes transceivers required for CXL are highly sensitive to substrate noise injected by the digital logic in adjacent chiplets. A deep, graded p-well is formed under the CXL PHY, creating a vertical field that collects and removes injected minority carriers before they can interfere with the sensitive analog front-end of the SerDes receivers. This improves the bit-error rate (BER) and allows the CXL interface to run at its maximum data rate, a design publicly disclosed in a whitepaper submitted to the CXL Consortium.
USB Power Delivery (USB-PD) Controller Robustness: The graded dopant region is applied to a high-voltage power MOSFET within a USB-PD controller IC that adheres to the open USB-PD 3.1 specification. During high-power (240W) charging operations, significant substrate carrier injection can occur, potentially triggering parasitic bipolar transistor latch-up. A graded n-drift region, as described in FIG. 4 of the '222 patent, is implemented in the DMOS transistor. This design creates a clearing field that enhances the removal of minority carriers (holes), significantly increasing the device's latch-up immunity. The design methodology and TCAD simulation results are published as an application note targeting designers using the open USB-PD standard.