US 11012252

US Patent 11012252, titled "Active ethernet cable," was issued to Credo Technology Group Ltd on May 18, 2021, from an application filed on August 13, 2019. The inventors are Yattung LAM and Baohua Chen.

Abstract:
The patent discloses architectures and communication methods for mass-manufactured active Ethernet cables designed for robust performance at high per-lane PAM4 symbol rates (up to 56 GBd and beyond). The cable includes electrical conductors connecting first and second connectors. Each connector is adapted to fit into an Ethernet port of a host device to receive an electrical input signal (inbound data stream) and provide an electrical output signal (outbound data stream). Each connector houses a transceiver that performs clock and data recovery (CDR) on the inbound electrical input signal to extract and re-modulate it into an electrical transit signal for transmission over the cable's conductors.

Plain-Language Overview of Independent Claims:

• Independent Claim 1 (Active Ethernet cable): This claim describes an active Ethernet cable with two connectors, each containing a transceiver. These connectors are designed to plug into standard Ethernet ports. Each transceiver takes an incoming electrical signal from a host device, performs clock and data recovery, and then re-modulates this data for transmission through the cable (as a "transit data stream"). Additionally, each transceiver performs clock and data recovery on the "transit data stream" received from the other end of the cable and re-modulates it into an "outbound data stream" to be sent to the host device. A key feature is that the transceivers use fixed, pre-determined (cable-independent) equalization settings for processing the electrical input signals from the host device and for generating the electrical output signals to the host device.

• Independent Claim 6 (Communication method): This claim outlines a communication method performed within such an active Ethernet cable. It involves a first connector receiving an inbound data stream from a first host device, performing clock and data recovery, and re-modulating it for transit within the cable. Similarly, a second connector receives a second inbound data stream from a second host device, performs clock and data recovery, and re-modulates it for transit. The method further specifies that the second transceiver performs clock and data recovery on the first transit data stream to extract it and re-modulates it as an outbound data stream for the second host device. Conversely, the first transceiver performs clock and data recovery on the second transit data stream and re-modulates it as an outbound data stream for the first host device. Similar to Claim 1, the re-modulation of transit data streams into outbound data streams and the initial clock and data recovery on the inbound electrical input signals use fixed, cable-independent equalization parameters.

• Independent Claim 11 (Cable manufacturing method): This claim describes a method for manufacturing the active Ethernet cable. It includes connecting conductor pairs to first and second transceivers to enable the transport of electrical transit signals between them. The method then involves packaging each transceiver into a connector. These connectors are designed to interface with host devices, allowing the transceivers to receive inbound electrical signals from host devices and provide outbound electrical signals to them. The transceivers are specifically configured to perform clock and data recovery on the inbound signals, re-modulating them into transit data streams, and also to perform clock and data recovery on transit signals from the cable, re-modulating them into outbound data streams. Critically, these transceivers are configured to use fixed, cable-independent equalization parameters for clock and data recovery on host-facing electrical input signals and for generating host-facing electrical output signals.

Litigation Information:
While no CAFC 2026 dockets were found specifically, the patent family for US11012252B2 is currently involved in litigation, including multiple PTAB cases and US district court cases filed in 2025.

Known litigation involving US patent 11012252 includes the following cases:

PTAB Cases:

• Case Number: IPR2025-00834

  • Plaintiff(s): Petitioner: Amphenol Corporation
  • Defendant(s): Credo Technology Group Ltd (as patent owner)
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Filing Date: The effective date for this IPR is April 10, 2025.
  • Outcome/Current Status: Settlement

• Case Number: IPR2025-01386

  • Plaintiff(s): Petitioner: Volex PLC
  • Defendant(s): Credo Technology Group Ltd (as patent owner)
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Filing Date: The effective date for this IPR is August 7, 2025.
  • Outcome/Current Status: Settlement

• Case Number: IPR2025-01219

  • Plaintiff(s): Petitioner: Marvell Semiconductor, Inc.
  • Defendant(s): Credo Technology Group Ltd (as patent owner)
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Filing Date: The effective date for this IPR is August 7, 2025.
  • Outcome/Current Status: Pending - Instituted

US District Court Cases:

• Jurisdiction: Texas Eastern District Court

  • Case Number: 2:25-cv-00298
  • Plaintiff(s): Not specified in the provided data.
  • Defendant(s): Not specified in the provided data.
  • Filing Date: Not explicitly stated, but the case was filed in 2025.
  • Outcome/Current Status: Litigation

• Jurisdiction: Delaware District Court

  • Case Number: 1:25-cv-00316
  • Plaintiff(s): Not specified in the provided data.
  • Defendant(s): Not specified in the provided data.
  • Filing Date: Not explicitly stated, but the case was filed in 2025.
  • Outcome/Current Status: Litigation

• Jurisdiction: International Trade Commission

  • Case Number: 337-TA-1446
  • Plaintiff(s): Not specified in the provided data.
  • Defendant(s): Not specified in the provided data.
  • Filing Date: Not explicitly stated.
  • Outcome/Current Status: Litigation

• Jurisdiction: Texas Eastern District Court

  • Case Number: 2:25-cv-00297
  • Plaintiff(s): Not specified in the provided data.
  • Defendant(s): Not specified in the provided data.
  • Filing Date: Not explicitly stated, but the case was filed in 2025.
  • Outcome/Current Status: Litigation

• Jurisdiction: Texas Eastern District Court

  • Case Number: 2:25-cv-00296
  • Plaintiff(s): Not specified in the provided data.
  • Defendant(s): Not specified in the provided data.
  • Filing Date: Not explicitly stated, but the case was filed in 2025.
  • Outcome/Current Status: Litigation

Additionally, it is noted that the "First worldwide family litigation filed" is linked to the Darts-ip platform for family ID=72236814, which includes US11012252 (B2). Specific details for this global litigation were not provided in the readily available snippets.

Proceedings overview

Two AIA trial proceedings have been filed against US patent 11012252. One proceeding is currently in the "Trial Instituted" status, while the other was "Terminated-Settled" prior to institution. This indicates an active challenge to the patent's validity, but no claims have been formally invalidated by the PTAB to date. The defensive posture for a defendant is mixed: some claims are under active PTAB review, potentially leading to future invalidation, while other challenges have been resolved by settlement without a merits decision.

IPR2025-01219 — Marvell Semiconductor, Inc. v. Credo Technology Group Ltd.

• Type: Inter Partes Review
• Filed: 2025-08-07
• Status: Trial Instituted (The PTAB has decided to initiate a trial to review the patentability of the challenged claims. The last modification date was 2026-05-15.)
• Judge panel: The specific judge panel information is not available from the provided search results.
• Petition grounds: Marvell Semiconductor, Inc. challenged claims 1-4, 6-9, and 11-14 as obvious under 35 U.S.C. § 103, relying on the combination of U.S. Patent 8,516,238 (Cornelius) and a 2015 Intel whitepaper titled “High-Speed Serial Bus Repeater Primer” (Samaan). An additional ground of obviousness under § 103 was asserted for claims 1-14 over U.S. Patent 9,882,706 (Lugthart) in view of U.S. Patent 7,445,389 (Aronson). Furthermore, claims 5 and 10 were challenged as obvious over Cornelius and Samaan, further in view of Lugthart, specifically addressing a "per-lane symbol rate in excess of 50 GBd" limitation.
• Institution decision: Instituted on 2026-02-03. The PTAB initiated a trial after finding a reasonable likelihood that the petitioner would prevail on at least one claim challenged.
• Final Written Decision (if issued): A Final Written Decision has not yet been issued, as the proceeding is in the "Trial Instituted" phase.
• Settlement / termination: Not settled; the trial has been instituted.
• Appeal: Not applicable at this stage.
• Defensive value: This proceeding signifies a substantial challenge to the patentability of claims 1-14. If Marvell Semiconductor, Inc. prevails, these claims could be canceled, significantly weakening the patent. For a defendant, this creates an opportunity to potentially leverage a future invalidation decision.

IPR2025-01386 — Volex plc v. Credo Technology Group Ltd.

• Type: Inter Partes Review
• Filed: 2025-08-07
• Status: Terminated-Settled (The proceeding was closed due to a settlement agreement between the parties. The last modification date was 2025-09-15, and the termination date was 2025-09-09.)
• Judge panel: The specific judge panel information is not available, as the case was terminated prior to institution of trial.
• Petition grounds: While a petition was filed, the proceeding was terminated before the PTAB made an institution decision. Therefore, the specific claims challenged and statutory bases were not formally adjudicated, and detailed grounds are not available from the search results for the petition itself.
• Institution decision: Denied (implicitly, as it was terminated prior to institution of trial).
• Final Written Decision (if issued): No Final Written Decision was issued due to the settlement and termination of the proceeding prior to institution.
• Settlement / termination: The proceeding was terminated-settled on 2025-09-09. The decision document indicates that a joint request to treat the settlement agreement as business confidential information was granted.
• Appeal: Not applicable, as the proceeding was settled and terminated prior to institution.
• Defensive value: The settlement of this IPR means that the challenged claims were not formally invalidated by the PTAB. However, the confidential nature of the settlement terms prevents an understanding of any agreement made regarding the patent's validity or enforcement. For a defendant, this means these claims were not "hardened" by a PTAB decision confirming their patentability, but also not canceled.

Strategic summary

Currently, no claims of US patent 11012252 have been formally CANCELED by a Final Written Decision from the PTAB. Claims 1-14 of the patent are presently under review in IPR2025-01219, with trial having been instituted. This means their patentability is actively being challenged based on obviousness grounds. The other proceeding, IPR2025-01386, was Terminated-Settled, meaning the claims challenged in that petition were not adjudicated by the PTAB on the merits and thus are neither sustained nor canceled by a PTAB ruling.

The estoppel landscape is evolving. For IPR2025-01386, Volex plc and its privies would be estopped under 35 U.S.C. § 315(e)(2) from asserting in future district court or ITC actions any invalidity ground they raised or reasonably could have raised in their petition, specific to the claims challenged in that IPR, should the PTAB have issued a final written decision. However, since it settled prior to institution, the full scope of estoppel may be limited to grounds actually raised in the petition if there were any collateral estoppel effects from the settlement agreement itself, which is confidential. For IPR2025-01219, if a Final Written Decision issues, Marvell Semiconductor, Inc. and its privies will be estopped from raising any ground they raised or reasonably could have raised during the IPR with respect to the claims addressed in the FWD. Other potential defendants would still be able to pursue invalidity arguments against claims 1-14 using other prior art or even the same prior art if they are not in privity with Marvell, particularly if the PTAB does not cancel all challenged claims.

A pattern signal is that Credo Technology Group Ltd. is facing multiple IPRs on this patent, indicating that its validity is being actively scrutinized by competitors. The fact that Marvell Semiconductor, Inc. has several IPRs against Credo Technology Group, as shown in the search results, suggests a broader dispute.

Recommended next steps

For IPR2025-01219, which was instituted on 2026-02-03, the PTAB has a statutory deadline of one year from institution to issue a Final Written Decision (FWD). Therefore, the FWD for IPR2025-01219 is anticipated by approximately 2027-02-03. Parties involved or interested in this patent should closely monitor the docket for this proceeding for further updates, including scheduling orders, oral hearing dates, and the eventual issuance of the FWD. The PTAB's decisions are publicly available on the USPTO PTAB Decisions portal.

Inventors

• Yattung LAM (Credo Technology Group Ltd)
• Baohua Chen (Credo Technology Group Ltd)

Both inventors were employed by Credo Technology Group Ltd, the original assignee, at the time of the patent application filing (or the priority date, 2019-03-01, as indicated by the assignment effective date).

Original assignee

The original assignee on the issued patent US11012252 is Credo Technology Group Ltd. Credo Technology Group Ltd is a fabless semiconductor company that provides high-speed connectivity solutions, including active electrical cables (AECs), which embody the claims of this patent. The company is currently operating and publicly traded (NASDAQ: CRDO).

Assignment timeline

A search on the USPTO Patent Assignment Search database (https://assignmentcenter.uspto.gov/) for patent number 11012252 returned no matching records. This indicates that, beyond the initial assignment from the inventors to Credo Technology Group Ltd (which is implicit in the patent's original assignee information and noted in Google Patents legal events as recorded on 2019-08-13, reel 050042/0823, with an effective date of 2019-02-27), no subsequent assignments of this patent have been formally recorded with the USPTO.

Timeline diagram

timeline
    title Ownership of US 11012252
    2019 : Filed by Credo Technology Group Ltd
    2021 : Issued to Credo Technology Group Ltd

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. There are no recorded transfers of the patent from the original assignee to any other entity.
2. Known asserter in the chain — Not present. The patent remains with the original operating company, Credo Technology Group Ltd.
3. Repeat correspondent across the chain — Not present. No assignment chain exists beyond the initial transfer from inventors to the original assignee.
4. Cascading transfers — Not present. No multiple consecutive assignments are recorded.
5. Pre-litigation transfer — Not present. The patent has not been transferred from its original assignee. Litigation has been filed against Credo's family of patents, but not by a new assignee of this specific patent.
6. Bankruptcy fire-sale — Not present. Credo Technology Group Ltd is an active, operating company.
7. Privateering — Unclear. While Credo Technology Group Ltd is an operating company, the existence of multiple PTAB and district court cases in 2025 (as noted in the Patent Summary and Google Patents legal events) indicates assertion activity. Without further details on the nature of these specific lawsuits (e.g., against competitors or non-competitors), it is unclear if this patent is involved in "privateering" actions. However, the patent itself has not been transferred to a third party.
8. Defensive aggregator (anti-NPE) — Not present. The patent is currently owned by Credo Technology Group Ltd and has not been acquired by a defensive aggregator.

Verdict

Operating-company assertion. The patent US11012252 remains assigned to its original operating company, Credo Technology Group Ltd, and no subsequent assignments are recorded with the USPTO Assignment Center (search results: "No matching records were found for the query." on 2026-05-21). The litigation noted in the patent summary suggests assertion activity, which, given the continued ownership by an operating company, points to operating-company assertion.

USPTO Assignment Center search: https://assignmentcenter.uspto.gov/ (search for patent number 11012252).

The USPTO website provides tools for searching patents, including Patent Public Search which allows searching by patent number.

The most relevant prior art for US Patent 11012252, "Active Ethernet Cable," as identified in its patent citations, is analyzed below. The analysis focuses on how these references potentially anticipate claims under 35 U.S.C. § 102, which generally relates to novelty and states that an invention cannot be patented if it was known or used by others before the applicant invented it, or if it was patented or described in a printed publication more than one year before the application date.

Here are the cited patents and their potential relevance:

1. US7049937B1

• Full Citation: US7049937B1, "Self-identifying cable for interconnecting electronic devices," granted May 23, 2006.
• Publication/Filing Date: June 11, 2002 (priority date).
• Brief Description: This patent describes a self-identifying cable that can communicate its characteristics (e.g., cable type, length) to connected devices. It focuses on the cable's ability to identify itself and potentially configure the devices for optimal performance.
• Potential Anticipation: This patent might anticipate aspects of US11012252B2 related to an "active" cable that provides information or performs functions beyond simple electrical conduction. Specifically, it could relate to the concept of a cable influencing or adapting communication based on its inherent properties, which in US11012252B2 involves equalization parameters. However, US7049937B1 doesn't explicitly mention transceivers performing clock and data recovery and re-modulation within the cable for signal regeneration, which is central to US11012252B2's independent claims.

2. US20070237464A1

• Full Citation: US20070237464A1, "Electrical-optical active optical cable," published October 11, 2007.
• Publication/Filing Date: April 10, 2006 (priority date).
• Brief Description: This publication describes an active optical cable that converts electrical signals to optical signals and vice-versa, allowing for longer transmission distances than passive electrical cables.
• Potential Anticipation: This reference introduces the concept of an "active" cable with integrated electronics to extend signal reach. While it focuses on optical conversion, the general idea of an active cable with integrated transceivers for signal regeneration could be seen as broadly anticipatory to the "active" nature of the Ethernet cable in US11012252B2. However, the specific electrical signal processing, clock and data recovery, and re-modulation of electrical signals for transit within an Ethernet cable, as described in US11012252B2's independent claims, are not directly addressed.

3. US7401985B2

• Full Citation: US7401985B2, "Electrical-optical active optical cable," granted July 22, 2008.
• Publication/Filing Date: April 10, 2006 (priority date).
• Brief Description: This patent is a granted version of US20070237464A1, describing an active optical cable for converting electrical signals to optical signals and back.
• Potential Anticipation: As a granted version of US20070237464A1, its potential anticipation is similar. It broadens the concept of an "active" cable but doesn't specifically detail the electrical domain signal conditioning (CDR and re-modulation with fixed equalization for host-facing links, and cable-dependent for internal links) that distinguishes US11012252B2.

4. US20130343400A1

• Full Citation: US20130343400A1, "Link training and training frame for 100gbps ethernet," published December 26, 2013.
• Publication/Filing Date: June 22, 2012 (priority date).
• Brief Description: This publication describes methods for link training and the use of training frames in high-speed Ethernet, particularly for 100 Gbps. Link training involves adapting equalization filters to combat channel non-idealities.
• Potential Anticipation: This reference is highly relevant as it describes link training and adaptive equalization within an Ethernet context. While US11012252B2 emphasizes fixed, cable-independent equalization for host interfaces and potentially cable-dependent or adaptive equalization for internal cable links (claims 2, 3, 12-14), US20130343400A1 focuses on adaptive equalization generally for high-speed Ethernet. The concept of training phases and equalization (as discussed in the detailed description of US11012252B2, referring to Figures 4 and 5) could be anticipated in a broader sense. However, the specific architecture of transceivers within the cable performing CDR and re-modulation on both inbound and transit data streams, and the distinct application of fixed vs. cable-dependent equalization parameters for different parts of the communication path as claimed in US11012252B2, may differentiate it.

5. US9230416B2

• Full Citation: US9230416B2, "Communication devices including a sensor configured to detect physical input," granted January 5, 2016.
• Publication/Filing Date: August 6, 2012 (priority date).
• Brief Description: This patent describes communication devices with sensors to detect physical input, such as cable insertion, and react accordingly. It broadly covers how devices interact with physical connections.
• Potential Anticipation: This patent might be relevant to the general interaction between a host device and a cable, particularly if the "active" nature of US11012252B2's cable involves detecting its presence or capabilities. However, it does not appear to directly anticipate the core claims of US11012252B2 regarding internal transceivers performing CDR and re-modulation for signal integrity within the cable.

6. US20140086264A1

• Full Citation: US20140086264A1, "Method for rapid pma alignment in 100gbase-kp4," published March 27, 2014.
• Publication/Filing Date: September 24, 2012 (priority date).
• Brief Description: This publication details methods for rapid Physical Media Attachment (PMA) alignment in high-speed Ethernet (100GBASE-KP4), which is part of the physical layer.
• Potential Anticipation: This reference relates to the physical layer operations of high-speed Ethernet, including PMA sublayer functions (which the transceivers in US11012252B2 may implement, as stated in its description). The techniques for rapid alignment could be relevant to the efficient operation of the transceivers. Similar to US20130343400A1, it provides context for high-speed Ethernet physical layer challenges and solutions but may not directly anticipate the specific active cable architecture with dual CDR/re-modulation stages and distinct equalization parameter strategies.

7. US20140146833A1

• Full Citation: US20140146833A1, "Pma-size training frame for 100gbase-kp4," published May 29, 2014.
• Publication/Filing Date: November 29, 2012 (priority date).
• Brief Description: This publication describes the use of PMA-sized training frames for 100GBASE-KP4 Ethernet to facilitate link training and equalization.
• Potential Anticipation: This builds on the concepts of link training and equalization for high-speed Ethernet (similar to US20130343400A1 and US20140086264A1) by specifying the use of particular training frames. The training phase, as mentioned in US11012252B2 (e.g., in relation to Figures 4 and 5, and controller 216), is a common aspect of high-speed serial communication. The specific content and application of these training frames within an active cable that performs CDR and re-modulation internally might differentiate US11012252B2.

8. US9322704B1

• Full Citation: US9322704B1, "Composite active optical cables," granted April 26, 2016.
• Publication/Filing Date: October 18, 2013 (priority date).
• Brief Description: This patent describes composite active optical cables, which integrate both optical and electrical components to manage power and signaling.
• Potential Anticipation: This further elaborates on "active" cables by combining optical and electrical aspects. While still focused on optical transmission, the idea of a composite active cable managing both signal and power might broadly relate to the active nature of the Ethernet cable in US11012252B2. However, the core claims of US11012252B2 are specific to electrical Ethernet cables and the detailed signal processing within them.

9. US9337993B1

• Full Citation: US9337993B1, "Timing recovery in a high speed link," granted May 10, 2016.
• Publication/Filing Date: December 27, 2013 (priority date).
• Brief Description: This patent describes methods and systems for timing recovery in high-speed communication links, which is crucial for accurate data reception.
• Potential Anticipation: This patent directly relates to "clock and data recovery" (CDR), a fundamental aspect of US11012252B2's independent claims. The techniques for timing recovery described could be seen as anticipating the CDR functions within the transceivers of the active Ethernet cable. However, US11012252B2's claims specify where and how CDR is applied (on both inbound and transit signals, with specific equalization strategies) within an active cable architecture, which might still represent a novel combination or application of known CDR techniques.

10. US20150334186A1

• Full Citation: US20150334186A1, "Coax Adaptor for Ethernet Physical Layer Transceiver," published November 19, 2015.
• Publication/Filing Date: May 15, 2014 (priority date).
• Brief Description: This publication describes an adapter that allows an Ethernet Physical Layer Transceiver (PHY) to operate over coaxial cable. It might involve signal conditioning for compatibility.
• Potential Anticipation: This reference pertains to adapting Ethernet signals to different physical media (coaxial cable), which inherently involves signal processing for compatibility. This could broadly relate to the idea of ensuring robust data transfer over a particular cable medium. However, US11012252B2 focuses on active processing within the Ethernet cable itself, with two stages of CDR and re-modulation, rather than an adapter for a different medium.

11. US20160197434A1

• Full Citation: US20160197434A1, "Flat ethernet cables and associated systems, devices, and methods," published July 7, 2016.
• Publication/Filing Date: January 5, 2015 (priority date).
• Brief Description: This publication describes the physical construction of flat Ethernet cables and systems associated with them.
• Potential Anticipation: This reference is primarily focused on the physical form factor of Ethernet cables. It does not appear to directly anticipate the active electronic components (transceivers performing CDR and re-modulation) or the specific equalization strategies central to US11012252B2's independent claims.

12. US20180241579A1

• Full Citation: US20180241579A1, "Power supply system, power sourcing equipment, and ethernet y cable," published August 23, 2018.
• Publication/Filing Date: April 9, 2015 (priority date).
• Brief Description: This publication describes power supply systems for Ethernet, including Y-cables that might provide power to devices or active components.
• Potential Anticipation: This reference addresses power delivery in Ethernet cables, which is a necessary aspect for "active" cables like the one in US11012252B2 (since its transceivers are "powered"). However, it does not describe the signal processing aspects (CDR, re-modulation, equalization) that form the core of US11012252B2's claims.

13. US20200280458A1

• Full Citation: US20200280458A1, "Active ethernet cable," published September 3, 2020.
• Publication/Filing Date: March 1, 2019 (priority date).
• Brief Description: This is a prior publication of US11012252B2, listing the same title, inventors, and assignee.
• Potential Anticipation: As a prior publication of the same patent, it is not considered prior art under 35 U.S.C. § 102 against its own granted claims, but rather part of the same patent family.

14. US20200280329A1

• Full Citation: US20200280329A1, "Active 1:n breakout cable," published September 3, 2020.
• Publication/Filing Date: March 1, 2019 (priority date).
• Brief Description: This publication describes an active breakout cable, such as a 1:4 breakout cable for Ethernet, which can adapt to different generations of Ethernet standards or split high-speed signals into multiple lower-speed lanes.
• Potential Anticipation: This is closely related to US11012252B2, as US11012252B2 itself discusses breakout cables in its detailed description (Figures 7 and 8). This reference focuses on the "breakout" aspect, but the underlying active cable technology with transceivers, CDR, and re-modulation is highly similar. Since it shares the same priority date and assignee, it is likely part of the same intellectual property portfolio rather than anticipating US11012252B2 under 35 U.S.C. § 102.

15. CN111641090A

• Full Citation: CN111641090A, "An active 1: n branch cable," published September 8, 2020.
• Publication/Filing Date: March 1, 2019 (priority date).
• Brief Description: This Chinese patent application describes an active 1:n branch (breakout) cable.
• Potential Anticipation: Similar to US20200280329A1, this is a related application from the same priority date and assignee, focusing on breakout cables. Its relationship to US11012252B2 is as a family member rather than prior art for novelty purposes.

In summary, many of the cited patents broadly deal with "active" cables, high-speed Ethernet, link training, and signal integrity. US20130343400A1, US20140086264A1, US20140146833A1, and US9337993B1 are particularly relevant as they address aspects of link training, equalization, and timing recovery in high-speed communication. However, the specific inventive contribution of US11012252B2 lies in the dual-stage CDR and re-modulation within the cable's connectors, coupled with the distinct application of fixed, cable-independent equalization for host interfaces and potentially cable-dependent equalization for the internal cable links. This specific architectural and parameter management approach within an active Ethernet cable is what differentiates US11012252B2 from the broader prior art.

US Patent 11012252 ("Active Ethernet cable") presents an active Ethernet cable design where transceivers within the cable's connectors perform clock and data recovery (CDR) and re-modulation on both inbound (host-to-cable) and outbound (cable-to-host) data streams. A key distinguishing feature across its independent claims (Claims 1, 6, and 11) is the use of fixed, cable-independent equalization parameters for the host-facing CDR (receive) and re-modulation (transmit) functions. This analysis will identify combinations of prior art references that would render these claims obvious to a person having ordinary skill in the art (POSITA) in high-speed Ethernet communication.

The priority date of US11012252 is March 1, 2019. References published or having priority dates before this are considered prior art. References from the same patent family or with the same priority date, such as US20200280458A1 and US20200280329A1, are not considered for obviousness.

Obviousness Analysis for Independent Claim 1 (Active Ethernet cable)

Claim 1 Elements:

1. Electrical conductors connected between a first connector and a second connector.
2. Connectors adapted to fit into an Ethernet port of a corresponding host device.
3. Connectors receive an electrical input signal (inbound data stream) and provide an electrical output signal (outbound data stream).
4. Each connector includes a respective transceiver.
5. The transceiver performs CDR on the electrical input signal to extract and re-modulate the inbound data stream for transit via the electrical conductors as an electrical transit signal.
6. The transceiver performs CDR on the respective electrical transit signal to extract and re-modulate the transit data stream as the outbound data stream.
7. Crucially: The respective transceivers each employ fixed, cable-independent, equalization parameters for:
   • the re-modulation of the transit data stream as the outbound data stream (host-facing transmit).
   • the clock and data recovery performed on the electrical input signal (host-facing receive).

Combination of Prior Art References:
A combination of US7049937B1 (Nortel Networks), WO2018161273A1 (Dai et al.), and the general knowledge of Ethernet standards (e.g., IEEE 802.3, as cited in US11012252B2) would render Claim 1 obvious.

• US7049937B1 (Nortel Networks): This patent discloses a "self-identifying cable for interconnecting electronic devices," which teaches the fundamental concept of an "active cable" containing embedded electronics (e.g., microcontrollers) to perform functions beyond passive wire. Such a cable inherently includes electrical conductors and connectors adapted for host devices. A POSITA would readily understand that these embedded electronics could include transceivers for signal processing.
• WO2018161273A1 (Dai et al.): Titled "Ethernet link extension method and device," this reference (which is explicitly cited and discussed within US11012252B2) teaches an Ethernet link extension device that performs auto-negotiation and link training. This process involves adaptive equalization (adjusting transmit and receive filters) to mitigate channel non-idealities in high-speed Ethernet communication, particularly for rates like 50 Gbps and beyond. It further discloses transceivers that perform clock and data recovery (CDR) and re-modulation of data streams to facilitate link extension. Dai et al. thus provides the detailed mechanisms for high-speed Ethernet transceivers, CDR, re-modulation, and equalization, all within the context of extending an Ethernet link.

Motivation to Combine:
A POSITA, seeking to overcome the limitations of passive copper cables for high-speed Ethernet (e.g., 50 Gbps per lane or more) over extended lengths, would be motivated to combine the active cable concept taught by Nortel with the high-speed Ethernet link extension and equalization techniques described by Dai et al.. The objective would be to create an active Ethernet cable that regenerates signals to maintain robust data transfer over longer distances.

Addressing the "Fixed, Cable-Independent Equalization Parameters" Limitation:
The critical aspect of Claim 1 is the use of "fixed, cable-independent, equalization parameters" for the host-facing interfaces (CDR on the electrical input signal and re-modulation to the outbound data stream). While Dai et al. teaches adaptive equalization, a POSITA would recognize that for an active cable acting as a transparent link extender or retimer, the interface to the host device should ideally be standard-compliant and predictable.

• Interoperability: Ethernet standards (such as IEEE Std 802.3-2015, which US11012252B2 acknowledges) define specific electrical characteristics for network interfaces. To ensure an active cable is mass-manufacturable and broadly compatible with various host devices from different manufacturers, its host-facing transceivers should present a consistent, standard-compliant electrical interface. If the host-facing interface were to adapt its equalization parameters based on the specific host, it could lead to interoperability issues or interfere with the host device's own PHY (Physical Layer) training and operations.
• Predictable Performance: The US11012252B2 patent itself states, "the inbound data streams may be expected to be compliant with the relevant standard and may be expected to have experienced essentially no deterioration from their traversal of the network interface port's receptacle pins and the cable assembly's connector plug pins." This implies that the active cable receives a clean, standard signal from the host and should output a clean, standard signal to the host. Therefore, configuring the host-facing transceivers with fixed, cable-independent equalization parameters ensures that the active cable acts as an "ideal short link" from the host's perspective, simplifying its integration into existing network environments.
• Design Efficiency: By using fixed, cable-independent parameters for the host interface, the complexity of adaptive equalization can be confined to the internal, cable-facing transceivers, which are designed to compensate for the specific, and potentially varying, characteristics of the cable itself. This allows for optimized performance over the actual cable length while maintaining a simple, standardized interface to the hosts.

Thus, a POSITA combining the active cable concept with high-speed Ethernet link extension would be motivated by principles of interoperability and standard compliance to configure the host-facing transceivers with fixed, cable-independent equalization parameters, rendering Claim 1 obvious.

Obviousness Analysis for Independent Claim 6 (Communication method)

Claim 6 Elements:
This claim describes a communication method within the active Ethernet cable, comprising steps of: receiving electrical input signals, performing CDR on them, re-modulating them as transit data streams, receiving transit data streams, performing CDR on them, and re-modulating them as outbound data streams.
Crucially: It specifies that "said re-modulating the first transit data stream, said re-modulating the second transit data stream, said performing clock and data recovery on the first electrical input signal, and said performing clock and data recovery on the second electrical input signal, each employ fixed, cable-independent, equalization parameters."

Obviousness Argument:
If the active Ethernet cable apparatus of Claim 1 is deemed obvious, then the method of communication performed by such a cable (Claim 6) is also rendered obvious. The steps of receiving, performing CDR, and re-modulating signals are inherent functions of transceivers in high-speed data communication, as taught by Dai et al.. The application of "fixed, cable-independent, equalization parameters" for the host-facing operations, as discussed in the obviousness analysis for Claim 1, is a direct operational consequence of the obvious hardware configuration. The motivation for this specific equalization strategy (interoperability, standard compliance, predictable performance) applies equally to the method of communication.

Obviousness Analysis for Independent Claim 11 (Cable manufacturing method)

Claim 11 Elements:
This claim describes a cable manufacturing method including:

1. Connecting conductor pairs to first and second transceivers.
2. Packaging the first transceiver into a first connector configured to couple electrical input/output signals with a first host device.
3. Packaging the second transceiver into a second connector configured to couple electrical input/output signals with a second host device.
   Crucially: The first and second transceivers are configured to perform CDR and re-modulation as described in Claim 1, and "each configured to employ fixed, cable-independent, equalization parameters for clock and data recovery on the respective electrical input signals and for generating the respective electrical output signals."

Obviousness Argument:
The steps of "connecting" conductor pairs and "packaging" transceivers into connectors are standard manufacturing practices for electronic cables and devices. The core inventive aspect of this manufacturing method lies in "configuring" the transceivers to implement the specific equalization strategy recited in the claim. If the design of the active Ethernet cable with its specific equalization parameter configuration (Claim 1) is obvious, then the method of manufacturing such a cable, including configuring its transceivers accordingly, would also be obvious. The manufacturing steps are merely the means to realize the obvious apparatus. The determination of "cable-dependent equalization parameters" (as mentioned in dependent claims, e.g., Claim 14) during manufacturer-testing is a well-known practice for optimizing performance in active cables that compensate for varying cable lengths and characteristics.

In summary, the specific combination of an active cable architecture with high-speed Ethernet transceivers performing CDR and re-modulation, coupled with the explicit choice of fixed, cable-independent equalization for host-facing interfaces (driven by motivations for interoperability, standard compliance, and predictable performance), renders the independent claims of US11012252 obvious in light of the prior art.