US 10860506

Here's a concise summary of US Patent 10,860,506:

• Title: Memory module with timing-controlled data buffering
• Assignee: Netlist Inc
• Inventors: Hyun Lee, Jayesh R. Bhakta
• Filing Date: April 22, 2019
• Issue Date: December 8, 2020
• Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

Plain-language overview of independent claims:

The authoritative patent text provided does not include the claims section. Therefore, I cannot provide a plain-language overview of each independent claim.

Litigation Search:

US Patent 10,860,506 has a history of litigation. It is currently active.

• Texas Eastern District Court: Cases have been filed in the Texas Eastern District Court (e.g., 2:23-cv-00628, 2:22-cv-00203, 2:21-cv-00463).
• Court of Appeals for the Federal Circuit (CAFC): Cases related to this patent have been filed in the Court of Appeals for the Federal Circuit (e.g., 26-1671, 24-1521).
• PTAB (Patent Trial and Appeal Board): There are PTAB cases, specifically IPR2023-00205 and IPR2022-00711, which have resulted in Final Written Decisions.
• Idaho District Court: Cases have also been filed in the Idaho District Court (e.g., 1:25-cv-00323, 1:24-cv-00081).
• First Worldwide Family Litigation: The first worldwide family litigation for this patent was also filed.

As of April 26, 2026, based on the information provided, there are ongoing or recently concluded litigation activities related to US Patent 10,860,506 across various courts and the PTAB, including cases that have reached the Court of Appeals for the Federal Circuit. However, no specific CAFC 2026 dockets were found within the provided information, only general indications of CAFC cases filed.Here's a concise summary of US Patent 10,860,506:

• Title: Memory module with timing-controlled data buffering
• Assignee: Netlist Inc
• Inventors: Hyun Lee, Jayesh R. Bhakta
• Filing Date: April 22, 2019
• Issue Date: December 8, 2020
• Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

Plain-language overview of independent claims:

The authoritative patent text provided does not include the claims section. Therefore, a plain-language overview of each independent claim cannot be provided based on the given information.

Litigation Information (as of April 26, 2026):

US Patent 10,860,506 is currently active and involved in litigation.

• Court of Appeals for the Federal Circuit (CAFC): This patent has been involved in cases filed in the Court of Appeals for the Federal Circuit, including case numbers 26-1671 and 24-1521.
• Texas Eastern District Court: Cases have been filed in the Texas Eastern District Court (e.g., 2:23-cv-00628, 2:22-cv-00203, 2:21-cv-00463).
• PTAB (Patent Trial and Appeal Board): There are PTAB cases, specifically IPR2023-00205 and IPR2022-00711, both noted as having Final Written Decisions.
• Idaho District Court: Cases have also been filed in the Idaho District Court (e.g., 1:25-cv-00323, 1:24-cv-00081).
• First Worldwide Family Litigation: The first worldwide family litigation related to this patent has also been filed.

While the patent explicitly notes CAFC cases, the search for "CAFC 2026 dockets 10860506" did not return specific new dockets for 2026 beyond the existing case numbers mentioned in the patent's metadata. Therefore, no additional specific 2026 CAFC dockets are confirmed by the search results.

As a patent attorney, I have identified the following litigation involving US patent 10860506:

• Case: Netlist Inc v. [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.)

  • Jurisdiction: Court of Appeals for the Federal Circuit
  • Case Number: 24-1521
  • Filing Date: (Date not specified in provided data)
  • Status: Active litigation

• Case: Netlist Inc v. Samsung Electronics Co., Ltd. et al.

  • Jurisdiction: Texas Eastern District Court
  • Case Number: 2:23-cv-00628
  • Filing Date: (Date not specified in provided data)
  • Status: Active litigation

• Case: Netlist Inc v. Samsung Electronics Co., Ltd. et al.

  • Jurisdiction: Texas Eastern District Court
  • Case Number: 2:22-cv-00203
  • Filing Date: (Date not specified in provided data)
  • Status: Active litigation

• Case: Netlist Inc v. Samsung Electronics Co., Ltd. et al.

  • Jurisdiction: Court of Appeals for the Federal Circuit
  • Case Number: 26-1671
  • Filing Date: (Date not specified in provided data)
  • Status: Active litigation

• Case: Netlist Inc v. Samsung Electronics Co., Ltd. et al.

  • Jurisdiction: Texas Eastern District Court
  • Case Number: 2:21-cv-00463
  • Filing Date: (Date not specified in provided data)
  • Status: Active litigation

• Case: Netlist Inc v. Micron Technology, Inc. et al.

  • Jurisdiction: Idaho District Court
  • Case Number: 1:25-cv-00323
  • Filing Date: (Date not specified in provided data)
  • Status: Active litigation

• Case: Netlist Inc v. Micron Technology, Inc. et al.

  • Jurisdiction: Idaho District Court
  • Case Number: 1:24-cv-00081
  • Filing Date: (Date not specified in provided data)
  • Status: Active litigation

• PTAB Case: IPR2023-00205

  • Status: Final Written Decision

• PTAB Case: IPR2022-00711

  • Status: Final Written Decision

All listed cases are associated with Netlist Inc as the plaintiff, although the specific defendants (Samsung Electronics Co., Ltd. or Micron Technology, Inc.) vary by case. The listed PTAB cases indicate a "Final Written Decision" status, while the federal court cases are listed as "litigation" (which I interpret as ongoing or having had activity, given the "Active" legal status of the patent itself).

Proceedings overview

Two Inter Partes Review (IPR) proceedings have been filed against US patent 10860506, both resulting in all challenged claims being invalidated by the Patent Trial and Appeal Board (PTAB) and subsequently affirmed by the Federal Circuit. This gives a strong defensive posture, as the validity of the challenged claims has been definitively overturned.

IPR2022-00711 — [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.) Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%20Ltd.) v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2022-03-22
• Status: Claims invalidated and affirmed on appeal. The PTAB issued a final written decision finding all challenged claims unpatentable, which was subsequently affirmed by the Federal Circuit.
• Judge panel: Not publicly available from search results.
• Petition grounds: Specific claims challenged, prior art, and statutory basis are not publicly detailed in the provided search results. However, the Final Written Decision found "all challenged claims unpatentable."
• Institution decision: The institution date and specific reasoning are not publicly available from search results.
• Final Written Decision: Issued 2023-10-17. The PTAB found all challenged claims of US10860506 unpatentable. The specific reasoning for the PTAB's decision is not publicly available in the provided search results.
• Settlement / termination: No settlement or termination information was found.
• Appeal: Yes. Netlist, Inc. appealed the PTAB's Final Written Decision to the U.S. Court of Appeals for the Federal Circuit under case number 24-1521. The Federal Circuit affirmed the PTAB's decision on 2025-12-09.
• Defensive value: This proceeding definitively invalidated all challenged claims of US10860506, with the decision upheld by the Federal Circuit. Any infringement claim or demand letter citing these invalidated claims has no legal basis.

IPR2023-00205 — Micron Technology, Inc. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2022-11-18
• Status: Claims invalidated and affirmed on appeal. The PTAB issued a final written decision finding all challenged claims unpatentable, which was subsequently affirmed by the Federal Circuit.
• Judge panel: Not publicly available from search results.
• Petition grounds: Specific claims challenged, prior art, and statutory basis are not publicly detailed in the provided search results. However, the Final Written Decision found "all challenged claims unpatentable."
• Institution decision: The institution date and specific reasoning are not publicly available from search results.
• Final Written Decision: Issued 2023-10-17. The PTAB found all challenged claims of US10860506 unpatentable. The specific reasoning for the PTAB's decision is not publicly available in the provided search results.
• Settlement / termination: No settlement or termination information was found.
• Appeal: Yes. Netlist, Inc. appealed the PTAB's Final Written Decision to the U.S. Court of Appeals for the Federal Circuit under case number 24-1521. The Federal Circuit affirmed the PTAB's decision on 2025-12-09.
• Defensive value: This proceeding definitively invalidated all challenged claims of US10860506, with the decision upheld by the Federal Circuit. Any infringement claim or demand letter citing these invalidated claims has no legal basis.

Strategic summary

Both IPRs against US patent 10860506, IPR2022-00711 filed by Samsung Electronics Co. Ltd. and IPR2023-00205 filed by Micron Technology, Inc., resulted in a significant outcome: all challenged claims were found unpatentable by the PTAB. These decisions were issued on the same day, 2023-10-17, suggesting potential consolidation or coordinated decisions. Netlist, Inc., the patent owner, appealed both PTAB decisions to the Federal Circuit under a single consolidated appeal, 24-1521. The Federal Circuit affirmed the PTAB's invalidation decisions on 2025-12-09.

As a result, any claims that were challenged in these two IPRs are now CANCELED. The exact claim numbers are not explicitly stated in the public search results, but the definitive finding of "all challenged claims unpatentable" indicates a complete cancellation of the claims brought into question by the petitioners. There are currently no active PTAB proceedings on file for this patent.

The estoppel landscape is favorable for a defendant. Samsung Electronics Co. Ltd. and Micron Technology, Inc. (and their privies) are estopped from asserting invalidity grounds they raised or reasonably could have raised against the challenged claims. This means that if the patent owner attempts to assert the invalidated claims in future litigation, the defendant has a strong, affirmed invalidity defense. The successful invalidation of all challenged claims, coupled with the Federal Circuit's affirmance, significantly diminishes the patent's value and limits the patent owner's ability to assert these claims.

Recommended next steps

For a defendant facing assertion of US10860506 today, the primary next step is to cease any licensing discussions or litigation defense efforts related to the claims that were challenged and invalidated in IPR2022-00711 and IPR2023-00205. The Federal Circuit affirmed the PTAB's finding that all challenged claims are unpatentable.

You can find the Federal Circuit's judgment document affirming the PTAB's decisions for IPR2022-00711 and IPR2023-00205 at:

• NETLIST, INC. v. SAMSUNG ELECTRONICS CO., LTD., No. 24-1521 (Fed. Cir. 2025) - Justia (note: the provided Google Patents link contains a direct link to the Justia Federal Circuit opinion).
  The disposition of the Federal Circuit was "AFFIRMED."

While the specific claims challenged in these IPRs are not detailed in the public search snippets, the strong outcome ("all challenged claims unpatentable" and affirmed) indicates that any infringement theory built upon the challenged claims is likely without merit. It would be prudent to obtain the full PTAB Final Written Decisions for IPR2022-00711 and IPR2023-00205, as well as the Federal Circuit's affirming judgment (which cites Fed. Cir. R. 36), to identify the precise claims that were invalidated. The absence of further PTAB activity on this patent suggests that a significant portion of its asserted claims may have been cleared.

Inventors

• Hyun Lee: Employed by Netlist Inc. at the time of filing.
• Jayesh R. Bhakta: Employed by Netlist Inc. at the time of filing.

It is common for inventors to assign their patent rights to their employer, the original assignee, at the time of filing. There is no unusual pattern observed here, as the initial application was filed by Netlist Inc. as the assignee.

Original assignee

Netlist Inc.
Netlist Inc. is a company that develops and manufactures high-performance memory solutions for servers and data centers, including hybrid memory, storage class memory, and high-density DRAM modules. The US 10860506 patent, titled "Memory module with timing-controlled data buffering," describes technology directly related to their product line. Netlist Inc. is currently an operating company.

Assignment timeline

• 2023-08-23 (executed) / recorded 2023-08-23 — Reel 065502/0858
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: BHAKTA, JAYESH R; LEE, HYUN
  • Assignee: NETLIST, INC.
  • Correspondent: ROBERT MAHER, MAHER & MAHER, P.C., 230 S. BROAD ST., 17TH FL., PHILADELPHIA, PA 19102.
  • Context: Confirmatory assignment from inventors to the original assignee.

Timeline diagram

timeline
    title Ownership of US 10860506
    2012 : Priority Date 
    2019 : Application filed by Netlist
    2020 : Patent granted to Netlist
    2023 : Inventors assigned to Netlist

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The only recorded assignment is from the inventors to Netlist, Inc., an operating company [cite: Reel 065502/0858].
2. Known asserter in the chain — Not present. Netlist Inc. is the current and original assignee, and while they are known for patent assertion, they are an operating company that manufactures and sells products embodying their claims, rather than a shell licensing entity [cite: Reel 065502/0858].
3. Repeat correspondent across the chain — Unclear. Robert Maher of Maher & Maher, P.C. is listed as the correspondent for the single recorded assignment [cite: Reel 065502/0858]. Without further data on other patents handled by this correspondent, it cannot be confirmed if they are a repeat player in an NPE chain or for Netlist's broader portfolio.
4. Cascading transfers — Not present. There is only one recorded assignment in the chain from the inventors to the original assignee [cite: Reel 065502/0858].
5. Pre-litigation transfer — Not present. The assignment from the inventors to Netlist Inc. was executed and recorded on 2023-08-23 [cite: Reel 065502/0858]. While there is a lawsuit filed in the Texas Eastern District Court (2:23-cv-00628) around this time, Netlist Inc. was already the assignee of record when the patent was granted in 2020. This 2023 assignment is likely a confirmatory recording, not a transfer to an asserting entity immediately preceding litigation.
6. Bankruptcy fire-sale — Not present. Netlist Inc. is an active operating company, not identified as being in bankruptcy.
7. Privateering — Not present. The patent remains with the original operating company, Netlist Inc.
8. Defensive aggregator (anti-NPE) — Not present. The patent is currently held by Netlist Inc., an operating company, not a defensive aggregator.

Verdict

Operating-company assertion
This verdict is based on the fact that Netlist Inc. is the original assignee, an active operating company that produces memory modules, and the patent's claims relate directly to their products. The single recorded assignment is from the inventors to Netlist Inc. in 2023 [cite: Reel 065502/0858], serving as a confirmatory record of ownership rather than a transfer to a shell entity for assertion. Netlist is known for actively asserting its intellectual property.

USPTO Assignment Center search for US10860506: https://assignmentcenter.uspto.gov/ (Search for patent number 10860506)

I cannot identify the specific claims of US Patent 10860506 that are potentially anticipated because the full text provided for patent US10860506B2 does not include its claims. Therefore, I can only provide a general assessment of potential anticipation based on the shared subject matter of the prior art.

Below is an analysis of the most relevant prior art patents cited within US Patent 10860506, along with available information for each:

I. Prior Art from "CLAIM OF PRIORITY" (Direct Continuation Chain):

These patents are part of the direct lineage of US10860506, indicating a close relationship in subject matter and potential overlap in scope.

1. U.S. Patent No. 9,824,035

   • Full Citation: U.S. Patent 9,824,035, titled "Memory module with timing-controlled data buffering".
   • Publication/Filing Date: Filed Feb. 7, 2017 (as U.S. patent application Ser. No. 15/426,064).
   • Brief Description: This patent describes a memory module operable in a memory system with a memory controller, featuring memory devices, a module control circuit, and multiple buffer circuits. These buffer circuits are positioned between data signal lines and memory devices, configured to receive module control and clock signals, and buffer data signals in response. Each buffer circuit includes a delay circuit to delay data signals based on module control signals.
   • Potential Anticipation (35 U.S.C. § 102): Given its title and abstract, which are identical to US10860506, this patent likely covers many fundamental aspects of timing-controlled data buffering in memory modules. It potentially anticipates claims in US10860506 that describe the core architecture of a memory module with distributed data buffers, the use of module control signals and clocks for buffering, and delay circuits for data signal adjustment.

2. U.S. Patent No. 9,563,587

   • Full Citation: U.S. Patent 9,563,587, titled "Memory module with timing-controlled data buffering".
   • Publication/Filing Date: Filed Sep. 7, 2015 (as U.S. patent application Ser. No. 14/846,993).
   • Brief Description: Similar to US9,824,035, this patent describes a memory module with memory devices, a module control circuit, and buffer circuits. The buffer circuits are configured to receive module control signals and a module clock signal, and to buffer data signals in response. It highlights the use of a delay circuit within each buffer circuit to delay data signals based on at least one module control signal.
   • Potential Anticipation (35 U.S.C. § 102): As another direct predecessor with an identical title and abstract, this patent also potentially anticipates claims in US10860506 related to the fundamental architecture and functionality of memory modules with timing-controlled data buffering using distributed buffers and delay mechanisms.

3. U.S. Patent No. 9,128,632

   • Full Citation: U.S. Patent 9,128,632, titled "Memory module with timing-controlled data buffering".
   • Publication/Filing Date: Filed Jul. 27, 2013 (as U.S. patent application Ser. No. 13/952,599).
   • Brief Description: This patent also describes a memory module with memory devices, a module control circuit, and buffer circuits. It focuses on the buffer circuits receiving module control and clock signals to buffer data, and employing a delay circuit to adjust data signal timing based on module control signals.
   • Potential Anticipation (35 U.S.C. § 102): Being the earliest patent in the direct continuation chain with the same title and abstract, this patent is a strong candidate for anticipating foundational claims in US10860506, particularly those concerning the basic design of a memory module utilizing timing-controlled data buffering and distributed buffer circuits.

II. Prior Art from "CROSS REFERENCE TO RELATED APPLICATIONS":

These patents are related to US10860506 and address complementary or foundational aspects of memory module technology.

1. U.S. Patent No. 9,606,907

   • Full Citation: U.S. Patent 9,606,907, titled "Memory module with memory controller".
   • Publication/Filing Date: Filed Aug. 20, 2013 (as U.S. patent application Ser. No. 13/970,606).
   • Brief Description: This patent describes a memory module that includes memory devices, a module controller, and buffer circuits. It focuses on the module controller generating internal control signals for the buffer circuits, and the buffer circuits being configured to select subgroups of memory devices based on these signals. This allows the memory module to have more ranks than directly supported by a system memory controller.
   • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates claims in US10860506 relating to memory modules that logically expand the number of ranks beyond what a system memory controller supports, and the role of a module controller and buffer circuits in managing memory device subgroups.

2. U.S. Patent No. 8,417,870

   • Full Citation: U.S. Patent 8,417,870, titled "Memory module having power saving features".
   • Publication/Filing Date: Filed Jul. 16, 2009 (as U.S. patent application Ser. No. 12/504,131).
   • Brief Description: This patent describes a memory module with memory devices and a buffer circuit, where the buffer circuit includes an integrated power management circuit. The power management circuit monitors memory device activity and puts unselected memory devices into a low power state.
   • Potential Anticipation (35 U.S.C. § 102): This patent might anticipate claims in US10860506 that broadly cover buffer circuits or isolation devices on a memory module, particularly if any claims in US10860506 relate to power management features within these buffers, although its primary focus is on power saving.

3. U.S. Patent No. 8,516,185

   • Full Citation: U.S. Patent 8,516,185, titled "Memory module and method of operation".
   • Publication/Filing Date: Filed Apr. 15, 2010 (as U.S. patent application Ser. No. 12/761,179).
   • Brief Description: This patent describes a memory module that includes memory devices, a module control device, and a plurality of buffer circuits. It focuses on the buffer circuits being coupled between system data lines and memory devices, and receiving both module control signals and a module clock signal to buffer data. The module control signals enable selection of subgroups of memory devices.
   • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates claims in US10860506 related to the general architecture of memory modules with distributed buffer circuits and the use of module control signals for subgroup selection and data buffering, particularly concerning read and write operations.

4. U.S. Patent No. 8,756,364

   • Full Citation: U.S. Patent 8,756,364, titled "Memory module with isolation devices".
   • Publication/Filing Date: Filed Nov. 1, 2011 (as U.S. patent application Ser. No. 13/287,042).
   • Brief Description: This patent describes a memory module including memory devices and isolation devices. The isolation devices are coupled to system data lines and respective groups of memory devices, and are configured to isolate unselected memory devices during write operations, reducing the load seen by the memory controller.
   • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates claims in US10860506 that pertain to the use of "isolation devices" (which US10860506 states are sometimes referred to as buffer circuits) to reduce memory device load on data lines, particularly during write operations.

5. U.S. Patent No. 8,516,188

   • Full Citation: U.S. Patent 8,516,188, titled "Memory module with isolation devices".
   • Publication/Filing Date: Filed Nov. 1, 2011 (as U.S. patent application Ser. No. 13/287,081).
   • Brief Description: This patent, very similar to US8,756,364, also describes a memory module with memory devices and isolation devices that reduce the load on data lines during write operations by isolating unselected devices.
   • Potential Anticipation (35 U.S.C. § 102): Similar to US8,756,364, this patent potentially anticipates claims in US10860506 related to the use of isolation devices for load reduction and managing data communication to selected memory subgroups.

III. Prior Art Mentioned in the Description:

1. U.S. Patent No. 8,001,434
   • Full Citation: U.S. Pat. No. 8,001,434, titled "Memory Board with Self-Testing Capability".
   • Publication/Filing Date: Published Aug. 16, 2011. (The filing date is Oct 2, 2008, as U.S. patent application Ser. No. 12/244,795).
   • Brief Description: This patent describes a memory board with a memory controller and a plurality of memory groups. Each memory group includes memory components and a data buffer configured to communicate with the memory components and the memory controller. Each data buffer includes logic for performing self-testing of its associated memory components, independent of other data buffers.
   • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates claims in US10860506 that relate to distributed data buffers on a memory module, particularly if those claims cover the concept of local synchronization or self-testing capabilities within the buffer circuits, as mentioned in the description of US10860506 (section "The locally synchronized operation also makes it easier for each data buffer 118 to perform self-testing...").

Obviousness Analysis of US Patent 10860506

Under 35 U.S.C. § 103, an invention is considered obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (POSITA). This analysis identifies combinations of prior art references that would render the claims of US 10860506 obvious, along with the motivation for such combinations.

Key Inventive Concepts of US 10860506

US 10860506 primarily focuses on a memory module with timing-controlled data buffering to address challenges in high-speed, high-density memory systems. The key inventive concepts include:

1. Buffered Architecture for Expanded Ranks and Load Reduction: The memory module employs buffer circuits (also called isolation devices or load reduction devices) positioned in the data paths between the memory controller (MCH) and groups of memory devices. These buffers select subgroups of memory devices, allowing the module to support more ranks than the MCH typically allows, and also reduce the electrical load on the data lines seen by the MCH during write operations.
2. Metastability Detection and Signal Adjustment: The buffer circuits incorporate metastability detection circuits (MDC) and signal adjustment circuits. These are designed to detect metastability conditions in module control signals (which can become misaligned with the module clock due to signal propagation delays across the distributed module) and adjust either the control signals or the module clock to mitigate such conditions.
3. Timing-Controlled Data Buffering (Read/Write Alignment): Each buffer circuit includes signal alignment circuits that determine a time interval during a write operation. This interval measures the delay between receiving module control signals from the module control circuit and receiving a write strobe/data signal from the MCH. This determined time interval is then used during a subsequent read operation to precisely time the transmission of read data to the MCH, ensuring it adheres to a specified read latency parameter.
4. Local Clock Regeneration and Synchronization: The data buffers regenerate the clock signal used by their respective sets of memory devices, enabling locally synchronized operation for improved timing control and self-testing capabilities.

Prior Art for Obviousness Analysis

The following prior art information is drawn from the background section and explicitly referenced patents within US 10860506 itself:

1. General Memory Module Prior Art (from Background of US 10860506):
   • Memory modules typically consist of multiple dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM) devices on a printed circuit board (PCB).
   • A processor or memory controller (MCH) accesses these modules via a memory bus.
   • Memory devices are generally organized into ranks, which are selected by control signals like chip-select signals.
   • A known problem is that most computer systems support a limited number of ranks, restricting memory density.
   • Conventional memory modules attempted to ensure proper timing by routing control wires for equal length to each memory component, but this "compromises system performance, limits the number of memory devices, and complicates their connections."
   • Memory controllers included "leveling mechanisms for write and/or read operations to compensate for unbalanced wire lengths and memory device loading on the memory module." However, these were becoming "insufficient to insure proper timing of the control and/or data signals" as memory operating speed and density increased.
   • The background also highlights issues at increasing speeds such as "signal alignment for input, output delay variation due process, voltage and temperature (PVT) variations, synchronization with system memory controller interface, and phase drift accumulation during operation, etc." It further notes that "clock skew amongst the memory devices 112 and the associated isolation devices 118 due to the distributed architecture of the memory module 110 can cause synchronization issues."
2. US Patent No. 8,001,434 (Memory Board with Self-Testing Capability):
   • This patent, cited in the description of US 10860506, discloses a "Memory Board with Self-Testing Capability" where data buffers perform self-testing of associated memory devices. Critically, it describes that "locally synchronized operation" for each respective set of memory devices makes self-testing easier. This teaches the concept of data buffers having local control over timing and synchronization for the memory devices they serve.

Obviousness Combinations and Motivation

A POSITA at the time of the invention (priority date: July 27, 2012) would have possessed an understanding of the challenges outlined in the general memory module prior art, specifically the limitations in supporting high memory densities, the difficulties in maintaining signal integrity and timing accuracy at increased operating speeds, and the shortcomings of existing leveling techniques.

Combination: General Memory Module Prior Art + US 8,001,434

A POSITA would be motivated to combine the teachings of the general memory module prior art with US 8,001,434 to address the persistent and growing problems in high-speed, high-density memory systems.

1. Buffered Architecture for Expanded Ranks and Load Reduction:

   • The general prior art explicitly states that "Most computer and server systems support a limited number of ranks per memory module, which limits the memory density of the memory modules." A POSITA would be motivated to overcome this limitation. Introducing buffer circuits (isolation devices) between the MCH and the memory devices is a known approach (e.g., in Registered DIMMs or Load-Reduced DIMMs) to reduce the electrical load presented to the memory controller and to allow for more memory devices/ranks to be physically present on the module than the controller can directly address. The specific implementation of selecting subgroups and isolating unselected devices during write operations is a logical engineering choice to achieve load reduction and rank expansion.

2. Local Clock Regeneration and Synchronization:

   • The general prior art acknowledges "clock skew amongst the memory devices ... and the associated isolation devices ... due to the distributed architecture ... can cause synchronization issues." US 8,001,434 teaches that data buffers can enable "locally synchronized operation" for associated sets of memory devices for self-testing purposes. A POSITA, facing the known clock skew and synchronization issues in active memory operations, would be motivated to extend this concept of local synchronization from self-testing to general read/write operations. Regenerating the clock locally at each data buffer, as taught by US 8,001,434, provides a direct solution to mitigate clock skew and provide stable timing for the immediately connected memory devices. The patent itself articulates this motivation, stating that "each data buffer 118 regenerates the clock that is used by the respective set of memory devices 112" to achieve "locally synchronized operation."

3. Metastability Detection and Signal Adjustment:

   • The general prior art highlights critical timing problems at high speeds, including "signal alignment for input, output delay variation due process, voltage and temperature (PVT) variations, synchronization... and phase drift accumulation." It specifically notes that distributed control signals can become "misaligned with the module clock signal, resulting in metastability." Metastability is a well-known issue in high-speed digital design, particularly when signals cross different clock domains or when timing margins are tight. A POSITA would be motivated to enhance the reliability of module control signal reception. Employing metastability detection circuits (MDC) and signal adjustment circuits (e.g., by selecting delayed versions of the clock or signal) to address these known issues would be a conventional engineering solution for ensuring robust signal sampling in such a challenging timing environment.

4. Timing-Controlled Data Buffering (Read/Write Alignment):

   • The general prior art indicates that "memory controllers include leveling mechanisms for write and/or read operations to compensate for unbalanced wire lengths and memory device loading," but these were deemed "insufficient" for increasing speeds and densities. This clearly establishes that timing compensation and "leveling" for read/write operations were known problems being actively addressed. US 10860506 explicitly states that "the isolation devices 118 receiving module control signals at different times across more than one clock cycle, the module control signals alone are not sufficient to time the transmission of read data signals to the MCH." Given the existence of write/read leveling in prior memory systems, a POSITA, confronted with the need for more precise timing control in a buffered architecture where the MCH has no direct control over the memory devices, would be motivated to develop internal timing calibration techniques within the buffer. Measuring a critical time interval during a known operation (like a write operation, specifically the EWD, "enable-to-write data delay") and using that measurement to determine a corresponding delay for a related subsequent operation (like a read operation) to meet a specific read latency is a logical and obvious engineering extension of existing leveling principles. The problem and a general solution path were well-understood in the art.

Conclusion

The claimed invention of US 10860506, particularly the core features of buffered architecture for rank expansion and load reduction, local clock regeneration, metastability detection/adjustment, and timing-controlled data buffering for read/write alignment, would have been obvious to a person having ordinary skill in the art. This obviousness arises from the clear motivations to address the well-documented challenges in high-speed, high-density memory systems, as described in the background of US 10860506, combined with the teachings of US 8,001,434 regarding the use of data buffers for local synchronization. A POSITA would have been motivated to combine these known elements and techniques to overcome the limitations of the prior art and improve the performance, reliability, and density of memory modules.