Invalidity dossier
US 9606907
Memory module with distributed data buffers and method of operation
Current assignee: Netlist Inc
Added 9/23/2026, 6:31:27 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US9606907B2
Title: Memory module with distributed data buffers and method of operation
Patent number / application: US9606907B2; application US13/970,606; published as US20140040568A1.
Inventor(s): Hyun Lee; Jayesh R. Bhakta.
Assignee: Netlist Inc (original assignee; current assignee listed as Netlist Inc).
Key dates (as listed):
- Priority date (assumed): 2009-07-16, claimed from US12/504,131 (patent/US8417870B2).
- Filing date: 2013-08-20.
- Publication date: 2017-03-28 (grant).
- Adjusted expiration listed: 2030-07-05; legal status listed as "Expired – Fee Related."
Purpose (from the supplied definitions): "the present disclosure relates generally to memory subsystems of computer systems, and more specifically to systems, devices, and methods for improving the performance and the memory capacity of memory subsystems or memory 'boards,' particularly memory boards that include dual in-line memory modules (DIMMs)."
Plain-language scope (only what the excerpt supports): The patent concerns memory modules, notably DIMMs, that use distributed data buffers. The excerpt identifies terminology central to the disclosure — DIMMs, DRAM/SDRAM, PCB, and ranks of memory, where "the memory devices of a memory module are generally arranged as ranks or rows of memory, each rank of memory generally having a bit width." The listed prior-art keywords are memory, memory devices, module, data, and control signals. Classifications include G11C5/02, G11C5/025, G11C5/04, G11C5/06, G11C5/066, G11C7/10, and G11C8/12.
Source: https://patents.google.com/patent/[US9606907](/patent/US9606907)/en
What the excerpt does not establish: It does not set out any claim language, a full written description, the number or arrangement of buffers, or how data/control signals are routed. The supplied text contains no abstract, no detailed description, and no claims, so the precise scope of coverage cannot be determined from it. The priority date, assignee listings, and legal status are expressly flagged in the source as assumptions or non-legal conclusions.
Generated 10/1/2026, 9:42:44 PM
Cases on file (0)
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Litigation summary
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Proceedings on file (0)
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No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.