US 8510859

I'll search for litigation/docket information on this specific patent, then compile the summary.

I found no litigation or CAFC hits. Let me try two more targeted docket-focused searches before concluding.

Search results for docket/litigation records

I searched for litigation and Federal Circuit activity specific to US 8,510,859. No district court case, PTAB proceeding (IPR/PGR/CBM), or CAFC 2026 docket entry for this patent was found. All hits that came back were for different patents with superficially similar numbers (e.g., US 8,509,859 "Jarosinski"; US 8,523,085 "Capstan Ag"; US 8,859,510), which I am not treating as substitutes. On the record available to me, this appears to be a patent that has not been litigated or appealed; the only recorded post-grant activity is maintenance-fee payments (4th year 2017-02-02; 8th year 2021-01-27; 12th year 2025-01-06). I cannot rule out non-public or newly filed proceedings; treat the "no litigation" finding as based on the searches performed, not as authoritative.

US 8,510,859 B2 — Bibliographic summary

Abstract (verbatim): Methods and arrangements to launch trusted, distinct, co-existing environments are disclosed. Embodiments may launch trusted, distinct, co-existing environments in pre-OS space with high assurance. A hardware-enforced isolation scheme may isolate the partitions to facilitate storage and execution of code and data. In many embodiments, the system may launch a partition manager to establish embedded and main partitions. Embedded partitions may not be visible to the main OS and may host critical operations. A main partition may host a general-purpose OS and user applications, and may manage resources that are not assigned to the embedded partitions. Trustworthiness in the launch of the embedded partition is established by comparing integrity metrics for the runtime environment against integrity measurements of a trusted runtime environment for the embedded partition, e.g., by sealing a cryptographic key with the integrity metrics in a trusted platform module. Other embodiments are described and claimed.

Plain-language overview of the independent claims

Claim 1 — Method of launching runtime environments (this is the core claim). Four steps in sequence:

1. Configure a first runtime environment that manages access to its own protected content based on predetermined integrity metrics. Critically, configuring this environment includes executing a hardware partition manager (i.e., the partitioning is done by hardware/firmware/microcode, not by a later-loaded hypervisor).
2. Verify, by a trusted platform module (TPM), the current integrity metrics of that first environment against trusted metrics — and the verifying step itself includes the TPM doing the measuring.
3. Decrypt the protected content for the first environment in response to that successful verification.
4. Only after the first environment verifies, launch a second runtime environment that co-exists with the first on the same processing system — again with TPM-based verification of the second environment's current integrity metrics.

In short: trust the embedded/first partition first, then bring up the coexisting second partition, with the TPM doing the measuring and gating key release.

Claim 10 — Machine-accessible storage medium (no signals; i.e., a non-transitory CRM). The same idea expressed as instructions that cause a processing system to:

• configure a first runtime environment that manages access to its protected content, including executing a hardware partition manager;
• have the TPM measure the first environment's current integrity metrics;
• extend those metrics into a first register of the TPM so they can be compared against trusted metrics, which gates access to a first key after verification;
• decrypt the protected content via that first key; and
• launch a second runtime environment afterward, upon TPM verification of the second environment's metrics, the two environments coexisting, with the TPM measuring the second environment.

Dependent claim families (context): Claims 2–9 depend from claim 1; claims 11–15 depend from claim 10. They add, among other things: assigning and hiding resources (2, 12); establishing a trusted communication channel into the first environment (3); extending metrics into PCR7 (4, 13); key-then-content decryption (5); the second environment's own configure/verify/decrypt cycle (6); releasing resource control to the second environment's OS (7); configuring a main environment and extending its hash into PCR4 (8, 14); and configuring another embedded environment with its hash extended into PCR7 (9, 15). There is no independent system/apparatus claim — only the method claim 1 and the storage-medium claim 10.

Notes and uncertainties

• Literal-reading caveat (per your strict rule): Claim 1 recites "by the trust platform module" in the fourth clause and "by the trusted platform module" in the second, third and fourth clause presentations. I have preserved the literal text; I flag the inconsistency only to note it exists in the granted claim language, not to correct it.
• Status/date uncertainties: Legal status, "Active," the 2029‑06‑11 adjusted expiration, and the maintenance-fee events are Google Patents' representations (the page itself disclaims these as assumptions, not legal conclusions). I have reported them as-is.
• Docket search: As stated, no litigation or CAFC record was located; absence of evidence here is not proof of absence of proceedings.
• Everything else above is drawn from the authoritative full text and bibliographic data of US 8,510,859 provided/retrieved from the patent record itself.

I'll search for litigation involving US patent 8510859.

The initial searches returned noise from other patents. Let me narrow to the specific patent number and litigation databases.

Let me search litigation-specific databases directly and try alternate phrasings.

Litigation search results for U.S. Patent No. 8,510,859

Bottom line: Based on my searches, I found no litigation (district court, Federal Circuit, ITC, or PTAB) involving U.S. Patent No. 8,510,859.

What was searched

I queried for the literal identifiers "8510859," "8,510,859," "US8510859," and the patent's title ("Methods and arrangements to launch trusted, co-existing environments") against litigation- and enforcement-oriented sources and general web indexes that routinely surface court filings (Justia dockets/opinions, CourtListener/RECAP, Docket Alarm, RPX Insight litigation_documents, Unified Patents-style case lists, drugpatentwatch docket pages, Federal Circuit blog filing PDFs).

Critical caveat — beware of the "'859" false positive

The reason this is worth stating plainly: almost every search hit using the shorthand "'859" points to a different patent. I did not auto-correct any of these, but I also did not conflate them with your target. Examples my searches surfaced, each of which is NOT US 8,510,859:

A careless search that "auto-corrects" 8510859 into a truncated '859 shorthand, or that matches the six-digit string inside a longer number, will produce a long list of irrelevant results. None of the above is US 8,510,859.

About the patent itself (for context, not litigation)

• US 8,510,859 B2 — "Methods and arrangements to launch trusted, co-existing environments"
• Inventors: Vincent J. Zimmer; Lyle Cool
• Original/current assignee: Intel Corporation
• Application US 11/527,180; priority/filing date 2006‑09‑26; granted 2013‑08‑13
• Status: Active; adjusted expiration 2029‑06‑11
• Related: divisional US 9,235,707 B2; foreign family members EP 1906333 B1, CN 101154256 B, KR 100989977 B1

The patent appears to have remained in Intel's portfolio (it is a defensive/portfolio asset covering pre‑OS partition launch with a TPM), which is consistent with no recorded assertion activity by Intel or by any third party (there is no indication the patent was ever transferred to a non‑practicing entity, which is where most assertion litigation would arise).

Confidence and recommendation

I have moderate-to-high confidence that there is no known litigation involving US 8,510,859 as of the current date, but I cannot certify a negative. My searches did not return a clean, direct record confirming "no litigation" from a dedicated litigation database, and I was unable to complete direct portal lookups (Unified Patents case list, PACER, Docket Alarm/Alarm patent page) before exhausting my search steps.

To confirm conclusively, I would recommend running the exact registration number (no shorthand) through:

• Unified Patents litigation portal — https://portal.unifiedpatents.com/litigation/caselist
• Docket Alarm / RPX Insight patent page for U.S. 8,510,859
• PACER (search party "Intel Corporation" + patent number) and CAFC docket search
• USPTO Patent Center / PTAB for any IPR/PGR/CBM tied to 11/527,180 or 8,510,859

This is a factual search summary, not legal advice or a freedom-to-operate/clearance opinion. If you need a certified litigation history, a formal search with date-stamped results from the databases above should be commissioned.

If no results appear there either, the answer stands: no litigation is known for US 8,510,859.

I'll start by verifying the PTAB proceedings record via web search before drafting.

The initial hits relate to different patents (e.g., ContentGuard's 6,963,859). Let me search more precisely.

Multiple unrelated "859" patents are muddying results. Let me search PTAB dockets specifically for the Intel/Zimmer patent.

Proceedings overview

Total AIA trial proceedings on file for US 8,510,859: 0. Breakdown by status: active — 0; claims invalidated — 0; claims sustained — 0; settled — 0; institution denied — 0. This is the canonical result from the structured "PTAB proceedings on file" block (USPTO Open Data Portal), and my independent web searches surfaced no IPR, PGR, or CBM naming this patent. The bottom line for a defendant: there is no PTAB win to inherit and no estoppel blanket already spread. US 8,510,859 stands exactly as issued on 2013-08-13 — all 15 claims intact, never challenged, never amended. You would be the first petitioner at the Board, which means (a) no free invalidity finding, but also (b) no § 315(e) estoppel entangling you and no adverse claim-construction record from a prior panel.

No proceedings to report

There is no {PROCEEDING_NUMBER} — {Petitioner} v. {Patent Owner} entry to populate for US 8,510,859. I am stating that plainly rather than manufacturing a docket. Two verification notes:

1. False positives my searches surfaced (explicitly NOT this patent). Several unrelated patents share the "859" shorthand and should be screened out of any docket pull:

If a vendor docket report or an AI research tool hands you one of those numbers as a hit on "US 8,510,859," it is a string-match error. Reject it.

2. Residual uncertainty. My web searches are not a substitute for the Office's own docket, and search engines do not index every PTAB paper. The ODP block is the authoritative source and it reports nothing; the searches agree. I did not find and cannot cite a Notice of Filing Date, institution decision, or FWD for this patent, so any statement about a judge panel, petition ground, or claim-level disposition would be fabrication. There is none to report.

Strategic summary

Claim status: all claims UNTESTED. Claims 1–15 of US 8,510,859 have never been before the PTAB. That means every claim is still live — the two independent claims (claim 1, a method to launch runtime environments; claim 10, a machine-accessible storage medium) as well as the dependent claims (2–9, 11–15), which add the familiar limitations: resource hiding (claims 2, 12), a trusted communication channel (claim 3), extension of current integrity metrics into PCR7 (claims 4, 9, 13, 15), key-then-content decryption (claim 5), a main runtime environment hashed into PCR4 (claims 8, 14), and additional embedded runtimes into PCR7 (claims 9, 15), plus the "additional keys for additional runtime environments" limitation (claim 11). The claim set has not been narrowed, disclaimed, or canceled by any AIA trial. A certificate of correction or an ex parte reexamination would also sit outside the structured block; I saw no evidence of either, but treat that as a "not observed," not a certified negative.

Estoppel landscape: a clean slate — for now, which is a double-edged sword. Because there is no FWD, no § 315(e)(2) estoppel runs against anyone, including you. If you file a first IPR, you may preserving arguments in the parallel district court that a prior petitioner would already have forfeited, and you are not collaterally bound by another petitioner's claim construction. But the same blank slate cuts the other way: you cannot free-ride on a prior petitioner's evidentiary development, expert declarations, or the panel's claim-construction findings — all of that would be yours to build from scratch, at IPR cost. Nothing in the file limits the prior art you may raise, other than the ordinary IPR limits of §§ 102/103 over patents and printed publications (§ 311(b)). System prior art, public use, and on-sale art remain available in district court but not at the Board.

Pattern signals: this patent looks like a defensive portfolio asset, not an assertion vehicle. — US 8,510,859 is Intel-assigned (assignment recorded 2008-04-14; inventors Zimmer and Cool), with a same-family divisional, US 9,235,707 (filed 2013-08-09, granted 2016-01-12), and foreign counterparts EP1906333B1, CN101154256B, and KR100989977B1. There is no nullity-concentrated petitioner history because there is no petitioner. The absence of any IPR is itself informative: well-asserted patents with meaningful revenue exposure reliably attract AIA challenges, often by defensive aggregators like Unified Patents. Fourteen years of granted life (adjusted expiration 2029-06-11) with zero petitions is consistent with a patent that has not been wielded against a commercially motivated adversary. If you are holding a demand letter citing US 8,510,859, that posture is unusual and worth stress-testing — confirm the patent owner's identity and the actual asserted claims before you build a defense around this patent's PTAB history, because there is no history.

Recommended next steps

If you are a defendant:

• There is no FWD to link to and no disposition to quote — I will not invent one. The correct citation for the patent's current status is the patent itself: US 8,510,859 B2 on Google Patents, showing all 15 claims as issued (2013-08-13) with no intervening certificate.
• Confirm the negative independently before relying on it, using the Office's own systems: USPTO PTAB E2E / PTAB Center and the PTAB decisions library. Run the search on the patent number and on the application number 11/527,180 and the family division 13/963,803, since a challenge could be indexed under any of them.
• Because the claims are untested, an IPR is a genuinely open option rather than a crowded one. First-filer positioning matters: you would not be competing with an earlier petitioner's § 315(e) baggage, and you would set the claim-construction record. Budget accordingly (electrical/computer IPR through hearing runs at roughly the medians reported by AIPLA — the PTAB's own practice confirms the trial-stage cost curve, see PTAB rulemaking commentary, 2026).
• Note the current procedural regime, which affects a new petition: as of 2025-10-20, institution decisions are made by the Director rather than an APJ merits panel, and USPTO has proposed rules barring IPRs against patents that have survived a prior validity challenge. Neither changes the outcome here (there is no prior challenge), but the Director-level institution filter may make institutions harder to obtain generally — factor that into your go/no-go.

If proceedings are pending (they are not): the statutory clock to note is 35 U.S.C. § 316(a)(11) — FWD within 12 months of institution, extendable up to 6 months for good cause. Compressed discovery, expert declarations, and the sur-reply window all fall inside that year. None of that is triggered here.

Bottom line: No PTAB activity exists on US 8,510,859 as of the ODP ingest. The absence is the signal — you are not inheriting an invalidation, and you are not fighting one either. The patent is fully intact and untested, so any validity challenge starts from zero, at the Board or in court.

Verification caveat: my searches returned no PTAB record for this patent, but search indexing of PTAB dockets is incomplete and I could not exhaustively query PTAB E2E from this session. Treat the "0 proceedings" figure as authoritative only to the extent the ODP structured block is current; re-confirm in PTAB E2E on the patent number and application number 11/527,180 before filing.

I'll verify the assignment record against live sources before finalizing.

Confirming litigation/assertion activity before finalizing.

US 8,510,859 B2 — Ownership Chain Reconstruction

Patent: Methods and arrangements to launch trusted, co-existing environments
App. No. 11/527,180 · Filed 2006-09-26 · Granted 2013-08-13 · Adjusted expiration 2029-06-11
Assignee of record: Intel Corporation (Delaware)

Source of truth for this report: the legal-events and Patent Citations data on the Google Patents page for US8510859 (which mirrors the USPTO assignment record for reel/frame 020820/0566) plus live searches of USPTO/EU/CN/KR family data and SEC filings. No separate post-issuance assignment records were found.

Inventors

Unusual patterns: none detected.

• Both inventors signed an inline assignment within ~6–9 weeks of filing (2006-11-06 and 2006-11-29) — i.e., neither inventor retained rights and neither is an outside/independent inventor requiring a separate chain.
• No evidence of either inventor departing Intel within 12 months of filing, and no subsequent inventor-side assignments exist. The "all inventors depart → fire-sale" tell is not present.
• One administrative oddity worth noting but not an NPE signal: the inventors' instrument was not recorded until 2008-04-14, roughly 17 months after execution and about 3 weeks after publication of US20080077993A1 (2008-03-27). That is a late perfection of chain of title, consistent with portfolio-administration backlog, not a transfer.

Original assignee

Intel Corporation, a Delaware corporation, 2200 Mission College Blvd., Santa Clara, CA (per family/related Intel filings).

• Primary line of business: semiconductor design and manufacturing — CPUs, chipsets, platforms, and platform firmware/drivers.
• Product embodying the claims: Yes, functionally. The patent's subject matter — a hardware partition manager that launches sequestered embedded partitions by extending integrity metrics into TPM PCR7/PCR4 and unsealing keys, with SRTM and DRTM variants described in the spec — maps onto Intel's shipping Trusted Execution Technology (TXT) measured-launch architecture and TXT-capable chipsets/firmware. The specification itself cites SRTM/DRTM, Intel ICH6 hide registers, and Intel chipset datasheets as implementation vehicles. (Note: this is a technology-mapping statement, not a claim-by-claim infringement/product analysis.)
• Current status: Operating. Intel remains a publicly traded company (NASDAQ: INTC). It is not acquired, dissolved, or in bankruptcy. It is, however, operating under cost-reduction programs — the 2024 Restructuring Plan and the 2025 Restructuring Plan — as defined in its own Form 10-K, and in 2025 took a U.S. Department of Commerce CHIPS Act "Secure Enclave" investment involving escrowed Intel shares. None of this has produced an assignment of this patent.
• Domestic/family status: US asset Active with full maintenance-fee compliance. The foreign family largely lapsed: EP1906333B1 listed Not-in-force, CN101154256B Expired – Fee Related, KR100989977B1 Expired – Fee Related. The continuation/divisional US 9,235,707 (app. 13/963,803, filed 2013-08-09) remains Active and is also Intel-owned.

Assignment timeline

One recorded assignment in the entire chain.

• 2006-11-06 / 2006-11-29 (executed) / recorded 2008-04-14 — Reel 020820/0566
  • Conveyance: Assignment — ASSIGNMENT OF ASSIGNORS INTEREST (original, not a post-issuance transfer)
  • Assignor: Vincent J. Zimmer and Lyle Cool (joint inventors)
  • Assignee: Intel Corporation, Delaware
  • Correspondent: ⚠️ Not determinable from the sources retrieved. The USPTO record for reel 020820/0566 lists the assignors, assignee, execution dates, and reel/frame, but the correspondent of record (recording attorney/firm) is not exposed in the Google Patents legal-events rendering or in the search results I was able to retrieve. I will not guess this field. To capture it you need the USPTO Patent Assignment Center abstract for reel 020820 frame 0566 itself. Because the chain contains only this single instrument, the "repeat correspondent" signal cannot be evaluated at all — there is no recurrence to observe.
  • Context: Inline employee-invention assignment to the operating employer; the multi-month gap between execution and recording reflects late perfection of chain of title, not a transfer of ownership between unrelated parties.

No further assignments, security interests, mergers, name changes, licenses, or releases are recorded against this patent. Specifically, no post-issuance conveyor events exist at all — the only non-assignment legal events are fee payments and the grant notice:

The 12th-year payment on 2025-01-06 is affirmative evidence Intel retained ownership and valued the asset as recently as ~9 months ago.

Implication of an empty post-issuance chain: the original assignee (Intel) still owns the patent. This is a complete finding in itself and forecloses every NPE transfer-based signal below.

Timeline diagram

timeline
    title Ownership of US 8510859
    2006 : Application filed by Zimmer and Cool
         : Inventors assign rights to Intel
    2008 : Assignment recorded reel 020820 frame 0566
    2013 : Patent issued to Intel Corporation
         : Intel files divisional US 9235707
    2021 : Intel pays 8th year maintenance fee
    2025 : Intel pays 12th year maintenance fee

NPE / troll-pattern signals

Verdict

Insufficient data — the chain consists solely of the original assignment, with no post-issuance records.

Per the taxonomy, a chain containing only the original instrument falls into "Insufficient data," and that is the literal and honest mapping here: the sole record is reel 020820/0566 (inventors Zimmer and Cool → Intel Corporation, executed 2006-11-06/2006-11-29, recorded 2008-04-14). I want to be explicit that this is not a null or adverse finding — the affirmative evidence is that Intel Corporation has owned this patent continuously since 2006, paid every maintenance fee including the 12th-year fee on 2025-01-06, and kept both the parent (US 8,510,859) and the divisional (US 9,235,707) alive. There is therefore no NPE chain to report, no shell entity, no asserter, and no litigation involving this patent. The one unresolved item is the correspondent of record on reel 020820/0566, which I could not retrieve and will not invent; pull the Patent Assignment Center abstract directly to close that gap.

Verification links:

• USPTO Assignment Center: https://assignmentcenter.uspto.gov/
• USPTO Patent Assignment Search (indexed): https://assignment.uspto.gov/patent/index.html — search patent number 8510859; confirm the single hit at reel 020820/0566
• Google Patents legal events: https://patents.google.com/patent/US8510859/en#legalEvents
• Related divisional (same chain): https://patents.google.com/patent/US9235707/en

I'll search for this specific patent on USPTO and verify the prior-art citations before analyzing them.

Let me verify the two most on-point cited references (the Intel co-assigned ones) and the closest non-patent citation before analyzing.

Let me resolve one bibliographic conflict I found between the front page and the citation table, and confirm the two foreign references.

Prior-Art Analysis — US 8,510,859 B2

1. Record confirmation (USPTO / 8510859)

I located the record for US 8,510,859 B2 (not similarly-numbered US 8,509,859, 8,523,085, etc.). Confirmed attributes:

Sources: the USPTO-hosted publication of the patent (https://patentimages.storage.googleapis.com/06/3d/be/7fb2474fcccfa7/US8510859.pdf) and the Google Patents record (https://patents.google.com/patent/US8510859/en), which mirrors the USPTO bibliographic data. Claim 1 recites, in substance: (a) configuring a first runtime environment — including executing a hardware partition manager; (b) verifying, by a TPM (which itself measures) current vs. trusted integrity metrics; (c) decrypting protected content in response; and (d) launching a second, co-existing runtime environment only after that verification, again TPM-measured.

⚠️ Record discrepancies I must flag (not auto-corrected)

Per your strict rule, I am reporting the identifiers literally rather than silently reconciling them:

1. The patent's own front page ("References Cited") lists US 7,543,288 B2 (Luk et al., class 717/153), whereas the Google Patents structured citation table lists US 7,543,283 B2 — "Flexible instruction processor systems and methods" (Imperial College Innovations). These are two different six-figure numbers and titles. My attempt to resolve which was actually cited was cut off by the tool step limit, so I present both and mark it unresolved. (Note: both issued June 2009, which may explain the conflation.)
2. The Google table lists US 2005/0210467 A1 (Zimmer), while the front-page OCR shows 2005/0121467 A1 (Zimmer, 9/2005). Same inventor, publication month, and subject matter; I treat these as the same citation but preserve the literal variants.
3. Several foreign citations post-date the 2006-09-26 critical date by publication (see §3), so their §102 status is date-sensitive.

2. The 14 patent citations of US 8,510,859 — reference-by-reference

For each: full citation, date, description, and my §102 assessment against claim 1 and claim 10. Threshold: anticipation requires a single reference to disclose every limitation, arranged as claimed. None of the references below is a "knock-out" single-reference anticipation of claim 1 or 10; the two strongest (Goud; Zimmer) are the ones that map to the most claim elements and are discussed in detail.

Net result for the 14 patent citations: none of them, alone, anticipates claim 1 or claim 10. The two Intel co-assigned references — Goud (US 7,222,062 / US 2005/0138370) and Zimmer (US 7,552,419 / US 2005/0210467) — are the only ones that map to a majority of the limitations, and even they are missing at least (i) the hardware partition manager (vs. a VMM), and (ii) the "launch second after verifying first" ordering. Their proper role is §103.

3. The non-patent citations (11)

Only one is substantive prior art; the other ten are prosecution correspondence in the foreign counterparts (not prior art):

1. Stefan Berger, Ramón Cáceres, Kenneth A. Goldman, Ronald Perez, Reiner Sailer, Leendert van Doorn, "vTPM: Virtualizing the Trusted Platform Module," IBM Research Report RC23879, Feb. 14, 2006, pp. 1–18 (also published at USENIX Security Symposium 2006, 2006-07-31; https://dominoweb.draco.res.ibm.com/reports/rc23879.pdf).

• Description: Full software TPM virtualized inside a hypervisor, giving every VM its own vTPM; PCR-extend operation Extend(PCR_N, value) = SHA1(PCR_N ‖ value); sealing data so it can only be decrypted when selected PCRs are in the exact sealed state; remote attestation; vTPM suspend/resume/migration; certificate chains linking vTPM to hardware TPM.
• §102 assessment: The RC23879 report (2006-02-14) predates the 2006-09-26 filing, so it is a printed publication under §102(a)/(b). It squarely discloses TPM integrity metrics, PCR extension, and sealing a key to the measured state — the core of the claim 1 / claim 10 "verify by TPM, then decrypt protected content" mechanism — but it does so through a hypervisor/VMM and for VMs, not through a hardware partition manager configuring distinct coexisting environments in a defined launch order. Does not anticipate claim 1 or 10; very strong §103 art (the strongest single non-patent reference, and the most on-point of all the citations).

2–11. Office Actions, Search Reports, and Letters Patent from EP 07253768.1, CN 200710153796.4, and KR 10-2007-0097608 (2009–2012). These are procedural prosecution documents for the same family; they are not prior art and have no §102 relevance.

4. What the strongest §102/§103 case actually looks like

• No single reference anticipates claim 1 or claim 10. The distinguishing combination is (a) partitioning done by a hardware partition manager (firmware or processor microcode — the spec's SRTM partition manager 180 / DRTM partition manager 159), plus (d) the ordered launch in which the second coexisting environment is brought up only after the first is TPM-verified and its protected content decrypted. Every candidate reference uses a VMM/hypervisor as the partitioning agent and does not teach that ordering.
• Strongest §102 candidates (still falling short): Goud (US 7,222,062) — per-environment key gated by an integrity hash, but emulated TPM and no launch ordering; and the vTPM paper (Berger et al., 2006-02-14) — hardware-TPM PCR extension/sealing, but hypervisor-based.
• Most natural §103 combination: Goud (US 2005/0138370 / US 7,222,062) for "multiple operational environments each with a TPM-held key gated by an integrity measurement," + Zimmer (US 2005/0210467 / US 7,552,419) for "measuring platform configuration and seal/unseal on hash match across environments," + the vTPM paper for TPM PCR-extension/sealing mechanics — against the ordered, hardware-partition-manager launch of claim 1. Whether that combination renders claim 1 obvious turns on whether a POSITA would have been motivated to move partitioning from the VMM down into firmware/microcode and to serialize the embedded-then-main launch, which is precisely the point the specification frames as its advance over VMM-based partitioning (see the '859 Background re: the 8-core VMM limit).

5. Caveats and open items

• Identifier conflicts (§1.1–1.2) are unresolved because my verification step hit the tool limit. Per your strict no-auto-correct rule, I have preserved both candidate identifiers (US 7,543,288 vs US 7,543,283; US 2005/0210467 vs 2005/0121467) rather than picking one. Confirm against the paper copy before relying on either.
• Critical-date sensitivity (§3, JP citations): JP 2006-323814 A (pub. 2006-11-30) and JP 2007-257197 A (pub. 2007-10-04) were published after the 2006-09-26 filing date; their prior-art effect, if any, runs through their earlier-filed US counterparts (e.g., US 7,725,703, US priority 2005-01-07) under §102(e), not through the foreign publication dates. I could not verify a US counterpart for JP 2007-257197 (Fujitsu) within the tool budget.
• Scope of the "citations" list: The IPR-style refresh citations and later third-party citations (e.g., the Amazon, Bitdefender, and NSA patents shown on the Google page as citing the '859) are forward citations — i.e., art that came after the '859 — and are therefore not §102 prior art against it. I excluded them by design.
• Claim-language note (carried over from the earlier section): claim 1 mixes "trusted platform module" and "trust platform module"; I have not altered this, and it does not change the analysis (both plainly refer to the TPM).
• No litigation/PTAB/CAFC record for US 8,510,859 was found earlier; consequently there is no adjudicated invalidity record to cross-check these §102 assessments against. These are my analyst opinions, not legal conclusions.

I'll ground the obviousness analysis by pulling details on the most relevant cited references, then build the §103 combinations.

Excellent — the EP search report is a key finding. Let me pull the vTPM non-patent reference and the Microsoft/Scarlata references to complete the combination analysis.

Obviousness Analysis — U.S. Patent No. 8,510,859 B2

Under 35 U.S.C. § 103 (pre-AIA, given the 2006‑09‑26 priority date)

Framing. This is a technical/analytical opinion on the prior-art record, not a legal conclusion. Obviousness is ultimately a question of law decided on Graham factors (scope/content of art, differences, PHOSITA level, secondary considerations) as refined by KSR Int'l v. Teleflex, 550 U.S. 398 (2007). Everything below is grounded in the prior-art list on the patent page ("Citations (14)" + 11 non-patent citations), the EP family search report, and reference details I retrieved.

1. The invention (for §103 purposes)

Independent claim 1 is a 4-step method, and independent claim 10 is the same idea in non-transitory medium form. Per the prior analysis, the two concepts that arguably carry the weight are:

Dependent claims add: assign and hide resources (2, 12); trusted channel into first env. (3); PCR7 extension (4, 13); key-then-content decryption (5); second env.'s own configure/verify/decrypt (6); release resource control to the second env.'s OS (7); main env., hash into PCR4 (8, 14); another embedded env., hash into PCR7 (9, 15).

The critical admission is in the patent's own Background: "A current solution is to launch a protected core managed by the firmware and then launch and secure additional partitions via the VMM." The patent also states the problem it targets: a single TPM/protected core is insufficient; the VMM can't scale past ~8 cores; and VMM-based security is only as good as the VMM. Those admissions frame the art.

2. Level of ordinary skill (PHOSITA)

A person of ordinary skill as of Sept. 2006 would have: (i) a B.S. in CS/EE plus ~2–4 years in platform firmware/OS security, or equivalent; and (ii) working familiarity with the TCG TPM architecture (PCRs, sealing/binding, measured launch, the CRTM chain of trust), virtualization/hypervisors (VMM, VM isolation), and platform firmware (BIOS/EFI/UEFI, SMM, ACPI). This is the level the patent's own disclosure assumes.

3. Principal prior-art references

Two evidentiary anchors worth stressing:

1. The EP search report for the same family (EP1906333A3) rates US 2005/210467 (Zimmer) as "X" — highly relevant, novelty‑destroying — against claims 1–15 with the notation "the whole document." A foreign counterpart examiner considered the Zimmer reference to disclose the core of all 15 claims.
2. Zimmer ’467 and Goud ’370 are co‑assigned to Intel with the ’859 patent, and the Scarlata references are Intel art — a fact that bears on motivation to combine (a common assignee solving a common platform-security problem).

4. Combination analysis

4.1 Primary combination — renders claims 1 and 10 obvious

Primary: Zimmer ’467 (US 2005/0210467) + Goud ’370 (US 7,222,062) + Berger vTPM + TCG TPM Spec.

KSR rationales that apply:

• (A) Known elements, known methods → predictable result. Multi‑environment platform (Zimmer) + TPM‑based measurement/sealing (Goud/Berger/TCG) yields the expected result of a per‑environment trust gate.
• (D) Known technique applied to a known, improvement‑ready device. The Background itself identifies the unmet need (single protected core insufficient; VMM‑only security inadequate) — an express design incentive.
• (F) Market/design forces. Premium‑content DRM and platform manageability (set‑top‑box / PVR "vet‑for‑premium‑content" use case in the spec) push toward isolating critical code from the general‑purpose OS.
• Common ownership (Intel) further supports the combination as between Zimmer ’467, Goud ’370, and the Scarlata references.

4.2 Secondary/alternative combination — reinforces claims 1 & 10

Zimmer ’467 + US 2006/0026418 (IBM multi‑tiered trust) + Scarlata ’719/’106 (per‑VM vTPM + seal‑to‑PCR). The Scarlata references supply the express recognition of the exact problem the ’859 patent addresses ("only one software environment at a time") and the per‑VM virtual‑TPM measurement/sealing mechanism — making the leap from Zimmer’s shared TPM to per‑environment TPM gating even smaller.

4.3 Where the primary combination is imperfect (genuine §103 battleground)

• "Hardware partition manager" (A) is not a term of art in the cited art. No single reference uses it. The ’859 patent distinguishes its partition manager (firmware 180 / microcode 159; SRTM/DRTM) from a software VMM hypervisor — and the Background criticizes VMM‑only partitioning. The obviousness case therefore depends on treating Zimmer’s EFI‑firmware‑resident VMM (expressly disclosed) as within the claim’s "hardware partition manager," or on the general firmware‑based protected‑core launch that the Background concedes. This is the strongest non‑obviousness argument: that the recited execution of a hardware partition manager to configure the first environment is what differentiates the claim, and that a POSITA would not equate a firmware‑EFI VMM with a hardware/firmware partition manager absent the reference’s clear teaching.
• The strict ordering (D) — "launching a second runtime environment after the verification" — is arguably a design choice rather than a technical requirement, but a patentee could argue the art discloses concurrent launch (Zimmer: VMs operating simultaneously) and never a mandatory verify‑then‑launch sequence.

Net: the order/architecture limitations are the only credible non‑obviousness footholds; every other limitation is squarely in the art.

5. Dependent-claim analysis (would also fall with the primary combination)

6. Evidence-quality notes and caveats

• The EP X‑citation is the strongest single evidentiary data point. The EP1906333 search report marks US 2005/210467 (Zimmer) "X… the whole document," claims 1–15. That is a foreign‑counterpart examiner on this exact family treating one reference as covering all granted claims — highly probative that a §103 rejection built on Zimmer ’467 plus a TPM‑measurement/sealing reference would be reached.
• The ’859 Background is self‑defeating on several points (firmware‑managed core + additional partitions; establishing trust before OS boot). These are admissions usable against the claims.
• Effective‑date hygiene. Zimmer ’467 (pub. 2005‑09‑22) and Goud ’370 (pub. 2005‑06‑23) are §102(b) art. Berger vTPM (2006‑02‑14) and the TCG 1.2 spec (2006‑03‑29) are §102(a) art. The Scarlata references (US 2007/0094719A1; US 2006/0256106A1) published after the ’859 filing and are therefore §102(e) art at best (relying on their 2005‑05‑13 provisional / 2005‑06‑29 filings) — usable against claim 1 but with effective‑date scrutiny required. The JP‑Microsoft reference is a foreign publication dated after the ’859 filing and should be used only via any U.S. counterpart (uncertain on this record).
• No litigation / no secondary-consideration signal found. Per the earlier sections, no district‑court/PTAB/CAFC activity for US 8,510,859 was located, and the patent has stayed with Intel — so there is no evidence of unexpected results, commercial success, long‑felt need, or industry praise to rebut an obviousness finding. (Absence of evidence, not proof.)
• Reference‑detail limitation. My element mappings for Goud ’370, Berger, and the Scarlata references are drawn from their abstracts/specification excerpts and the patent page's citation list; I did not read every drawing/embodiment, so treat the mappings as strong‑but‑not‑exhaustive.
• Contradiction check vs. earlier sections. Consistent: the earlier summary flagged the claim‑1 phrase "trust platform module" vs "trusted platform module." I treat the recited module as the TPM recited elsewhere; the prior art (Zimmer/Goud/TCG/Berger) is all TPM‑based, so the drafting inconsistency does not change the §103 picture. No other contradictions found.

7. Bottom line

On the record of this page, claims 1 and 10 would very likely be held obvious over Zimmer ’467 (US 2005/0210467) in view of Goud ’370 (US 7,222,062) and the TCG TPM specification, optionally with Berger’s vTPM — with KSR rationales (predictable combination of known elements; known technique applied to an improvement‑ready platform; strong design/market incentives) supplying the motivation. The only meaningful non‑obviousness argument the patentee retains is that the cited art does not expressly teach obtaining the partitioning by "executing a hardware partition manager" (versus a software hypervisor) and does not mandate the verify‑first‑then‑launch‑second ordering; both are arguably design choices, but the "hardware partition manager" element is the claim term a competent challenger must squarely meet.

This is a technical analysis of the written record, not a legal opinion or a substitute for an examiner's rejection or a court's determination.