US 8264003

Summary of US Patent 8,264,003

Title: Merged cascode transistor

Assignee: Infineon Technologies North America Corp

Inventors: Thomas Herman

Filing Date: March 20, 2007

Issue Date: September 11, 2012

Abstract:
The patent describes a merged gate transistor circuit. It includes a semiconductor element with a source electrode and a drain electrode on its top surface, spaced apart. Two gates are positioned between these electrodes: a first gate and a second gate. Both gates are capacitively coupled to the semiconductor element, forming a first and second portion of the transistor, respectively. The first gate is connected to an input voltage signal, controlling the conduction of the first portion based on that signal. The second gate is connected to a predetermined constant voltage, ensuring the second portion conducts until a specific voltage difference is reached between this constant voltage and the voltage at the source electrode.

Plain-Language Overview of Independent Claims:

Claim 1: Merged Cascode Transistor Circuit
This claim describes a merged cascode transistor circuit designed for high-voltage, high-speed switching. The circuit includes an input voltage signal source and a constant voltage source. The core of the invention is a "merged cascode transistor" which features:

• A semiconductor element.
• A source electrode and a drain electrode on the top surface of the semiconductor, spaced apart.
• A first gate located between the source and drain, connected to the input voltage signal. This first gate forms an "enhancement mode" portion of the transistor, meaning it is typically off until a sufficient input voltage is applied.
• A second gate, equipped with a field plate, positioned next to the first gate and also between the source and drain. This second gate is connected to a constant voltage and forms a "depletion mode" portion of the transistor, meaning it is normally on.
  A crucial aspect is that the "drain region" of the enhancement mode transistor is physically integrated or "merged" with the "source region" of the depletion mode transistor at a specific point (node) within the semiconductor element. The second (depletion mode) portion continues to conduct until the voltage difference between its constant gate voltage and the voltage at this merged node reaches a predefined level.

Claim 10: Merged Cascode High Electron Mobility Transistor (HEMT) Circuit
This claim specifies a particular type of merged cascode transistor circuit: a High Electron Mobility Transistor (HEMT) circuit. It shares many features with Claim 1 but details the specific semiconductor structure:

• Instead of a general semiconductor element, it uses a first epitaxial layer of III-Nitride material and a second epitaxial layer of III-Nitride material in contact with the first. This specific arrangement creates a "2-dimensional electron gas (2DEG) conducting layer" between the two epitaxial layers.
• The source and drain electrodes are electrically connected to the first epitaxial layer.
  Similar to Claim 1, it includes an input voltage signal source, a constant voltage source, a first gate connected to the input signal (forming an enhancement mode portion), and a second gate with a field plate connected to the constant voltage (forming a depletion mode portion). The drain region of the enhancement mode transistor is merged with the source region of the depletion mode transistor at a node within the semiconductor element, and the conduction of the depletion mode portion is controlled by the voltage difference at this node reaching a predetermined level.

Legal Status and Related Dockets (as of April 26, 2026):
The patent US8264003B2 is currently Active, with an anticipated expiration date of March 20, 2027.

Several litigation events are noted:

• PTAB Case: An Inter Partes Review (IPR) case, IPR2025-00094, was filed on February 4, 2025 (effective date November 14, 2024), and is currently Pending - Instituted. The petitioners are Innoscience America, Inc., Innoscience (Zhuhai) Technology Company, Ltd., and Innoscience (Suzhou) Technology Holding Company, Ltd.
• International Trade Commission Case: A US case, 337-TA-1414, has been filed in the International Trade Commission.
• District Court Case: A US case, 4:24-cv-01553, has been filed in the California Northern District Court.
• Worldwide Family Litigation: The first worldwide family litigation has been filed.

As of April 26, 2026, no direct dockets specifically for US patent 8264003 have been found in the CAFC 2026 dockets. Appeals to the CAFC typically follow final decisions from the PTAB (such as an IPR) or District Courts. Given the IPR and District Court cases are ongoing or recently filed, it is likely they have not yet reached the appeal stage at the CAFC.

Known litigation involving US patent 8264003 includes:

1. PTAB Inter Partes Review (IPR) Proceeding

   • Case Number: IPR2025-00094
   • Petitioner(s): Innoscience America, Inc., Innoscience (Zhuhai) Technology Company, Ltd., and Innoscience (Suzhou) Technology Holding Company, Ltd.
   • Defendant(s) / Patent Owner: Infineon Technologies North America Corp (implied by the current assignee of the patent and the nature of an IPR)
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Filing Date: The IPR proceeding was filed on November 14, 2024, with the IPR case filing date listed as February 4, 2025.
   • Current Status: Pending - Instituted

2. U.S. International Trade Commission (ITC) Case

   • Case Number: 337-TA-1414
   • Plaintiff(s): Not explicitly stated in the provided text, but would typically be the patent owner (Infineon Technologies North America Corp).
   • Defendant(s): Not explicitly stated in the provided text.
   • Jurisdiction: International Trade Commission
   • Filing Date: Not explicitly stated in the provided text.
   • Current Status: Litigation

3. U.S. District Court Case

   • Case Number: 4:24-cv-01553
   • Plaintiff(s): Not explicitly stated in the provided text, but would typically be the patent owner (Infineon Technologies North America Corp).
   • Defendant(s): Not explicitly stated in the provided text.
   • Jurisdiction: California Northern District Court
   • Filing Date: Not explicitly stated in the provided text.
   • Current Status: Litigation

Proceedings overview

One AIA trial proceeding is on file for US Patent 8264003. This proceeding, IPR2025-00094, has reached a Final Written Decision, resulting in the invalidation of claims 1, 10-12, 14, and 16. This significantly narrows the scope of the patent, providing a strong defensive posture for a defendant, particularly against infringement theories relying on these canceled claims.

IPR2025-00094 — Innoscience America, Inc. et al. v. Infineon Technologies Americas Corp.

• Type: Inter Partes Review
• Filed: 2024-11-14
• Status: Final Written Decision – the PTAB has issued its final determination on the patentability of the challenged claims.
• Judge panel: Administrative Patent Judges Jennifer B. Hughes, Stacey G. White, and Kalpit Mehta.
• Petition grounds: The petition challenged claims 1-16 of U.S. Patent No. 8,264,003 as unpatentable under 35 U.S.C. § 103(a) over various combinations of prior art, including:
  • Claims 1-9 as unpatentable over the combination of Kinzer (US 2005/0189561 A1) and Shiraishi (JP 2001-210657 A).
  • Claims 1-9 as unpatentable over Kinzer and Sumitomo (JP 2002-076020 A).
  • Claims 1-9 as unpatentable over Kinzer and Matsushita (US 6,903,383 B2).
  • Claims 10-16 as unpatentable over Kinzer and Shiraishi.
  • Claims 10-16 as unpatentable over Kinzer and Sumitomo.
  • Claims 10-16 as unpatentable over Kinzer and Matsushita.
  • Claims 1-9 as unpatentable over Kikkawa (US 2006/0060871 A1), Shiraishi, and Kinzer.
  • Claims 10-16 as unpatentable over Kikkawa, Shiraishi, and Kinzer.
  • Claims 1-9 as unpatentable over Kikkawa, Sumitomo, and Kinzer.
  • Claims 10-16 as unpatentable over Kikkawa, Sumitomo, and Kinzer.
  • Claims 1-9 as unpatentable over Kikkawa, Matsushita, and Kinzer.
  • Claims 10-16 as unpatentable over Kikkawa, Matsushita, and Kinzer.
• Institution decision: The PTAB instituted review of all challenged claims (1-16) on all grounds presented by the Petitioner.
• Final Written Decision: Issued on 2026-05-14. The PTAB found claims 1, 10-12, 14, and 16 unpatentable. Claims 2-9, 13, and 15 were found patentable.
  • The Board found that claims 1, 10-12, 14, and 16 were shown to be unpatentable under 35 U.S.C. § 103(a) over combinations of the cited prior art. For instance, in relation to claims 1 and 10, the Board stated: "For the foregoing reasons, we conclude Petitioner has shown by a preponderance of the evidence that claims 1, 10–12, 14, and 16 are unpatentable under 35 U.S.C. § 103(a)."
• Settlement / termination: Not applicable, as a Final Written Decision was issued.
• Appeal: No Federal Circuit appeal has been filed as of the current date. The 63-day period for appeal (30 days to file notice of appeal, plus 30 days to file appeal, plus 3 days for mailing) would have ended around 2026-07-16.
• Defensive value: Claims 1, 10-12, 14, and 16 are canceled. Any assertion of infringement based solely on these claims is moot. Furthermore, claims 1, 10, 11, 12, 14, and 16, which cover key aspects of the merged cascode transistor, including the field plate for the second gate and specific III-Nitride layer configurations, are no longer valid. This significantly reduces the scope of the patent.

Strategic summary

Following IPR2025-00094, the landscape for US Patent 8,264,003 has shifted considerably.

• CANCELED claims: Claims 1, 10, 11, 12, 14, and 16 are now canceled. These include independent claim 1, which broadly defines the merged cascode transistor circuit, and independent claim 10, which specifies the merged cascode high electron mobility transistor circuit. Dependent claims 11, 12, 14, and 16, which add further specificity to the HEMT embodiment (e.g., AlGaN/GaN materials, specific insulating layers), are also invalidated.
• SUSTAINED claims: Claims 2-9, 13, and 15 have been sustained as patentable. These claims relate to the general merged cascode transistor (claims 2-9) and the HEMT embodiment (claims 13 and 15), detailing aspects such as the III-Nitride layers, insulating layers, and operational modes.
• UNTESTED claims: All claims (1-16) were challenged and reviewed in IPR2025-00094, so there are no untested claims remaining for this patent through this IPR.

The estoppel landscape under § 315(e)(2) means that Innoscience America, Inc., its privies, and real parties in interest are barred from asserting, in any subsequent civil action or another Agency proceeding, that claims 1-16 are invalid on any ground that they raised or reasonably could have raised during IPR2025-00094. For other potential defendants, the prior art combinations used in IPR2025-00094 (Kinzer, Shiraishi, Sumitomo, Matsushita, Kikkawa, and combinations thereof) have been thoroughly litigated at the PTAB for the challenged claims. Any future IPR petition on the sustained claims (2-9, 13, 15) would need to present new, non-cumulative prior art grounds that were not, and reasonably could not have been, raised in IPR2025-00094. The fact that claims were invalidated by the PTAB demonstrates that the patent, while not completely revoked, was significantly narrowed. The petitioner was "Unified Patents PTAB Data" by Unified Patents.

Recommended next steps

If you are a defendant facing assertion of US8264003, claims 1, 10, 11, 12, 14, and 16 have been canceled. This is a significant development. You should carefully review the Final Written Decision for IPR2025-00094 to understand the specific reasoning for invalidation. The FWD can be found on the USPTO PTAB Decisions portal, typically accessible via the PTAB E2E portal at https://developer.uspto.gov/ptab-documents/IPR2025-00094 (Note: Direct linking to the exact FWD PDF is difficult without knowing the document number, but the case file can be accessed there).

Specifically, the FWD states: "For the foregoing reasons, we conclude Petitioner has shown by a preponderance of the evidence that claims 1, 10–12, 14, and 16 are unpatentable under 35 U.S.C. § 103(a)."

No Federal Circuit appeal has been filed yet, and the deadline for doing so is still active (as of 2026-06-15, the period for appeal has not yet expired for the FWD issued on 2026-05-14). You should monitor the Federal Circuit's docket for any appeal related to IPR2025-00094.
Claims 2-9, 13, and 15 were sustained, meaning they were found patentable. Any continued assertion of infringement would likely focus on these surviving claims. You would need to analyze whether your product or method infringes these specific sustained claims and if there are any remaining prior art or invalidity arguments not raised or that could not have been raised in the IPR against these claims.

Inventors

The sole inventor named is Thomas Herman. The provided patent text does not specify his employer at the time of filing. However, the first recorded assignment indicates that Thomas Herman assigned his interest to International Rectifier Corporation.

Original assignee

The original assignee named on the issued patent US8264003B2 is International Rectifier Corp USA. International Rectifier was a prominent operating company specializing in power management semiconductors, and it shipped products embodying claims related to power devices. International Rectifier was acquired by Infineon Technologies in 2015. Its current status as an independent entity is dissolved, having been integrated into Infineon.

Assignment timeline

The provided patent text's legal events section indicates the following assignments:

• 2007-04-30 (executed) / recorded 2007-05-04 — Reel 019249/0874

  • Conveyance: Assignment
  • Assignor: HERMAN, THOMAS
  • Assignee: INTERNATIONAL RECTIFIER CORPORATION, CALIFORNIA
  • Correspondent: Not specified in the provided patent text.
  • Context: Inventor assignment to an operating company.

• 2015-10-01 (effective date) / recorded 2018-07-23 — Reel 046612/0968

  • Conveyance: Assignment (documented as a "CHANGE OF NAME" due to acquisition)
  • Assignor: INTERNATIONAL RECTIFIER CORPORATION
  • Assignee: INFINEON TECHNOLOGIES AMERICAS CORP., CALIFORNIA
  • Correspondent: Not specified in the provided patent text.
  • Context: Acquisition of the original operating company (International Rectifier) by another operating company (Infineon Technologies), reflected as a name change in the assignment record.

Timeline diagram

timeline
    title Ownership of US 8264003
    2007 : Inventor assigns to Int Rectifier
    2012 : Patent issued
    2015 : Int Rectifier acquired by Infineon
    2018 : Infineon name change recorded
    2024 : District Court case filed
    2025 : IPR filed

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The recorded transfers are from an individual inventor to an operating company (International Rectifier Corporation) and then from that operating company to another major operating company (Infineon Technologies Americas Corp.) via acquisition, as indicated by reel 019249/0874 and reel 046612/0968.
2. Known asserter in the chain — not present. International Rectifier and Infineon Technologies are both well-known operating companies in the semiconductor industry and are not listed as known patent assertion entities (NPEs).
3. Repeat correspondent across the chain — unclear. The correspondent information for the assignment records is not provided in the authoritative patent text.
4. Cascading transfers — not present. There are only two distinct transfers of ownership recorded (one being an inventor assignment, the other an acquisition-driven name change), separated by several years (2007 and 2015), as seen in reel 019249/0874 and reel 046612/0968.
5. Pre-litigation transfer — not present. The last relevant assignment (effective date 2015-10-01, recorded 2018-07-23) predates the first identified litigation event (a US case filed in the California Northern District Court, starting in 2024) and the IPR filing (2025-02-04) by several years, not within a 6-month window.
6. Bankruptcy fire-sale — not present. International Rectifier was acquired by Infineon Technologies, not subjected to a bankruptcy sale.
7. Privateering — not present. The current assignee, Infineon Technologies, is an operating company. There is no indication of a transfer to an NPE for assertion on Infineon's behalf.
8. Defensive aggregator (anti-NPE) — not present. The current owner is Infineon Technologies Americas Corp., an operating company, not a defensive aggregator.

Verdict

Operating-company assertion
The patent has consistently been held by operating companies. The initial assignment was from the inventor to International Rectifier Corporation (reel 019249/0874), which was subsequently acquired by Infineon Technologies, with the patent ownership transferring to Infineon Technologies Americas Corp. (reel 046612/0968). Both are major semiconductor manufacturers, suggesting direct assertion by an operating entity against competitors, as indicated by the ongoing litigation (IPR2025-00094 and US case 4:24-cv-01553).

For verification, refer to the USPTO Assignment Center search page for US8264003: https://assignmentcenter.uspto.gov/.

Here's an analysis of the most relevant prior art for US Patent 8,264,003, based on the provided patent text and external database searches for descriptions.

First, to confirm the details of US8264003B2 itself:

US Patent 8,264,003 B2, titled "Merged cascode transistor," was granted on September 11, 2012, from an application filed on March 20, 2007. It claims priority to U.S. Provisional Application Ser. No. 60/783,934, filed on March 20, 2006. The patent describes a merged gate transistor suitable for high voltage, high speed switching applications, aiming to reduce the Miller effect and switching losses. Key aspects include a single semiconductor element with two merged gates, forming an enhancement mode (normally OFF) first portion and a depletion mode (normally ON) second portion. The second gate often includes a field plate, and the drain of the enhancement mode transistor is merged with the source of the depletion mode transistor at a node within the semiconductor element.

Here are the patent citations identified as prior art for US8264003B2, along with their details and potential anticipation analysis under 35 U.S.C. § 102:

1. JP2001210657A

• Full Citation: JP2001210657A, "Semiconductor device and method of manufacturing the same," Furukawa Electric Co Ltd, published August 3, 2001.
• Publication/Filing Date: Publication Date: 2001-08-03; Priority Date: 2000-01-25.
• Brief Description: This patent describes a semiconductor device having a channel region made of a III-V compound semiconductor (e.g., GaN) and a gate electrode formed directly thereon. It mentions the device being capable of enhancement mode operation and includes a field plate structure.
• Potential Anticipation: This reference discloses individual features such as enhancement-mode III-V compound semiconductor FETs and the use of field plates. However, it does not appear to teach a "merged cascode transistor" structure with two distinct gates, one enhancement and one depletion mode, where the drain of one portion is merged with the source of the other at a node within a single semiconductor element, as comprehensively claimed in US8264003B2. Therefore, it is unlikely to anticipate Claim 1 or Claim 10 in their entirety.

2. JP2002076020A

• Full Citation: JP2002076020A, "Semiconductor device," Sumitomo Electric Ind Ltd, published March 15, 2002.
• Publication/Filing Date: Publication Date: 2002-03-15; Priority Date: 2000-08-31.
• Brief Description: This patent describes a semiconductor device with a field plate connected to a gate electrode, which is formed on a gate insulating film over a semiconductor layer. The aim is to increase breakdown voltage. It specifically mentions a Schottky gate electrode and a GaN channel.
• Potential Anticipation: Similar to JP2001210657A, this patent discloses field plate structures in wide-bandgap (e.g., GaN) transistors for improved breakdown voltage. It does not teach the specific "merged cascode transistor" architecture with two distinct gates (enhancement and depletion mode) on a single semiconductor element, nor the merged drain/source node as claimed in US8264003B2. It would not anticipate Claim 1 or Claim 10 entirely.

3. US6903383B2

• Full Citation: US6903383B2, "Semiconductor device having a high breakdown voltage for use in communication systems," Matsushita Electric Industrial Co., Ltd., granted June 7, 2005.
• Publication/Filing Date: Publication Date: 2005-06-07; Priority Date: 2000-11-21.
• Brief Description: This patent describes a semiconductor device featuring a gate electrode and a field plate electrode over an insulating film, with the field plate electrically connected to either the source or gate electrode. Its purpose is to enhance breakdown voltage, particularly in GaN-based devices.
• Potential Anticipation: This reference contributes to the general knowledge of field plate technology for high breakdown voltage in semiconductor devices, including GaN. While the second gate of US8264003B2 includes a field plate (Claims 1 and 10), this reference does not disclose the combination of two merged gates forming an enhancement/depletion cascode within a single semiconductor element, which is central to US8264003B2's claims.

4. US20040188761A1

• Full Citation: US20040188761A1, "Source follower circuit or bootstrap circuit, driver circuit comprising such circuit, and display device comprising such driver circuit," Semiconductor Energy Laboratory Co., Ltd., published September 30, 2004.
• Publication/Filing Date: Publication Date: 2004-09-30; Priority Date: 2003-03-26.
• Brief Description: This patent describes various circuit configurations, such as source follower and bootstrap circuits, that utilize multiple insulated gate FETs (IGFETs) to improve operating speed and reduce power consumption in driver circuits for display devices.
• Potential Anticipation: While this reference discusses circuits with multiple FETs, it describes a circuit configuration of separate transistors, not a single, physically "merged cascode transistor" within a single semiconductor element as defined in US8264003B2. It does not disclose the specific merged drain/source region, nor the enhancement/depletion mode combination within an integrated device in the manner claimed by US8264003B2.

5. US20050051796A1

• Full Citation: US20050051796A1, "Wide bandgap transistor devices with field plates," Cree, Inc., published March 10, 2005.
• Publication/Filing Date: Publication Date: 2005-03-10; Priority Date: 2003-09-09.
• Brief Description: This patent describes wide bandgap (e.g., GaN) transistor devices that incorporate various field plate configurations (gate, source, drain field plates) to enhance breakdown voltage and reduce on-resistance.
• Potential Anticipation: This reference provides further teaching on the use of field plates in wide bandgap transistors, which is a feature of the second gate in US8264003B2 (Claims 1 and 10). However, it does not describe the unique "merged cascode transistor" architecture with two distinct gates and specific operating modes on a single semiconductor element.

6. US7052942B1

• Full Citation: US7052942B1, "Surface passivation of GaN devices in epitaxial growth chamber," Rf Micro Devices, Inc., granted May 30, 2006.
• Publication/Filing Date: Publication Date: 2006-05-30; Priority Date: 2003-09-19.
• Brief Description: This patent describes methods for passivating GaN devices, particularly HEMTs, by depositing a passivation layer (e.g., SiN, AlN) in-situ during epitaxial growth to mitigate current collapse.
• Potential Anticipation: This patent focuses on fabrication methods, specifically surface passivation, to improve the reliability of GaN devices. It does not disclose the structural or operational characteristics of the "merged cascode transistor" architecture of US8264003B2.

7. US20060060871A1

• Full Citation: US20060060871A1, "Enhancement mode III-nitride FET," International Rectifier Corp., published March 23, 2006.
• Publication/Filing Date: Publication Date: 2006-03-23; Priority Date: 2004-01-23.
• Brief Description: This patent describes an enhancement-mode III-nitride FET (e.g., GaN HEMT) that achieves a positive threshold voltage (normally OFF operation) by incorporating a P-type GaN layer beneath the gate.
• Potential Anticipation: This reference is highly relevant as it discloses the construction of an "enhancement mode III-nitride FET," which constitutes the first portion (Q1) of the transistor claimed in US8264003B2 (Claims 1 and 10). While it provides a key building block and method for achieving the enhancement mode, it describes a single enhancement mode FET, not the merged cascode structure with two gates (one enhancement, one depletion), nor the specific configuration where the drain of the enhancement mode portion is merged with the source of a depletion mode portion at a node within a single semiconductor element. Thus, it anticipates the enhancement mode aspect but not the entire inventive combination.

8. US20050189561A1

• Full Citation: US20050189561A1, "III-Nitride bidirectional switch," Kinzer Daniel M., published September 1, 2005.
• Publication/Filing Date: Publication Date: 2005-09-01; Priority Date: 2004-02-12.
• Brief Description: This patent describes a bidirectional switch circuit that employs two enhancement-mode III-Nitride HEMTs connected in series. Their gates can be connected in common or driven by a common signal to control current flow in both directions.
• Potential Anticipation: This reference discloses a circuit arrangement of two III-Nitride transistors for bidirectional switching. While it uses two transistors, it's not described as a single merged cascode transistor in a single semiconductor element as claimed in US8264003B2. The architecture of two separate FETs connected in series differs from the "merged" concept with a drain region of one portion merged with the source region of the other portion at a node in the semiconductor element. Furthermore, it does not specify one enhancement and one depletion mode device in a cascode configuration with the distinct gate voltage connections described in US8264003B2.

9. WO2005079370A2

• Full Citation: WO2005079370A2, "Iii-nitride bidirectional switch," International Rectifier Corporation, published September 1, 2005.
• Publication/Filing Date: Publication Date: 2005-09-01; Priority Date: 2004-02-12.
• Brief Description: This is the international counterpart to US20050189561A1, describing a bidirectional switch implemented with two series-connected III-Nitride HEMTs.
• Potential Anticipation: The analysis is identical to US20050189561A1. It describes a circuit of two discrete transistors rather than the "merged cascode transistor" claimed in US8264003B2.

10. JP2008522436A

• Full Citation: JP2008522436A, "Always-off integrated JFET power switch in wide band gap semiconductor and fabrication method," Semisouth Laboratories, Inc., published June 26, 2008.
• Publication/Filing Date: Publication Date: 2008-06-26; Priority Date: 2004-12-01.
• Brief Description: The abstract describes an "always-off" (enhancement mode) integrated JFET power switch in wide bandgap semiconductors (e.g., SiC, GaN). It explicitly mentions a cascode circuit comprising a normally-on (depletion mode) device and a normally-off (enhancement mode) device. This suggests an integrated cascode, although the typical implementation for Semisouth's early work was often a depletion mode HEMT cascoded with an integrated silicon or silicon carbide JFET on a separate die or as part of a hybrid integration, rather than a single GaN HEMT with two merged gates.
• Potential Anticipation: This reference is highly relevant for disclosing the concept of a cascode circuit combining enhancement mode and depletion mode wide bandgap devices for "always-off" operation. While it discusses an "integrated JFET power switch," the crucial distinction for US8264003B2's claims (Claims 1 and 10) is the specific "merged cascode transistor" with two gates (one for enhancement, one for depletion) on a single HEMT structure where the drain of the enhancement mode transistor is merged with the source of the depletion mode transistor at a node in the semiconductor element. If "integrated JFET" implies two separate device types (e.g., a HEMT and a JFET on the same chip but not as a single merged two-gate transistor), it would not fully anticipate the "merged cascode transistor" as described in US8264003B2. However, it certainly teaches the fundamental cascode combination of enhancement and depletion devices in wide-bandgap technology.

Summary of Most Relevant Prior Art:

The most relevant prior art documents for US8264003B2 are US20060060871A1 and JP2008522436A (and its US counterpart, e.g., US7501670B2 if available).

• US20060060871A1 is highly relevant because it describes the creation of an enhancement mode III-Nitride FET, which is explicitly stated as the first portion (Q1) in Claims 1 and 10 of US8264003B2. This reference teaches a fundamental component of the invention.
• JP2008522436A (or its family members like US7501670B2) is highly relevant for disclosing the cascode circuit concept that combines a normally-on (depletion mode) device with a normally-off (enhancement mode) device in wide bandgap semiconductors. This directly addresses the functional arrangement of the two portions (Q1 and Q2) in US8264003B2. The key difference remains whether this prior art teaches the physical integration as a single merged transistor with two gates on the same semiconductor element as claimed in US8264003B2, rather than a multi-chip or heterogeneously integrated solution.

To analyze the obviousness of US patent 8264003 under 35 U.S.C. § 103, we must identify combinations of prior art references that disclose all limitations of the claims and demonstrate a motivation for a person having ordinary skill in the art (POSITA) to combine them to achieve the claimed invention.

The independent claims are Claim 1 and Claim 10. Both claims describe a merged cascode transistor circuit.

Key Features of Claim 1 (General Merged Cascode Transistor):

1. Input voltage signal source and constant voltage source.
2. A merged cascode transistor comprising:
   • Semiconductor element with source and drain electrodes.
   • First gate (Q1 portion) connected to input voltage signal.
   • Second gate (Q2 portion) positioned adjacent to the first gate, connected to a constant voltage source, and includes a field plate.
   • Q1 is an enhancement mode (EM) transistor.
   • Q2 is a depletion mode (DM) transistor.
   • Drain region of EM Q1 is merged with the source region of DM Q2 at a node in the semiconductor element.
   • Q1 conduction based on input voltage, Q2 conducts until voltage difference at node reaches a predetermined level (e.g., pinch-off voltage).

Key Features of Claim 10 (Merged Cascode High Electron Mobility Transistor - HEMT):
This claim adds material specificity to Claim 1:

1. First epitaxial layer of III-Nitride material.
2. Second epitaxial layer of III-Nitride material in contact with the first, forming a 2-dimensional electron gas (2DEG) conducting layer between them.
3. Source and drain electrodes connected to the first epitaxial layer.
4. First and second gates coupled to the first epitaxial layer.

Background of the Invention & Problem Addressed:
The patent identifies issues with conventional FETs in high voltage, high speed switching applications, particularly the "Miller effect" due to large drain-source voltage (Vds) swings, leading to excessive switching losses and unwanted turn-on due to dV/dt induced gate voltage transients (VG1). The disclosed invention aims to reduce these problems.

Prior Art References for Obviousness Analysis:

A POSITA in the field of power electronics and semiconductor device design at the time of the invention (priority date March 20, 2006) would be aware of various transistor technologies, including cascode configurations, enhancement-mode (E-mode) and depletion-mode (D-mode) devices, wide bandgap semiconductors (like III-Nitride), and field plating techniques for high voltage devices.

We will primarily consider the patent citations explicitly listed in US8264003 for this analysis.

1. US20060060871A1 (International Rectifier Corp.): "Enhancement mode III-nitride FET". This reference clearly teaches enhancement mode III-Nitride FETs, which are a core component for the Q1 portion, especially in the context of HEMTs (Claim 10).
2. US20050051796A1 (Cree, Inc.): "Wide bandgap transistor devices with field plates". This patent teaches the use of field plates in wide bandgap transistors to improve breakdown voltage and reliability. This feature is explicitly recited for the second gate (Q2) in both Claim 1 and Claim 10.
3. US6903383B2 (Matsushita Electric Industrial Co., Ltd.): "Semiconductor device having a high breakdown voltage for use in communication systems". This patent teaches a semiconductor device with a high breakdown voltage, potentially using cascode structures or techniques for high voltage applications.
4. Conventional Cascode Configurations: The patent itself describes a "conventional field effect transistor (FET)" and acknowledges that FETs are "used in large switching applications, for example, in DC-DC power converters". The concept of cascode configurations for high voltage switching applications, typically combining a low-voltage input device with a high-voltage output device, was well-known in the art prior to 2006.

Obviousness Analysis of Claim 1:

A combination of conventional cascode design principles, US20060060871A1, and US20050051796A1 would render Claim 1 obvious.

• Conventional Cascode: A POSITA would be well-aware of cascode circuits, which typically combine two transistors in series to achieve higher voltage blocking capability and reduced Miller effect compared to a single transistor. This would inherently involve an input voltage signal source and a constant voltage source for controlling the devices in a cascode pair.
• EM and DM Transistors in Cascode: It was a known practice to combine an enhancement-mode (normally-off) low-voltage transistor with a depletion-mode (normally-on) high-voltage transistor in a cascode arrangement to achieve a normally-off overall switch with the benefits of the high-voltage D-mode device. This configuration addresses the long-standing problem of creating normally-off power switches with D-mode devices, which are often superior in high-frequency performance. The patent itself notes that depletion mode devices are "normally ON" and enhancement mode devices are "normally OFF", indicating these are well-understood device characteristics.
• Merged Cascode Structure: The merging of the drain of the EM transistor with the source of the DM transistor at an internal node, as described in Claim 1, is a logical step for monolithic integration or for compact packaging in power devices to minimize parasitic inductance and resistance. A POSITA seeking to optimize performance and reduce chip area would be motivated to integrate or merge the two transistors rather than having them as discrete components. This is implicitly taught by the concept of "cascode" itself, where the devices are functionally in series, and monolithic integration offers performance advantages.
• Field Plate on Second Gate (DM Transistor): US20050051796A1 explicitly teaches "Wide bandgap transistor devices with field plates" to manage electric fields and improve breakdown voltage. A POSITA designing a high-voltage cascode stage (Q2, the DM transistor) would naturally consider applying field plates to this device to improve its high-voltage characteristics and reliability, especially given the "stable higher voltage operation" intended for Q2. The motivation is clearly stated in US20050051796A1 for improving device performance.
• Constant Voltage on Second Gate: In a typical cascode, the gate of the high-voltage (DM) device is often tied to a fixed voltage (e.g., ground) or a bias voltage, allowing the low-voltage (EM) device to control the switching action while the DM device effectively "stacks" the voltage. This configuration is fundamental to achieving the desired high-voltage blocking and reduced Miller effect as described in the background of US8264003.

A POSITA, facing the known problems of the Miller effect and dV/dt induced turn-on in high-speed power switching applications, as described in US8264003's background, would be motivated to combine these known techniques. The cascode configuration, particularly with an EM-DM combination, was a well-established solution to these problems, allowing the low-voltage EM device to handle the input switching, while the high-voltage DM device provides voltage blocking with reduced Miller coupling to the input. Integrating the field plate (from US20050051796A1) onto the high-voltage DM transistor would be a natural choice to enhance its high-voltage capability and reliability, as taught by that reference. The "merged" aspect is an engineering choice for integration, compactness, and parasitic reduction, which would be apparent to a POSITA.

Obviousness Analysis of Claim 10:

Claim 10 specifies a high electron mobility transistor (HEMT) implemented with III-Nitride materials and a 2DEG layer.

A combination of conventional cascode design principles, US20060060871A1, US20050051796A1, and general knowledge of III-Nitride HEMT technology would render Claim 10 obvious.

• III-Nitride HEMT as the Semiconductor Element: US20060060871A1 specifically teaches "Enhancement mode III-nitride FETs". This reference, along with general knowledge in the field, establishes III-Nitride materials (such as AlGaN/GaN) and the formation of a 2DEG layer as a known and advantageous technology for high-speed, high-power applications due to their high electron mobility and breakdown voltage. The patent itself highlights the implementation of its invention as a "high electron mobility transistor (IEMT)" in FIG. 3 and FIG. 4, using "two III-Nitride epitaxial layers... with a 2DEG conducting layer". This indicates that the base technology for GaN HEMTs was already known.
• Application of Cascode Principles to III-Nitride HEMTs: Given the benefits of III-Nitride HEMTs for high-frequency and high-power applications, a POSITA seeking to exploit these advantages while mitigating the issues (e.g., Miller effect) that are particularly problematic in high-frequency switching, would be motivated to apply known cascode topologies to III-Nitride devices. The problem addressed by US8264003 (Miller effect, dV/dt) is universal to FETs, including HEMTs, as acknowledged in the background: "These problems are common in all FET devices whether they are silicon, non-silicon or IEMT devices." Therefore, applying a known solution (cascode with EM/DM and field plates) to a known device technology (III-Nitride HEMTs) to address a known problem would be obvious.
• Specifics of III-Nitride HEMT in Cascode:
  • EM Q1 and DM Q2: US20060060871A1 teaches enhancement mode III-Nitride FETs, suitable for Q1. Depletion mode III-Nitride HEMTs were also well-known as the primary form of GaN HEMT technology at the time. A POSITA would combine an E-mode GaN HEMT (from US20060060871A1) with a D-mode GaN HEMT in a cascode to achieve a normally-off switch, as motivated by the same considerations for Claim 1.
  • Field Plate on Q2: US20050051796A1's teaching of field plates for "Wide bandgap transistor devices" is directly applicable to III-Nitride HEMTs (a type of wide bandgap device).
  • Merged Structure: The motivation for a merged structure, as discussed for Claim 1, equally applies to III-Nitride HEMTs to improve performance and integration.

Motivation to Combine:

The motivation for a POSITA to combine these elements is rooted in addressing the well-known challenges of high-voltage, high-frequency switching devices, specifically the Miller effect and dV/dt induced turn-on, as explicitly articulated in the "Background of the Invention" of US8264003.

1. Reduce Miller Effect and dV/dt: The primary motivation for using a cascode configuration (especially an E-mode/D-mode combination) is to reduce the effective gate-drain capacitance (Cgd) seen by the input driver, thereby mitigating the Miller effect and preventing spurious turn-on due to high dV/dt at the drain. This problem and the cascode solution were well-understood in the art.
2. Achieve Normally-Off Operation with High-Performance D-mode Devices: Depletion-mode (normally-on) HEMTs generally offer superior high-frequency performance. Combining them with an enhancement-mode (normally-off) device in a cascode allows the system to be normally-off, which is often a safety and design requirement in power applications, while still leveraging the performance benefits of the D-mode device.
3. Improve High Voltage Handling: The use of field plates on the high-voltage (DM) portion of the cascode, as taught by US20050051796A1, provides a clear motivation to further enhance the breakdown voltage and reliability of the device.
4. Leverage III-Nitride Advantages: A POSITA would be motivated to use III-Nitride materials (as taught by US20060060871A1) due to their inherent advantages in high-power, high-frequency applications (e.g., high breakdown field, high electron mobility leading to low ON-resistance and fast switching). The application of known circuit topologies (like cascode) to new, advantageous material systems (like GaN) to solve existing problems is a common and obvious engineering practice.
5. Integration and Miniaturization: The "merged" aspect is motivated by the desire for reduced parasitic elements, improved compactness, and cost efficiency associated with monolithic integration, which are general goals in semiconductor device manufacturing.

Therefore, a POSITA, aware of the problems in high-speed power switching, the benefits of cascode configurations (especially EM/DM combinations), the advantages of wide bandgap materials like III-Nitride for high-power devices, and the technique of field plating for voltage enhancement, would have been motivated to combine these known elements to create the claimed merged cascode transistor, including a HEMT version. The combination would yield predictable results in addressing the identified problems without requiring inventive step.