US 7969231

Here is a concise summary of US patent 7969231:

US Patent 7969231 Summary

• Title: Internal voltage generating circuit
• Assignee: The current assignee is Advanced Memory Technologies LLC. The original assignee was Panasonic Corp.
• Inventors: Seiji Yamahira.
• Filing Date: July 2, 2009.
• Issue Date: June 28, 2011.
• Abstract: The patent describes an internal voltage generating circuit where an output terminal of a first boost circuit is connected to a second boost circuit. After the second boost circuit starts up, its boost clock frequency is reduced. This design reduces the startup time for the second boost circuit and increases the current supply capability of the first boost circuit once the second is running. The goal is to stably supply output voltages from both boost circuits without instantaneous changes in the first boost circuit's output voltage when the second boost circuit is active.

Independent Claims Overview:

• Claim 1: This claim describes an internal voltage generating circuit comprising a first boost circuit (between a first voltage and a first terminal), a second boost circuit (between the first terminal and a second terminal), a frequency dividing circuit (to divide a first clock signal for the first boost circuit to generate a second clock signal), and a buffer circuit (to select and supply either the first or second clock signal to the second boost circuit).
• Claim 3: This claim outlines an internal voltage generating circuit featuring a first charge pump circuit (generating a second voltage from a first voltage), a second charge pump circuit (generating a third voltage from the second voltage), a frequency dividing circuit (to generate a second clock signal from a first clock signal), and a buffer circuit (to select either the first or second clock signal to generate a third clock signal). This third clock signal is then supplied to the second charge pump circuit.
• Claim 6: This claim details an internal voltage generating circuit with a first charge pump circuit (generating a second voltage from a first voltage) and a second charge pump circuit (generating a third voltage from the second voltage). The frequency of the clock signal supplied to the second charge pump circuit is changed based on a control signal, specifically by dividing an original frequency.
• Claim 7: This claim describes an internal voltage generating circuit that includes a first charge pump circuit (generating a second voltage from a first voltage) and a second charge pump circuit (generating a third voltage from the second voltage). In this circuit, the duration of the high state of the clock signal supplied to the second charge pump circuit is changed according to a control signal.

Legal Status and Litigation:
The patent US7969231 is currently active and is set to expire on July 24, 2029.

According to the Google Patents record, the patent family has litigation. This includes:

• A PTAB case, IPR2025-01451, which was filed but not instituted (procedural).
• A US case filed in the Texas Western District Court (case number 1:25-cv-01036).
• A US case filed in the Texas Eastern District Court (case number 2:24-cv-01078).
• A "First worldwide family litigation" was also filed.

Additionally, a disclaimer was filed for claims 6-8 of said patent with an effective date of December 1, 2025, on March 24, 2026.

A review of the CAFC scheduled cases for May 2026 did not explicitly list US7969231. However, it's possible related litigation could be under a different case name or number. I cannot definitively confirm the absence of all CAFC dockets for 2026 without directly searching the CAFC database by patent number, which is not directly supported by the current tools for all types of queries.

Based on the information available for US patent 7969231, the following litigation is known:

1. PTAB Inter Partes Review (IPR)

   • Case Number: IPR2025-01451
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Plaintiff(s) / Petitioner(s): SK Hynix, Inc.
   • Defendant(s) / Patent Owner(s): Advanced Memory Technologies LLC (current assignee) (implied as patent owner in an IPR)
   • Filing Date: August 27, 2025 (effective date of IPR filing)
   • Outcome / Current Status: Not Instituted - Procedural

2. U.S. District Court, Western District of Texas

   • Case Number: 1:25-cv-01036
   • Jurisdiction: Texas Western District Court
   • Plaintiff(s): Not explicitly stated in the provided text, but Advanced Memory Technologies LLC is the current assignee and likely the plaintiff.
   • Defendant(s): Not explicitly stated in the provided text.
   • Filing Date: Not explicitly stated in the provided text, but the case number suggests it was filed in 2025.
   • Outcome / Current Status: Litigation is active.

3. U.S. District Court, Eastern District of Texas

   • Case Number: 2:24-cv-01078
   • Jurisdiction: Texas Eastern District Court
   • Plaintiff(s): Not explicitly stated in the provided text, but Advanced Memory Technologies LLC is the current assignee and likely the plaintiff.
   • Defendant(s): Not explicitly stated in the provided text.
   • Filing Date: Not explicitly stated in the provided text, but the case number suggests it was filed in 2024.
   • Outcome / Current Status: Litigation is active.

Additionally, claims 6-8 of US7969231 were disclaimed with an effective date of December 1, 2025.

Proceedings overview

US Patent 7969231 has been subject to one Inter Partes Review (IPR) proceeding, IPR2025-01451, which concluded with a discretionary denial of institution. Additionally, claims 6-8 of the patent were disclaimed by the patent owner on December 1, 2025. This means that while some claims have been removed from the patent due to disclaimer, the validity of the remaining claims has not been substantively challenged and affirmed or denied through a Final Written Decision at the PTAB. The patent is therefore partially narrowed by disclaimer, but its core claims remain untested by PTAB.

IPR2025-01451 — SK Hynix Inc. v. Advanced Memory Technologies LLC

• Type: Inter Partes Review
• Filed: 2025-08-27
• Status: Discretionary Denial. Institution of the IPR was denied by the Director of the USPTO, meaning the trial did not proceed to a full review of the patentability of the challenged claims.
• Judge panel: Not applicable, as institution was denied by the Director, rather than a three-member panel, a new policy implemented by Director Squires effective October 20, 2025.
• Petition grounds: The petition challenged claims of US Patent 7969231. Specific details on the challenged claims, prior art, and statutory bases (§ 102 / § 103 / § 112) are not publicly detailed in the search results for this specific denial. However, discretionary denials often involve considerations of parallel litigation.
• Institution decision: Denied. The institution decision was made by Director John Squires, who assumed personal control over IPR and PGR institution decisions effective October 20, 2025. The denial was "discretionary," which, under new USPTO policies implemented in 2025, can be based on factors such as parallel district court proceedings, the age of the patent ("settled expectations"), or petitioner delay. For IPR2025-01449, a related IPR petition by SK Hynix Inc. against Advanced Memory Technologies LLC on a different patent, the Patent Owner argued for discretionary denial due to a parallel district court case scheduled for trial on October 5, 2026, where a Final Written Decision in the IPR would not be due until March 1, 2027. This strongly suggests a similar rationale for the denial of IPR2025-01451 given the same parties and patents in suit.
• Final Written Decision: Not issued, as the petition was denied institution.
• Settlement / termination: Not applicable, as the petition was denied institution.
• Appeal: Not applicable, as the institution decision cannot be appealed.
• Defensive value: This proceeding indicates that SK Hynix Inc. attempted to invalidate claims of US7969231 but was denied institution based on discretionary factors, likely due to a parallel district court case. This denial means the patent's validity was not substantively reviewed by the PTAB in this instance, making an IPR-based defense for future challengers potentially viable if different arguments or circumstances are presented.

Strategic summary

Claims 6-8 of US7969231 are CANCELED due to a disclaimer filed by the patent owner on December 1, 2025. The remaining claims (1-5 and 7-8 were original, with 6-8 disclaimed means claims 1-5 are still active) are considered SUSTAINED in the sense that they were not directly affected by the IPR proceedings and have not been cancelled by a Final Written Decision. IPR2025-01451 did not result in any claims being invalidated; rather, institution was denied on discretionary grounds. This means the underlying merits of the patentability challenges were not addressed by the PTAB.

The estoppel landscape for IPR2025-01451 is limited. Since institution was denied on discretionary grounds, SK Hynix Inc. (and its privies) are not estopped under 35 U.S.C. § 315(e)(2) from raising any ground that was raised or reasonably could have been raised in the IPR petition. However, the discretionary denial itself, particularly if based on the Fintiv factors (parallel litigation timeline, investment in district court, etc.), could influence future petitions from the same party or parties in similar situations against this patent. Given the recent changes in PTAB policy, where the Director personally reviews institution decisions and has, at times, denied a high percentage of petitions without detailed reasoning, future IPRs may face similar discretionary hurdles.

There are signals of parallel litigation, as Advanced Memory Technologies, LLC has sued SK Hynix Inc. for infringement of US7969231 (along with other patents) in the Eastern District of Texas, with a trial scheduled for October 5, 2026. This patent owner, Advanced Memory Technologies LLC, is also speculated to be a Patent Assertion Entity (PAE) or "patent troll" by some media outlets. The PTAB's discretionary denial of institution is likely tied to this ongoing district court litigation.

Recommended next steps

• Claims 6, 7, and 8 of US7969231 were disclaimed by the patent owner on December 1, 2025, as recorded in the legal events of the patent. Any infringement theory built on these claims is moot.
• For the IPR2025-01451 proceeding, while the institution was denied, the underlying merits of the invalidity arguments were not adjudicated. A defendant facing assertion of this patent could consider filing a new IPR petition, potentially with different prior art or arguments, or addressing the discretionary factors that led to the previous denial. However, recent changes in PTAB practice, where the Director exercises significant discretion in institution decisions, particularly with parallel litigation, should be carefully considered. It would be advisable to review the specific reasoning for the discretionary denial, if available, on the USPTO PTAB E2E system to understand the precise grounds. As of the current date, the institution decision would have been issued.

Inventors

• Seiji Yamahira (Employer: Panasonic Corp)

Note: In the US, initial ownership of a patent typically vests in the inventor. However, employment agreements often assign these rights to the employer. Given Panasonic Corp was the original assignee, it is highly probable Seiji Yamahira was employed by Panasonic Corp at the time of filing.

Original assignee

The original assignee on the issued patent is Panasonic Corp.

Panasonic Holdings Corporation (formerly Panasonic Corporation) is a Japanese multinational electronics manufacturer, headquartered in Kadoma, Osaka, Japan. They produce a wide range of products and services, including consumer electronics, home appliances, automotive and avionic systems, industrial equipment, and rechargeable batteries. In 2019, Panasonic sold its semiconductor business.

Panasonic Holdings Corporation is currently operating.

Assignment timeline

• 2009-06-22 (executed) / recorded 2009-09-22 — Reel 023266/0680
  • Conveyance: Assignment
  • Assignor: YAMAHIRA, SEIJI
  • Assignee: PANASONIC CORPORATION
  • Correspondent: NOT LISTED
  • Context: Original assignment from inventor to corporation.
• 2020-08-17 (executed) / recorded 2020-08-24 — Reel 053570/0429
  • Conveyance: Assignment
  • Assignor: PANASONIC CORPORATION
  • Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Correspondent: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
  • Context: Internal reorganization; transfer of semiconductor-related assets.
• 2020-09-02 (executed) / recorded 2024-03-20 — Reel 066849/0802
  • Conveyance: Change of Name
  • Assignor: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Correspondent: PANASONIC CORPORATION, 1000, KADOMA, KADOMA-SHI, OSAKA, JAPAN
  • Context: Change of name, likely following Nuvoton Technology Corporation's acquisition of Panasonic's semiconductor business.
• 2024-03-25 (executed) / recorded 2024-04-22 — Reel 067184/0869
  • Conveyance: Assignment
  • Assignor: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Assignee: ADVANCED MEMORY TECHNOLOGIES LLC
  • Correspondent: KEMPER DIEHL, SUSMAN GODFREY LLP, 1000 LOUISIANA STREET, SUITE 5100, HOUSTON, TX 77002. This correspondent appears on other active patent litigation.
  • Context: Transfer to a patent assertion entity.

Timeline diagram

timeline
    title Ownership of US 7969231
    2008 : Filed by Panasonic Corp
    2009 : Assigned from inventor to Panasonic
    2011 : Issued
    2020 : Internal transfer to Panasonic Semi
    2024 : Name changed to Nuvoton Tech Japan
         : Assigned to Advanced Memory Technologies LLC

NPE / troll-pattern signals

1. Shell-entity transfer — present. The patent was assigned to Advanced Memory Technologies LLC (AMT) on 2024-04-22 (Reel 067184/0869). AMT is a Delaware limited liability company with its principal place of business at 825 Watters Creek Blvd. Suite 250, Allen, Texas 75013. Public records do not identify the personnel or management of Advanced Memory Technologies. AMT has been identified as a non-practicing entity (NPE) or patent assertion entity (PAE) in recent patent infringement lawsuits.

2. Known asserter in the chain — present. Advanced Memory Technologies LLC (AMT) is identified as a non-practicing entity (NPE) that has recently filed patent infringement lawsuits. In December 2024, AMT sued SK Hynix Inc. for infringing four patents, including US7969231, in the Eastern District of Texas. AMT also filed a complaint against Micron Technology, Inc. in the Western District of Texas in June 2025.

3. Repeat correspondent across the chain — present. Kemper Diehl of Susman Godfrey LLP is listed as the correspondent for the assignment to Advanced Memory Technologies LLC on 2024-04-22 (Reel 067184/0869). Susman Godfrey LLP attorneys, including Justin Nelson and Kalpana Srinivasan, are representing Advanced Memory Technologies LLC in its patent infringement lawsuit against SK Hynix Inc. This firm has been involved in several high-profile IP enforcement cases.

4. Cascading transfers — not present. There are no multiple consecutive assignments through chained LLCs in a short timeframe that suggest cascading transfers.

5. Pre-litigation transfer — present. The assignment to Advanced Memory Technologies LLC was executed on 2024-03-25 and recorded on 2024-04-22 (Reel 067184/0869). Advanced Memory Technologies LLC filed a patent infringement lawsuit against SK Hynix Inc. in the Eastern District of Texas on December 30, 2024. This is approximately 8 months after the assignment was recorded, falling within a pattern often seen before assertion.

6. Bankruptcy fire-sale — not present. The original assignee, Panasonic Corp, and its successors in the chain are currently operating.

7. Privateering — unclear. While the transfer is to an NPE, there is no public information readily available in the provided context to confirm if Nuvoton Technology Corporation Japan or any other prior operating company is funding or directing the litigation against their competitors.

8. Defensive aggregator (anti-NPE) — not present. The patent is currently held by Advanced Memory Technologies LLC, which is actively asserting the patent.

Verdict

NPE — high confidence

This verdict is driven by several strong signals. The patent was transferred from an operating company (Nuvoton Technology Corporation Japan) to Advanced Memory Technologies LLC, a known shell entity with no identified products and a registered-agent address, as recorded on 2024-04-22 (Reel 067184/0869). This transfer was a pre-litigation event, occurring approximately eight months before Advanced Memory Technologies LLC filed a patent infringement lawsuit against SK Hynix Inc. in December 2024. Furthermore, the correspondent for the final assignment, Kemper Diehl of Susman Godfrey LLP, is associated with a firm actively engaged in patent assertion.

Verification: USPTO Assignment Center search for US7969231

To identify the most relevant prior art for US patent 7969231, I will examine the patent citations listed in the Google Patents record. For each cited patent, I will provide the full citation, publication/filing date, a brief description, and discuss which claims of US7969231 it potentially anticipates under 35 U.S.C. § 102.

It's important to note that the USPTO website offers tools for patent searching, including Patent Public Search, which allows users to search databases of patents and patent application publications. The effective date of prior art for U.S. patents can be its filing date, or an earlier effective U.S. filing date under 35 U.S.C. 102(e) (pre-AIA) or 35 U.S.C. 102(a)(2) (AIA). Prior art can include patents, printed publications, public use, sales, or other public availability before the effective filing date of the claimed invention.

Disclaimer on Claims 6-8: As noted in the patent summary, a disclaimer for claims 6-8 of US7969231 was filed with an effective date of December 1, 2025, on March 24, 2026. Therefore, these claims are no longer active.

Here's an analysis of the cited prior art:

Cited Prior Art for US Patent 7969231

The following patents are cited as prior art in US7969231:

1. U.S. Pat. No. 5,999,475 (US5999475A)

   • Full Citation: US5999475A, Mitsubishi Denki Kabushiki Kaisha, "Internal potential generation circuit that can output a plurality of potentials, suppressing increase in circuit area", published December 7, 1999.
   • Publication/Filing Date: Publication Date: December 7, 1999. Filing Date: August 27, 1997.
   • Brief Description: This patent describes an internal potential generation circuit with a plurality of charge pump circuits that can output multiple potentials while suppressing an increase in circuit area. It specifically mentions an internal voltage generating circuit with a first boost circuit and a second boost circuit, and a high voltage switch circuit that connects or disconnects their output nodes. The first boost circuit has a higher current supply capability and a lower boosted voltage target, while the second has a lower current supply capability and a higher boosted voltage target. During startup, the switch circuit is conductive, allowing the higher-capability first boost circuit to rapidly charge the second output node. After the first boosted voltage reaches its target, the switch becomes non-conductive, and the circuits operate independently. This is explicitly discussed in the background section of US7969231 as a conventional internal voltage generating circuit (FIG. 9-12 and accompanying description).
   • Potential Anticipation (35 U.S.C. § 102): US5999475A appears to anticipate the fundamental concept of having multiple boost circuits with different characteristics and a switching mechanism to aid in faster startup of a lower current capability circuit. Specifically, it anticipates aspects related to:
     • An internal voltage generating circuit comprising a first boost circuit and a second boost circuit.
     • The relationship where the first boosted voltage is lower than the second boosted voltage, and the current supply capability of the first is larger than the second.
     • The use of a high voltage switch circuit to connect/disconnect the output nodes for faster charging.
     • The independent operation of the charge pump circuits after an initial startup phase.

   This patent forms the basis of the "conventional internal voltage generating circuit 900" detailed in the background section of US7969231. Therefore, many elements of independent claims 1, 3, 6, and 7, which generally describe a first boost/charge pump circuit generating a voltage and a second boost/charge pump circuit generating a higher voltage, could be considered anticipated by US5999475A in a broad sense. However, US7969231 introduces specific improvements, such as the frequency dividing circuit and buffer circuit, to overcome limitations of this prior art. Therefore, while the core architecture is present, the specific inventive steps of US7969231 related to clock signal management would differentiate it.

2. U.S. Pat. No. 5,940,284 (US5940284A)

   • Full Citation: US5940284A, Zilog, Inc., "Low voltage charge pump circuit", published August 17, 1999.
   • Publication/Filing Date: Publication Date: August 17, 1999. Filing Date: December 18, 1997.
   • Brief Description: This patent describes a low voltage charge pump circuit. The abstract mentions a charge pump circuit that generates a boosted voltage from a low supply voltage, utilizing a diode-connected transistor structure and a control circuit to regulate the output.
   • Potential Anticipation (35 U.S.C. § 102): US5940284A generally addresses the construction and operation of charge pump circuits for generating boosted voltages from low supply voltages. While it covers the broad concept of a charge pump, it does not appear to disclose the specific two-stage boost circuit architecture with variable clock frequencies for startup acceleration or power efficiency as claimed in US7969231. It may anticipate the general concept of a "charge pump circuit configured to generate a voltage" as a sub-component, potentially impacting the novelty of such a broad statement in any claim (e.g., portions of Claims 1, 3, 6, 7 that refer to a "first boost circuit" or "first charge pump circuit" generating a voltage from a first voltage). However, it is unlikely to anticipate the unique combination of elements related to frequency division and clock selection for a second boost circuit.

3. U.S. Pat. No. 6,249,445 (US6249445B1)

   • Full Citation: US6249445B1, Nec Corporation, "Booster including charge pumping circuit with its electric power consumption reduced and method of operating the same", published June 19, 2001.
   • Publication/Filing Date: Publication Date: June 19, 2001. Filing Date: February 15, 1999.
   • Brief Description: This patent discloses a booster circuit with a charge pumping circuit designed for reduced electric power consumption. It focuses on controlling the operation of the charge pump to minimize current drain when the output voltage reaches a desired level, often by stopping or slowing down the clock signal to the charge pump.
   • Potential Anticipation (35 U.S.C. § 102): US6249445B1 anticipates methods for reducing power consumption in charge pump circuits by controlling the clock signal. This broadly relates to the concept of managing clock signals for efficiency. While US7969231 also deals with clock signal modification (frequency division), its primary inventive step lies in reducing startup time and then operating the second charge pump at a reduced frequency for stable supply and improved efficiency of the first boost circuit, rather than simply stopping the clock once a target voltage is reached. It might anticipate the idea of changing the "frequency of a clock signal to be supplied to the second charge pump circuit" (Claim 6, which is disclaimed) or changing the "length of a period in which a clock signal...is in a high state" (Claim 7, which is disclaimed), if those changes are for power reduction. However, the specific combination with the two-stage boost architecture and the initial high-frequency operation for fast startup, followed by a reduced frequency, is not clearly anticipated.

4. U.S. Pat. No. 6,278,317 (US6278317B1)

   • Full Citation: US6278317B1, International Business Machines Corporation, "Charge pump system having multiple charging rates and corresponding method", published August 21, 2001.
   • Publication/Filing Date: Publication Date: August 21, 2001. Filing Date: October 29, 1999.
   • Brief Description: This patent describes a charge pump system with multiple charging rates. The system adjusts its charging rate, for instance, by changing the frequency of the clock signal, to optimize power consumption or startup time. It may use a higher frequency for faster charging and then a lower frequency for maintenance.
   • Potential Anticipation (35 U.S.C. § 102): US6278317B1's disclosure of a charge pump system having multiple charging rates and methods for achieving this (e.g., by adjusting clock frequency) directly bears on the inventive features of US7969231. Specifically, the idea of changing the frequency of a clock signal supplied to a charge pump circuit in accordance with a control signal (Claim 6, disclaimed) or changing the length of a period in which a clock signal is in a high state (Claim 7, disclaimed) to achieve different charging rates for startup and stable operation is a core concept. This patent could potentially anticipate the broad concept of adapting the clock frequency to the second boost circuit as described in claims 6 and 7. However, US7969231's claims specify a two-stage boost architecture where the first boost circuit's output feeds the second, and the frequency division is applied to the second boost circuit's clock to manage startup and then allow the first circuit to concentrate current supply to its own load, which may represent a more specific combination not fully disclosed in US6278317B1.

5. U.S. Patent Application Publication No. 2004/0095806 (US20040095806A1)

   • Full Citation: US20040095806A1, Matsushita Electric Industrial Co., Ltd., "Boosting circuit and non-volatile semiconductor storage device containing the same", published May 20, 2004.
   • Publication/Filing Date: Publication Date: May 20, 2004. Filing Date: November 19, 2002.
   • Brief Description: This application describes a boosting circuit and a non-volatile semiconductor storage device containing it. It may address improvements in power supply for memory devices, including aspects of charge pump operation or efficiency.
   • Potential Anticipation (35 U.S.C. § 102): Without a more detailed description of US20040095806A1's content, it's difficult to pinpoint specific anticipations. Given its general title, it likely covers boosting circuits for non-volatile memory, which is a common application for US7969231. If it discloses a multi-stage boost architecture or clock control for charge pumps, it could potentially anticipate broad aspects of the claims. However, based solely on the title, it's unlikely to anticipate the specific combination of a frequency dividing circuit and buffer circuit controlling the clock signal to a second boost circuit that takes its input from a first boost circuit, as detailed in independent claims 1 and 3 of US7969231.

6. U.S. Pat. No. 6,980,045 (US6980045B1)

   • Full Citation: US6980045B1, Xilinx, Inc., "Merged charge pump", published December 27, 2005.
   • Publication/Filing Date: Publication Date: December 27, 2005. Filing Date: December 5, 2003.
   • Brief Description: This patent describes a "merged charge pump" which likely refers to a charge pump design that integrates multiple functions or stages to achieve a desired output voltage or current, possibly with area or efficiency benefits.
   • Potential Anticipation (35 U.S.C. § 102): The term "merged charge pump" suggests an integration or combination of charge pump elements. This could potentially relate to the concept of multiple charge pump circuits working in conjunction, but the details of such a merger and its control mechanisms would be critical. It is not immediately apparent from the title or brief description that it would anticipate the specific frequency division and clock selection mechanism for a second boost circuit receiving input from a first boost circuit as claimed in US7969231.

7. U.S. Patent Application Publication No. 2007/0222498 (US20070222498A1)

   • Full Citation: US20070222498A1, Freescale Semiconductor Inc., "Slew rate control of a charge pump", published September 27, 2007.
   • Publication/Filing Date: Publication Date: September 27, 2007. Filing Date: March 24, 2006.
   • Brief Description: This application focuses on slew rate control of a charge pump. Slew rate refers to the rate of change of voltage, and controlling it in a charge pump can impact its startup time, stability, and power consumption. This often involves dynamic adjustment of internal parameters, including clock frequency or drive strength.
   • Potential Anticipation (35 U.S.C. § 102): Slew rate control of a charge pump, particularly during startup, directly relates to the problem US7969231 aims to solve (reducing setup time). If US20070222498A1 discloses controlling the slew rate by dynamically changing the clock frequency to a charge pump, it could be highly relevant to claims 6 and 7 (both disclaimed) concerning changing the frequency or high-state period of the clock signal. Depending on the specifics, it might also anticipate aspects of claims 1 and 3 regarding dynamically adjusting clock signals to a boost circuit for performance optimization, especially during startup.

8. U.S. Pat. No. 7,579,902 (US7579902B2)

   • Full Citation: US7579902B2, Atmel Corporation, "Charge pump for generation of multiple output-voltage levels", published August 25, 2009.
   • Publication/Filing Date: Publication Date: August 25, 2009. Filing Date: December 11, 2006.
   • Brief Description: This patent describes a charge pump capable of generating multiple output-voltage levels. This implies the ability to provide different boosted voltages, possibly for different applications within a device.
   • Potential Anticipation (35 U.S.C. § 102): The ability to generate multiple output-voltage levels is a characteristic shared with US7969231, which produces a first boosted voltage (VPUMP1) and a second, higher boosted voltage (VPUMP2). However, merely generating multiple voltages does not necessarily anticipate the specific architecture and control mechanisms of US7969231, particularly the cascaded boost circuits with frequency division for the second stage. It might anticipate the general concept of an internal voltage generating circuit outputting multiple boosted voltages, which is a broad aspect underlying the invention.

9. U.S. Pat. No. 7,592,856 (US7592856B2)

   • Full Citation: US7592856B2, Rohm Co., Ltd., "Charge pump circuit driver circuit having a plurality of oscillators", published September 22, 2009.
   • Publication/Filing Date: Publication Date: September 22, 2009. Filing Date: December 3, 2004.
   • Brief Description: This patent describes a charge pump circuit driver circuit that utilizes a plurality of oscillators. Having multiple oscillators could allow for different clock frequencies or phases to be generated and applied to the charge pump, potentially for efficiency or performance reasons.
   • Potential Anticipation (35 U.S.C. § 102): The use of a "plurality of oscillators" to drive a charge pump circuit is highly relevant to US7969231's frequency dividing circuit and buffer circuit, which effectively provide a choice between a high-frequency clock signal (CLK) and a lower-frequency clock signal (FCK) to the second boost circuit. This patent could potentially anticipate the concept of generating and selecting different clock signals for a charge pump. Specifically, it could be argued to anticipate parts of claims 1 and 3 that involve a frequency dividing circuit generating a second clock signal from a first and a buffer circuit selecting between them. The key distinction for US7969231 would lie in the specific application of this variable clocking within the cascaded boost circuit context to achieve the stated benefits of reduced startup time and improved efficiency for the first boost circuit.

10. U.S. Pat. No. 7,605,639 (US7605639B2)

    • Full Citation: US7605639B2, Hynix Semiconductor, Inc., "Internal voltage generator of semiconductor memory device", published October 20, 2009.
    • Publication/Filing Date: Publication Date: October 20, 2009. Filing Date: April 18, 2007.
    • Brief Description: This patent describes an internal voltage generator for a semiconductor memory device. Such generators typically include charge pump circuits and associated control logic to provide various internal operating voltages required by the memory.
    • Potential Anticipation (35 U.S.C. § 102): Similar to US20040095806A1, this patent generally describes an internal voltage generator for memory devices. Without more specific details of its internal architecture and control mechanisms, it's difficult to identify precise anticipatory elements. It likely anticipates the broad context of the invention (voltage generation in semiconductor memory). However, it's unlikely to anticipate the specific combination of cascaded boost circuits with frequency division and selection for the second stage's clock signal as claimed in US7969231.

11. U.S. Pat. No. 7,782,120 (US7782120B2)

    • Full Citation: US7782120B2, Hynix Semiconductor Inc., "Internal voltage generating circuit", published August 24, 2010.
    • Publication/Filing Date: Publication Date: August 24, 2010. Filing Date: October 4, 2007.
    • Brief Description: This patent describes an internal voltage generating circuit. It would likely detail a power supply circuit for an integrated circuit, possibly including charge pump mechanisms.
    • Potential Anticipation (35 U.S.C. § 102): Like the previous entry, this patent has a very general title. It broadly covers internal voltage generating circuits, which is the field of US7969231. Specific details of its internal workings would be needed to assess potential anticipation. It might anticipate general aspects of internal voltage generation, but not necessarily the specific combination of a cascaded boost circuit with adaptive clock frequency control for the second stage.

Summary of Most Relevant Prior Art:

Based on the descriptions, US5999475A is highly relevant as it describes a conventional internal voltage generating circuit that serves as the starting point for US7969231, particularly regarding the two-stage boost circuit and the initial connection via a high voltage switch for faster charging. US6278317B1 and US7592856B2 are also very relevant as they disclose charge pump systems with multiple charging rates or multiple oscillators for driving charge pumps, which directly relates to the frequency control aspects of US7969231. These patents could potentially anticipate the general idea of varying the clock frequency of a charge pump.

The specific inventive contribution of US7969231 appears to be the novel combination of a cascaded boost architecture (where the first boost circuit's output is the input for the second boost circuit) with the dynamic clock frequency selection and division for the second boost circuit, controlled to optimize both startup time and subsequent operational efficiency of the overall system. The disclaimer of claims 6-8 further emphasizes that the invention's novelty is not merely in changing frequency but in how it's integrated into the two-stage architecture for specific performance benefits.

Obviousness Analysis of US Patent 7969231 under 35 U.S.C. § 103

This analysis addresses the obviousness of US patent 7969231, focusing on independent claims 1 and 3, as claims 6-8 have been disclaimed. The analysis considers the prior art cited within US7969231 and other references provided.

1. Claims to be Analyzed:

• Claim 1 (Independent): An internal voltage generating circuit comprising:

  • a first boost circuit provided between a first voltage and a first terminal;
  • a second boost circuit provided between the first terminal and a second terminal;
  • a frequency dividing circuit configured to divide a first clock signal to be supplied to the first boost circuit to generate a second clock signal; and
  • a buffer circuit configured to select and supply the first clock signal or the second clock signal to the second boost circuit.

• Claim 3 (Independent): An internal voltage generating circuit comprising:

  • a first charge pump circuit configured to generate a second voltage from a first voltage;
  • a second charge pump circuit configured to generate a third voltage from the second voltage;
  • a frequency dividing circuit configured to divide a first clock signal to generate a second clock signal; and
  • a buffer circuit configured to select the first clock signal or the second clock signal and generate a third clock signal,
  • wherein the third clock signal is supplied to the second charge pump circuit.

2. Primary Prior Art Reference:

The patent US7969231 itself details a conventional internal voltage generating circuit 900, disclosed in U.S. Pat. No. 5,999,475 (Mitsubishi Denki Kabushiki Kaisha), in its background section (FIG. 9 and associated description). This serves as a strong primary reference for an obviousness argument.

• Disclosure of US5999475: US5999475 describes an internal voltage generating circuit 900 including a first boost circuit 901 and a second boost circuit 902. Both boost circuits perform operation in synchronization with a clock signal CLK and a complementary clock signal XCLK. The first boost circuit 901 outputs a first boosted voltage VPUMP1 through a first output node N1, and the second boost circuit 902 outputs a second boosted voltage VPUMP2 through a second output node N2. A high voltage switch circuit 903 connects or disconnects a path between the first output node N1 and the second output node N2.
  • Crucially, in the conventional circuit, both the first charge pump circuit 906 (part of 901) and the second charge pump circuit 909 (part of 902) receive a power source voltage VDD as their input.
  • The conventional circuit operates in two phases: During "Phase 1," the switch 903 is conductive, allowing the first charge pump 906 (with high current supply capability) to rapidly charge both N1 and N2 to VPUMP1. During "Phase 2," the switch 903 becomes non-conductive, and the second charge pump 909 (with low current supply capability) independently charges N2 to VPUMP2.
• Problem Addressed by US7969231 in relation to US5999475: The conventional circuit faces a trade-off where reducing the setup time of the second charge pump during Phase 2 by increasing its boost capacitances (Cb1-Cb6) leads to increased circuit area and potentially requires additional smoothing capacitance to prevent ripple, further increasing area.

3. Missing Elements in US5999475 for Claims 1 and 3 of US7969231:

Based on the description of US5999475 within US7969231, the following key elements of Claims 1 and 3 are not directly present:

• Hierarchical Boosting Input: The "second boost circuit provided between the first terminal and a second terminal" (Claim 1) or "second charge pump circuit configured to generate a third voltage from the second voltage" (Claim 3). In US5999475, both charge pumps receive VDD, not the output of the first boost circuit.
• Frequency Dividing Circuit: A circuit configured to divide a clock signal.
• Buffer Circuit for Clock Selection: A circuit configured to select and supply either the original or frequency-divided clock signal to the second boost circuit.

4. Secondary Prior Art References and Motivation to Combine:

A person having ordinary skill in the art (PHOSITA) would be motivated to combine US5999475 with other known techniques to address the limitations identified in the conventional art.

Combination 1: US5999475 + General Knowledge of Multi-Stage Boosting + US6278317B1 / US7592856B2

• Motivation for Hierarchical Boosting (Connecting First Terminal to Second Boost Circuit Input):

  • Facing the problem in US5999475 of the second charge pump's slow setup time during Phase 2 or the undesirable increase in circuit area required to speed it up, a PHOSITA would recognize that supplying the second charge pump with an already boosted voltage (VPUMP1 from the first stage) instead of the lower VDD would inherently reduce the voltage difference the second stage needs to generate. This is a common and obvious design principle in multi-stage voltage generation to achieve higher voltages or faster boosting with fewer stages or smaller capacitors. By providing a pre-boosted input from the high current capability first charge pump, the second charge pump's setup time would be naturally reduced.

• Motivation for Frequency Dividing Circuit and Buffer Circuit (Dynamic Clock Frequency Reduction):

  • Even with the hierarchical input, the second charge pump still draws current from the first. US7969231 notes that after the initial setup, a high operating frequency for the second charge pump could still impact the stability of the first charge pump's output (VPUMP1).
  • US6278317B1 (International Business Machines Corporation) - "Charge pump system having multiple charging rates and corresponding method". This patent discloses a "frequency regulated charge pump" where "the frequency fclk is determined by a controller circuit that measures the difference between the target VOUT voltage and the real VOUT". This directly teaches dynamically varying the clock frequency of a charge pump.
  • US7592856B2 (Rohm Co., Ltd.) - "Charge pump circuit driver circuit having a plurality of oscillators". This reference implies the capability to generate or select from different clock frequencies.
  • A PHOSITA, seeking to further optimize the system of US5999475 (as modified with hierarchical input) to ensure stability of VPUMP1 after VPUMP2 has reached its target voltage, would be motivated to reduce the current drawn by the second charge pump from the first. Reducing the clock frequency of a charge pump is a well-known method to reduce its current consumption and ripple. Therefore, it would be obvious to incorporate a mechanism, like a frequency dividing circuit and a buffer for selecting between an original fast clock (for rapid initial setup) and a divided, slower clock (for maintenance), to supply the second charge pump. This allows current supply to be concentrated into the output load of the first charge pump, suppressing output voltage fluctuation, as explicitly stated as a benefit in US7969231. The frequency dividing circuit and buffer circuit are standard components for implementing such a clock selection scheme.

5. Conclusion on Obviousness:

Claims 1 and 3 of US7969231 would have been obvious to a person having ordinary skill in the art at the time of the invention. The combination of the conventional internal voltage generating circuit of US5999475 with:

1. The well-known engineering principle of hierarchical voltage boosting (using the output of a first boost stage as the input for a subsequent boost stage) to reduce setup time for the second stage.
2. The teachings of US6278317B1 regarding frequency-regulated charge pumps or US7592856B2 regarding multiple oscillators for charge pump clocking, for the purpose of dynamically adjusting the clock frequency of the second boost circuit.

The motivation for this combination arises from directly addressing the identified shortcomings of the conventional art in US5999475, namely the desire to reduce the setup time for the second boosted voltage (VPUMP2) without increasing circuit area, and to improve the stability and efficiency of the first boosted voltage (VPUMP1) once the second stage is active. The frequency dividing circuit and buffer circuit are standard components that a PHOSITA would readily employ to achieve the desired clock signal modification.