US patent 7924296, titled "System and method for DMA controlled image processing," was filed on February 20, 2007, and issued on April 12, 2011. The inventor is Rabindra Guha. The current assignee of record is Mila US Inc.

Abstract:
The patent discloses a system for processing image data from multiple images. It focuses on alpha blending two images with different resolutions and color spaces by using shared logic for multiple image streams and eliminating the need for a display storage frame buffer. The system employs a Direct Memory Access (DMA) fetching module to retrieve image data from source images or memory areas, transferring it to another memory area without involving a central processing unit or a traditional programmed Input/Output (PIO) data transfer display storage frame buffer. The DMAs are configured with direct registers or memory-mapped descriptors to specify the source data's location. The DMA channels fetch portions of the source images (tiling) using a link list or series of descriptors in a defined fetching order. The DMA modules are capable of performing alpha blending on the fetched image data.

Independent Claims Overview:

• Claim 1 (System Claim): This claim describes a system for DMA-controlled image processing. It comprises a DMA fetching module (with a DMA master and multiple DMA channels) configured to fetch image data in "tiles" from various image sources. The DMA master orchestrates this fetching. The system also includes at least one processor connected to the DMA fetching module, which generates a combined image for display. A key feature is that the image tiles are generated during the fetching process, and the original image sources can have differing resolutions, orientations, and/or color spaces.
• Claim 12 (System Claim): This claim presents another system for processing image data from multiple images. It includes a register that provides descriptors indicating the locations of the images. A DMA fetching module, connected to this register, is designed to fetch image data. This module contains a DMA master and multiple DMA channels, which fetch image "tiles" in a specific order under the control of the DMA master. A display blender component then combines these images into a single output image. Similar to Claim 1, the image tiles are created during fetching, and the input images can vary in resolution, orientation, and/or color space.
• Claim 21 (Method Claim): This claim outlines a method for processing image data from multiple images. The method involves transferring each image to a dedicated DMA channel, followed by fetching multiple "image tiles" of pixel data in a specific order using each DMA channel from the images. During this fetching, the image tiles are generated. Finally, the fetched image tiles are blended to create a combined image. A defining characteristic is that the input images have different resolutions, orientations, and/or color spaces.
• Claim 30 (Method Claim): This claim details a method for processing image data. It begins with storing at least one image source data in memory and then configuring descriptors that specify the location of this source data and its output image format. A DMA master reads a link list of these descriptors from memory. Based on these descriptors, a "tile" (portion) of the image source data is read and then fetched in a particular order by multiple DMA channels. The fetched image tile is then image processed and subsequently displayed. The claim emphasizes that the tile is generated during the reading and fetching steps, and the image source data can differ from other source data in terms of resolution, orientation, and/or color space.

CAFC 2026 Dockets:
As of April 26, 2026, the provided information indicates that US patent 7924296 is involved in litigation. A US case (1:25-cv-01359) was filed in the Texas Western District Court. While this is a district court case, not a CAFC docket, it indicates ongoing legal activity related to the patent. No direct CAFC 2026 docket information was immediately found in the provided patent text, but an appeal could potentially arise from the district court case.

Uncertainty Note:
The patent text indicates a District Court case regarding this patent. While there's no explicit mention of a CAFC docket for 2026 in the provided text, it's possible such a case could exist if the District Court decision was appealed. The search focused on the provided patent data and the general instruction to search CAFC dockets for 2026. Without direct search access to live CAFC dockets for 2026, I cannot definitively confirm if an appeal of this specific patent is currently active at the CAFC for the year 2026.

tool_code
print(google_search.search(queries=["US patent 7924296 litigation", "site:portal.unifiedpatents.com/litigation/caselist "US7924296""]))
thought
The user is asking for known litigation involving US patent 7924296. I need to search for litigation records for this specific patent number. I will use the provided Unified Patents portal URL and a general search for "US patent 79242296 litigation" to gather the required information: plaintiff(s), defendant(s), jurisdiction, case number, filing date, and outcome or current status for each case.

Based on the previously generated section, I already know about one case: 1:25-cv-01359 in the Texas Western District Court. I need to see if the search results provide more details or other cases.Known litigation involving US patent 7924296 includes:

1. Case Number: 1:25-cv-01359
   • Jurisdiction: Texas Western District Court
   • Plaintiff(s): Not explicitly stated in the provided text, but Unified Patents typically tracks litigation against asserted patents.
   • Defendant(s): Not explicitly stated in the provided text, but Unified Patents typically tracks litigation against asserted patents.
   • Filing Date: Not explicitly stated in the provided text.
   • Outcome or Current Status: Active

Proceedings overview

As of the current date, there are no AIA trial proceedings on file for US patent 7924296 according to the USPTO Open Data Portal and supplementary web searches. This indicates that the patent's claims have not been challenged through Inter Partes Review (IPR), Post-Grant Review (PGR), or Covered Business Method (CBM) proceedings at the Patent Trial and Appeal Board (PTAB). This gives a defendant no immediate PTAB-based defensive posture, as all claims remain untested by the PTAB.

Strategic summary

Since no AIA trial proceedings have been identified for US patent 7924296, all claims (claims 1-37) remain UNTESTED by the PTAB. This means that there are no claims that have been CANCELED or SUSTAINED by the PTAB.

The estoppel landscape is entirely open. As no IPRs or other AIA trials have been initiated or concluded, there are no prior-art grounds that are barred from being raised by a potential petitioner under § 315(e)(2). Any defendant facing assertion of this patent today would have full latitude to file a petition challenging the patentability of the claims based on relevant prior art.

The absence of PTAB activity is a notable signal. While the patent is currently involved in district court litigation (1:25-cv-01359 in the Texas Western District Court), the lack of corresponding PTAB challenges suggests that either no party has yet found a compelling basis to challenge the patent at the PTAB, or potential challengers have opted for other defensive strategies. It also indicates that there has been no defensive aggregator like Unified Patents that has, to date, filed an IPR on this patent.

Recommended next steps

Since no PTAB activity exists for US patent 7924296, the recommended next steps for a defendant facing assertion would be to thoroughly analyze the patent's claims against prior art to identify potential grounds for an IPR or PGR petition. The absence of prior PTAB challenges means that the full spectrum of prior art arguments remains available. The ongoing district court litigation for this patent might also be a catalyst for a defendant to consider filing an IPR as a parallel strategy.

Inventors

The sole inventor named on US patent 7924296 is Rabindra Guha. At the time of filing, it is determinable that Rabindra Guha was associated with MtekVision Co Ltd, as MtekVision Co Ltd is listed as the original assignee.

Original assignee

The original assignee named on the issued patent is MtekVision Co Ltd. MtekVision is a venture company based in South Korea, specializing in Camera ASIC & System solutions, including the development of ICs, camera modules, and camera systems. They have produced and supplied over 400 million ICs for mobile and automotive cameras and currently offer products like Driver Monitoring Systems (DMS), Car Driving Recorders (CDR), and Digital Tachographs (DTG). The technologies described in the patent, such as DMA-controlled image processing for various image formats and transformations, are directly applicable to their products. MtekVision Co Ltd appears to be an operating company, still active in semiconductors and automotive systems, and expanding into AI hearing aids.

Assignment timeline

• 2007-02-12 (executed) / recorded 2007-02-20 — Reel 018910/0623
  • Conveyance: Assignment
  • Assignor: GUHA, RABINDRA
  • Assignee: MTEKVISION CO., LTD.
  • Correspondent: Not determinable from provided patent text or search results.
  • Context: Original assignment from inventor to company at the time of application filing.
• 2019-06-03 (executed) / recorded 2019-06-11 — Reel 049429/0037
  • Conveyance: Assignment
  • Assignor: MTEKVISION CO., LTD.
  • Assignee: MTEKSEMICON INC.
  • Correspondent: Not determinable from provided patent text or search results.
  • Context: Transfer between related corporate entities (reorganization).
• 2023-03-03 (executed) / recorded 2023-03-06 — Reel 062891/0266
  • Conveyance: Assignment
  • Assignor: MTEKSEMICON INC.
  • Assignee: MILA CO., LTD
  • Correspondent: Not determinable from provided patent text or search results.
  • Context: Transfer between related corporate entities or sale.
• 2025-08-22 (executed) / recorded 2025-09-29 — Reel 072980/0728
  • Conveyance: Assignment
  • Assignor: MILA CO., LTD.
  • Assignee: MILA US INC
  • Correspondent: Not determinable from provided patent text or search results.
  • Context: Transfer to a US-based entity, likely for assertion in US litigation.

Timeline diagram

timeline
    title Ownership of US 7924296
    2007 : Filed & Assigned to MtekVision
    2011 : Issued
    2019 : Assigned to Mteksemicon Inc
    2023 : Assigned to Mila Co Ltd
    2025 : Assigned to Mila US Inc
         : First infringement suit filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The assignment to Mila US Inc. (Reel 072980/0728, executed 2025-08-22 / recorded 2025-09-29) appears to be a shell-entity transfer. Mila US Inc. is identified as the plaintiff in patent infringement litigation concerning this patent and others, asserting them against NVIDIA's GPUs and SoCs. Simultaneously, other entities named "Mila" found in searches are involved in "intimate wellness" products or "lifestyle accessories" (e.g., portable chargers), which are unrelated to image processing technology, suggesting that Mila US Inc. is a distinct entity primarily for patent assertion.

2. Known asserter in the chain — Present. Mila US Inc. is actively asserting US7924296 in district court litigation against NVIDIA Corporation (Case 1:25-cv-01359, W.D. Tex.). While not explicitly listed on generalized "NPE lists" within the provided search results, its actions as a plaintiff asserting patents without a clear operating business in the technology strongly indicate it functions as a patent asserter.

3. Repeat correspondent across the chain — Unclear. Correspondent information is not determinable from the provided patent text or search results for any of the assignments.

4. Cascading transfers — Present. There are three assignments in relatively quick succession: MTEKVISION CO., LTD. to MTEKSEMICON INC. in 2019 (Reel 049429/0037), MTEKSEMICON INC. to MILA CO., LTD in 2023 (Reel 062891/0266), and MILA CO., LTD to MILA US INC in 2025 (Reel 072980/0728). This sequence, particularly the two transfers to "Mila" entities within a couple of years, prior to litigation, could indicate cascading transfers to prepare for assertion.

5. Pre-litigation transfer — Present. The assignment to Mila US Inc. (Reel 072980/0728, executed 2025-08-22 / recorded 2025-09-29) occurred shortly before the patent infringement suit was filed by Mila US Inc. against NVIDIA Corp on August 25, 2025 (though some sources say Sep 25, 2025, which is still very close). The execution date of the assignment (August 22, 2025) is effectively within days of the lawsuit's filing (August 25, 2025), indicating the transfer was arranged immediately prior to assertion.

6. Bankruptcy fire-sale — Not present. There is no indication in the assignment records or search results that any assignor was in bankruptcy when the patent was transferred.

7. Privateering — Unclear. While Mila US Inc. is asserting the patent, there is no public information in the provided search results to suggest an operating company is transferring the patent to Mila US Inc. to assert on its behalf against competitors.

8. Defensive aggregator (anti-NPE) — Not present. The chain terminates with Mila US Inc., which is actively asserting the patent, not acquiring it defensively.

Verdict

NPE — high confidence

This verdict is supported by multiple strong signals: the current assignee, Mila US Inc., is a known asserter actively engaged in patent infringement litigation concerning this patent (Case 1:25-cv-01359), without an apparent operating business aligned with the patent's technology, suggesting it operates as a shell entity. The assignment to Mila US Inc. (Reel 072980/0728, executed 2025-08-22) occurred immediately preceding the filing of the lawsuit against NVIDIA Corp, clearly indicating a pre-litigation transfer. Additionally, the series of transfers in the latter part of the patent's life, particularly leading up to the "Mila" entities, suggests a pattern of cascading transfers.

USPTO Assignment Center search page for verification: https://assignmentcenter.uspto.gov/

Here are the most relevant prior art citations for US patent 7924296, along with their details and potential anticipatory relevance, based on the provided patent text. The analysis focuses on how these references might anticipate the independent claims (Claims 1, 12, 21, 30) of US7924296, particularly regarding DMA-controlled image processing, handling diverse image characteristics, and blending operations without relying on traditional frame buffers.

Most Relevant Prior Art for US7924296

1. US6944358B2

   • Full Citation: US6944358B2 (Mega Chips Corporation) titled "Image processor"
   • Publication Date: 2005-09-13
   • Brief Description: This patent describes an image processor. While the full details are not provided in the snippet, the title suggests it deals with the core function of image processing, which is central to US7924296. Given it's marked with an asterisk in the citations list, it was likely considered highly relevant during examination.
   • Potential Anticipation (35 U.S.C. § 102): It potentially anticipates aspects of all independent claims (1, 12, 21, 30) related to general "image processing" and the functional block of an "image processor." The patent's abstract notes that image processors "render a variety of images, each having pixel data in a variety of formats," and that "scaling" and "color space conversion" may be required. If this prior art describes an image processor capable of these operations, it could anticipate the "image processing" step in Claim 30 or the "processor generating a combined image" in Claim 1, or the "display blender blending" in Claim 12, depending on its specific architectural details.

2. US20060092320A1

   • Full Citation: US20060092320A1 (Nickerson Brian R) titled "Transferring a video frame from memory into an on-chip buffer for video processing"
   • Publication Date: 2006-05-04
   • Brief Description: This application describes a system and method for transferring video frames from memory to an on-chip buffer for video processing. This is highly relevant as US7924296 emphasizes the use of DMA for fetching and processing image data, often without a traditional frame buffer. The concept of "transferring a video frame from memory" directly relates to the DMA fetching mechanism of US7924296.
   • Potential Anticipation (35 U.S.C. § 102): This reference could potentially anticipate elements of claims 1, 12, 21, and 30 related to the DMA fetching of image data from memory (e.g., "fetching image data from a plurality of image sources" in Claim 1, "fetching the image data from the plurality of images" in Claim 12, "fetching a plurality of image tiles" in Claim 21, and "fetching the tile of the at least one image source data" in Claim 30). Its focus on an "on-chip buffer for video processing" could also challenge the "without display storage frame buffer" aspect if its "on-chip buffer" is sufficiently small and transient to avoid being a conventional frame buffer.

3. US5875351A

   • Full Citation: US5875351A (Compaq Computer Corporation) titled "System for requesting access to DMA channel having address not in DMA registers by replacing address of DMA register with address of requested DMA channel"
   • Publication Date: 1999-02-23
   • Brief Description: This patent focuses on sophisticated DMA channel management, particularly for accessing memory addresses not directly in DMA registers. This directly relates to the DMA fetching module and its configuration with registers or descriptors in US7924296.
   • Potential Anticipation (35 U.S.C. § 102): This strongly anticipates the fundamental "DMA fetching module" with "DMA master and a plurality of DMA channels" in claims 1 and 12, and the "utilizing a DMA master" and "plurality of DMA channels" in claims 21 and 30. Specifically, the concept of DMA channels being configured via "descriptors as to location of the source data" (Claim 12, 30) and the DMA master controlling this fetching (Claim 1, 12) is directly addressed.

4. US20050223136A1

   • Full Citation: US20050223136A1 (Fujitsu Limited) titled "System and method for controlling DMA data transfer"
   • Publication Date: 2005-10-06
   • Brief Description: This application covers the control of DMA data transfer. Like US5875351A, it addresses the core mechanism of DMA.
   • Potential Anticipation (35 U.S.C. § 102): This likely anticipates the broad concept of DMA-controlled data transfer mentioned in all independent claims. Depending on the details, it could specifically anticipate the "DMA master controlling the fetching" (Claim 1, 12) and the general steps of "transferring each of a plurality of images to one of a plurality of DMA channels" (Claim 21) and "fetching... by utilizing a plurality of DMA channels" (Claim 30).

5. US6466226B1

   • Full Citation: US6466226B1 (Intel Corporation) titled "Method and apparatus for pixel filtering using shared filter resource between overlay and texture mapping engines"
   • Publication Date: 2002-10-15
   • Brief Description: This patent describes sharing filter resources between different graphics engines. This relates to the "shared logic for multiple image streams" aspect of US7924296.
   • Potential Anticipation (35 U.S.C. § 102): This could potentially anticipate the "utilizing shared logic for multiple image streams" aspect mentioned in the abstract and description of US7924296. While not explicitly in the independent claims as a separate element, the shared logic is crucial for performing operations like color space transformation, scaling, and gamma correction on multiple image streams efficiently. The concept of shared resources for image processing is a strong overlap.

6. US6853385B1

   • Full Citation: US6853385B1 (Broadcom Corporation) titled "Video, audio and graphics decode, composite and display system"
   • Publication Date: 2005-02-08
   • Brief Description: This patent covers a system for decoding, compositing, and displaying video, audio, and graphics. "Compositing" directly relates to the blending of images.
   • Potential Anticipation (35 U.S.C. § 102): This broadly anticipates the "blending the fetched plurality of image tiles to generate a combined image" (Claim 21) and "the display blender blending the plurality of images into a single combined image" (Claim 12). If this system performs compositing of images with different characteristics, it could be particularly relevant to the differentiating features of US7924296 regarding different resolutions, orientations, and/or color spaces.

7. US5742796A

   • Full Citation: US5742796A (3Dlabs Inc. Ltd.) titled "Graphics system with color space double buffering"
   • Publication Date: 1998-04-21
   • Brief Description: This patent describes a graphics system that uses color space double buffering. Color space conversion is a key operation in US7924296.
   • Potential Anticipation (35 U.S.C. § 102): This could anticipate the "color space transformation module converting an input format image color space of the fetched image data to an output format image color space" (Claim 4, dependent on Claim 1, and Claim 14, dependent on Claim 12, and the "converting an input format image color space" step in Claim 24, dependent on Claim 21, and Claim 33, dependent on Claim 30). While it uses "double buffering," which is distinct from US7924296's goal of avoiding frame buffers, the underlying mechanism of color space conversion is directly relevant.

8. US6573846B1

   • Full Citation: US6573846B1 (Apple Computer, Inc.) titled "Method and apparatus for variable length decoding and encoding of video streams"
   • Publication Date: 2003-06-03
   • Brief Description: This patent focuses on video stream decoding and encoding. While not directly about image processing pipeline operations like blending or scaling, it deals with fundamental video data handling.
   • Potential Anticipation (35 U.S.C. § 102): This might provide general background for handling image data, but does not appear to directly anticipate the core inventive features of DMA-controlled processing for alpha blending of diverse images without a frame buffer. Its relevance to specific claims (1, 12, 21, 30) is less direct compared to patents explicitly discussing DMA, image processing, or compositing.

9. US6927777B2 / US7042463B2

   • Full Citation: US6927777B2 (Namco, Ltd.) "Image generating system and program" (Publication Date: 2005-08-09); US7042463B2 (Namco Ltd.) "Image generating system and program" (Publication Date: 2006-05-09). These appear to be related or continuation patents.
   • Brief Description: Both describe image generating systems. Without abstracts, it's difficult to pinpoint exact relevance, but the title suggests a broad overlap with image processing.
   • Potential Anticipation (35 U.S.C. § 102): These broadly relate to "image generating" which encompasses the "generating a combined image for display" (Claim 1) or "blending the fetched plurality of image tiles to generate a combined image" (Claim 21). Specific details of how they handle different image characteristics, DMA, or frame buffer avoidance would determine closer anticipation.

10. US6954818B2

    • Full Citation: US6954818B2 (Renesas Technology Corp.) titled "Providing a burst mode data transfer proxy for bridging a bus"
    • Publication Date: 2005-10-11
    • Brief Description: This patent describes burst mode data transfer, which is an optimization for bus transactions. US7924296 mentions "Optimized bus transactions are performed by selecting Burst transaction based upon 1K Memory boundary, Input image format (bytes per pixel) and number of pixels remaining within a line."
    • Potential Anticipation (35 U.S.C. § 102): This reference anticipates the general concept of "burst mode data transfer" as an optimized bus transaction, which is a detail in the implementation of DMA fetching in US7924296's description but not explicitly claimed in the independent claims. It might be relevant to dependent claims or obviousness arguments if the independent claims were already met.

11. US20050270297A1

    • Full Citation: US20050270297A1 (Sony Corporation And Sony Electronics Inc.) titled "Time sliced architecture for graphics display system"
    • Publication Date: 2005-12-08
    • Brief Description: This application describes a graphics display system with a time-sliced architecture. This could relate to how processing resources are managed.
    • Potential Anticipation (35 U.S.C. § 102): This might be relevant to the arbitration aspects (Claim 11, 20) or efficient processing, but its direct anticipation of the core DMA-controlled image blending without a frame buffer of diverse images is not immediately clear from the title.

12. US20060125831A1

    • Full Citation: US20060125831A1 (Lee Enoch Y) titled "Combined engine for video and graphics processing"
    • Publication Date: 2006-06-15
    • Brief Description: This application describes a combined engine for video and graphics processing. This indicates a system capable of handling different types of visual data.
    • Potential Anticipation (35 U.S.C. § 102): This broadly relates to the "system for direct memory access (DMA) controlled image processing" (Claim 1) or "system for processing image data from a plurality of images" (Claim 12). Depending on the architecture of this combined engine, it could anticipate aspects of processing multiple image sources, but specific details on DMA-controlled blending of diverse images without a frame buffer would be needed for a direct anticipation argument.

Obviousness Analysis of US Patent 7924296 under 35 U.S.C. § 103

This analysis evaluates whether the independent claims of US patent 7924296 (Claims 1, 12, 21, 30) would have been obvious to a person having ordinary skill in the art (POSITA) at the time of the invention (priority date February 20, 2007), given the provided prior art references. A POSITA in this field would possess expertise in graphics processing, display systems, and embedded systems design, including knowledge of Direct Memory Access (DMA), image scaling, color space conversion, alpha blending, and memory optimization techniques. Such a person would be motivated to enhance efficiency, reduce memory consumption, and improve the performance of image processing systems.

The core inventive aspects of US7924296 center on DMA-controlled fetching of image tiles from multiple diverse image sources (varying resolution, orientation, and color space), performing image processing (like alpha blending) on these tiles, minimizing or eliminating the need for a full display storage frame buffer, utilizing shared logic for multiple image streams, and employing descriptors or link lists to control the DMA fetching order, including for rotation.

Combination 1: US20060092320A1 in view of US5875351A and US6853385B1

This combination addresses the fundamental concept of DMA-controlled image fetching and processing, particularly with reduced intermediate buffering, and the blending of multiple image sources.

• US20060092320A1 (Nickerson Brian R) discloses a "System and method for transferring a video frame from memory into an on-chip buffer for video processing." This reference teaches transferring image data in portions (like tiles of a video frame) from main memory to a smaller, transient "on-chip buffer" for processing, thereby implicitly reducing the need for a large display storage frame buffer. A POSITA would understand that "video frames" consist of "image data" and that processing can occur on smaller segments.
• US5875351A (Compaq Computer Corporation) describes a "System for requesting access to DMA channel having address not in DMA registers by replacing address of DMA register with address of requested DMA channel." This patent provides the foundational concepts of advanced DMA channel management, including the use of descriptors or similar mechanisms to specify memory locations for DMA transfers. It directly teaches the "DMA fetching module including a DMA master and a plurality of DMA channels" and the configuration of "descriptors as to location of the source data."
• US6853385B1 (Broadcom Corporation) teaches a "Video, audio and graphics decode, composite and display system." This reference clearly describes "compositing," which directly encompasses the "blending" of images, including alpha blending, to create a single output.

Motivation for combination:
A POSITA, seeking to enhance efficiency and reduce the memory footprint of image/video processing systems (as highlighted by US20060092320A1's focus on an on-chip buffer rather than a full frame buffer), would be motivated to combine the efficient, granular DMA transfer mechanisms of US5875351A with the image compositing capabilities of US6853385B1. The objective would be to perform blending operations directly on the image data as it is efficiently fetched in portions (tiles), obviating the need to store entire images in a large intermediate buffer. US5875351A's precise DMA control enables fetching specific "tiles" of data in a desired order, crucial for real-time processing and memory reduction.

Obviousness of Claim 1 (System):
Claim 1 describes a system with a DMA fetching module (master and channels) fetching image tiles from diverse image sources, with a processor generating a combined image for display, and the tiles generated during fetching.

• The DMA fetching module (DMA master, multiple channels) fetching image tiles is taught by US5875351A (advanced DMA channel management, descriptors for location) and US20060092320A1 (transferring video frames in portions to an on-chip buffer for processing). A POSITA would readily apply the detailed DMA control of US5875351A to fetch smaller "tiles" of image data, consistent with the concept of processing portions of a frame from US20060092320A1.
• The processor generating a combined image (via blending) is taught by US6853385B1, which describes a "compositing" system. A POSITA would integrate this compositing function into the processing path of data fetched by the DMA module.
• The feature that image sources are of different resolution, orientation, and/or color space was a known challenge in the prior art, as acknowledged by US7924296's own background ("Some image processor requires an image display engine to render a variety of images, each having pixel data in a variety of formats. ... scaling ... to a desired output resolution may be required"). Handling diverse image attributes (scaling, color space conversion, rotation) using known techniques applied to fetched image tiles would be an obvious engineering decision for a POSITA.

Obviousness of Claim 12 (System):
Claim 12 specifies a system with a register for descriptors, a DMA fetching module, and a display blender for combining diverse images.

• The register providing descriptors and the DMA fetching module are directly taught by US5875351A.
• The display blender blending images is directly encompassed by the "compositing" function of US6853385B1.
• The processing of diverse image sources would be handled by conventional techniques, as discussed for Claim 1.

Obviousness of Claim 21 (Method):
This method claim outlines transferring images to DMA channels, fetching tiles, and blending them, with diverse image sources.

• The steps of transferring to DMA channels and fetching tiles are taught by US5875351A (DMA mechanisms) and US20060092320A1 (efficient data transfer for processing).
• Blending the fetched tiles is taught by US6853385B1 (compositing).
• The handling of diverse images would involve applying conventional scaling, color space conversion, and rotation as necessary before blending, a standard practice for a POSITA.

Obviousness of Claim 30 (Method):
This method claim details storing image data, configuring descriptors, reading link lists via a DMA master, reading/fetching tiles, image processing, and displaying, for diverse image source data.

• Storing image source data, configuring descriptors, reading a link list utilizing a DMA master, and reading/fetching a tile based on the descriptors are directly taught by US5875351A (DMA channel with descriptors for location, using DMA master) and US20050223136A1 (system and method for controlling DMA data transfer).
• Image processing the stored tile is broadly taught by US6944358B2 ("Image processor"), and specifically by US6853385B1 (compositing/blending). A POSITA would be motivated to perform various image processing operations (e.g., blending, scaling, color space conversion, rotation) on the fetched tiles to achieve a desired output.
• Displaying the image processed tile is an inherent final step in image processing systems.
• Diverse image source data would be addressed by applying known techniques for resolution, orientation, and color space handling.

Combination 2: US20060092320A1 in view of US5875351A, US6466226B1, and US5742796A

This combination explicitly addresses the "shared logic" and specific image transformation modules (color space, scaling) described in the patent.

• US20060092320A1 (Nickerson Brian R): Teaches transferring data from memory into an on-chip buffer for video processing.
• US5875351A (Compaq Computer Corporation): Provides robust DMA control using descriptors and multiple channels.
• US6466226B1 (Intel Corporation): Discloses a "Method and apparatus for pixel filtering using shared filter resource between overlay and texture mapping engines." This directly teaches the concept of "utilizing shared logic for multiple image streams."
• US5742796A (3Dlabs Inc. Ltd.): Describes a "Graphics system with color space double buffering" that performs color space conversion.

Motivation for combination:
A POSITA designing an efficient image processing system, motivated by US20060092320A1 to minimize buffer memory, would naturally employ the advanced DMA capabilities of US5875351A to fetch image data as needed. To efficiently process multiple image streams (necessary for blending different images), they would be motivated to use shared processing resources as taught by US6466226B1. Given that input images can have different color spaces, integrating a color space conversion module (as in US5742796A) into this shared logic would be a logical step to prepare all images for a common processing stage (e.g., blending). Similarly, incorporating scaling capabilities (a common image processing operation) would be obvious to handle different input resolutions.

Obviousness of Dependent Claims (e.g., 4, 5, 14, 15, 24, 25, 33, 34):
This combination would render obvious features like:

• Color space transformation module (Claims 4, 14, 24, 33): Directly taught by US5742796A, and its integration into a processing pipeline for diverse images would be obvious to a POSITA.
• Horizontal scaling module (Claims 5, 15, 25, 34): Horizontal scaling is a conventional image processing technique for adapting images of different resolutions. Its inclusion in an image processing system handling diverse sources would be a straightforward engineering choice, as acknowledged by the patent itself.
• The underlying principle of shared logic for multiple image streams is explicitly taught by US6466226B1. Applying this concept to shared modules for color space conversion and scaling would be a predictable design optimization for hardware and cost efficiency.

Combination 3: US20060092320A1 in view of US5875351A and general knowledge of image rotation

This combination specifically addresses the feature of fetching image data in a "rotated manner."

• US20060092320A1 (Nickerson Brian R): Teaches transferring data from memory into an on-chip buffer for video processing.
• US5875351A (Compaq Computer Corporation): Provides robust DMA control using descriptors and multiple channels, allowing flexible access to memory addresses.

Motivation for combination:
A POSITA, aware of the common requirement for image rotation in display systems and utilizing the flexible DMA control from US5875351A to fetch data efficiently (as in US20060092320A1), would be motivated to configure the DMA fetching order to directly support rotation. By defining the sequence of memory addresses fetched by the DMA through descriptors (as taught by US5875351A), an image could be effectively "rotated on the fly" during fetching. This approach eliminates the need for a separate, full buffer to store an intermediate rotated image, consistent with the objective of minimizing frame buffer usage. The patent's description notes that "The fetch order provides the rotation aspect of the invention," suggesting the method of rotation is primarily achieved through controlling the DMA fetching order, which is an application of known DMA control to a known image processing effect.

Obviousness of Dependent Claims (e.g., 7, 17, 26, 35 - rotated manner fetching):
These claims describe a fetching order that allows the DMA fetching module to transfer image data in a rotated manner. Given the flexible control over DMA fetching via descriptors (US5875351A) and the common need for image rotation, a POSITA would find it obvious to configure the DMA descriptors to fetch pixels in an order that results in a rotated image. This approach avoids storing a fully rotated image, further reducing intermediate memory requirements.

Conclusion

The independent claims (1, 12, 21, 30) of US7924296, as well as key dependent claims relating to specific image transformations (color space, scaling, rotation) and shared logic, would have been obvious to a POSITA in light of the combinations of prior art discussed. The motivation for combining these references arises from well-understood engineering goals: reducing memory bandwidth, improving processing efficiency, and handling diverse image inputs for compositing and display. These were recognized challenges in the field prior to the patent's filing. The patent appears to combine known elements (DMA control, image processing modules, blending, shared resources) in a predictable architectural arrangement to achieve expected results (e.g., reduced buffer usage, alpha blending of diverse images) by applying conventional solutions to recognized problems in a straightforward manner.

Patent Term Adjustments (PTA)

Patent Term Adjustment (PTA) is granted to compensate patent owners for delays incurred by the USPTO during the examination process. These delays can be categorized into "A-delays" (USPTO failing to take certain actions within specific timeframes), "B-delays" (USPTO failing to issue a patent within three years of the application filing date), and "C-delays" (delays due to interference, secrecy orders, or appeals). The total PTA is the sum of these delays, minus any overlapping days and applicant-caused delays.

For US patent 7924296, the Google Patents entry states an "Adjusted expiration" date of 2029-08-23. This indicates that Patent Term Adjustment has been applied, extending the original 20-year term from the filing date. To determine the precise PTA, one would typically need to review the "Issue Notification" from the USPTO for this patent, which provides a detailed calculation based on prosecution history.

Patent Term Extensions (PTE)

Patent Term Extension (PTE) is a separate statutory provision under 35 U.S.C. § 156, available for patents covering certain human drugs, food or color additives, animal drugs, veterinary biological products, and medical devices. PTE aims to restore a portion of the patent term lost while the covered product was undergoing regulatory review by agencies like the FDA, during which it could not be marketed.

Based on the technical nature of US patent 7924296 ("System and method for DMA controlled image processing"), which relates to image processing and display systems, it is highly unlikely to be eligible for Patent Term Extension. The subject matter does not fall within the categories of products (pharmaceuticals, medical devices, etc.) that require extensive regulatory review to qualify for PTE. There is no information in the provided patent text or search results to suggest that a PTE has been applied for or granted for this patent.

Continuation Applications

A continuation application is a new patent application filed while an earlier "parent" application is still pending. It claims the same invention as the parent application, using the same written description and drawings, but often with different claims seeking a different scope of patent protection. Continuation applications benefit from the priority date of the original parent application.

The Google Patents page for US7924296 lists its application number as US11/677,033 and notes that it is a "Priority to US11/677,033" and "Application filed by MtekVision Co Ltd" with the same filing date, 2007-02-20. This indicates that US7924296 itself is the original application (or the result of it), and the provided information does not explicitly list any subsequent continuation applications claiming priority from US7924296. The "Priority Applications (1)" and "Applications Claiming Priority (1)" sections on Google Patents refer to US11/677,033, which is the application leading to US7924296. To definitively confirm if any continuation applications were filed from US7924296 (i.e., making US7924296 a parent), a direct search within the USPTO Patent Center for continuity data linked to patent number 7924296 would be necessary.

Divisional Applications

A divisional patent application is a new patent application that claims an invention disclosed in an earlier "parent" application but not claimed or elected for examination in that parent. Divisionals are typically filed in response to a Restriction Requirement issued by the USPTO examiner, who determines that the original application claims more than one distinct invention. Like continuations, divisional applications retain the same filing date as the original application.

The provided patent text and Google Patents information for US7924296 do not explicitly state the existence of any divisional applications. Similar to continuation applications, a thorough review of the prosecution history for application US11/677,033 within the USPTO Patent Center (specifically checking for restriction requirements and subsequent divisional filings) would be required for a definitive answer.

Related Family Members

The patent family for US7924296, based on the provided information, primarily includes the published application US20080198170A1 and the granted patent US7924296B2, both originating from application US11/677,033. These are essentially different publication stages of the same underlying patent application.

• US11/677,033: The application number from which US7924296 was granted.
• US20080198170A1: The patent application publication for the same invention.
• US7924296B2: The granted patent.

The patent text also lists "Families Citing this family (7)" and "Cited By (4)", which indicate other patents or applications that have referenced US7924296, but these are not considered "related family members" in the sense of sharing the same priority chain (e.g., continuations, divisionals, or continuations-in-part). Rather, they are later inventions that have cited US7924296 as prior art.

Projected Expiration Date

The standard term for a U.S. utility patent filed on or after June 8, 1995, is 20 years from its earliest effective filing date, subject to any Patent Term Adjustments (PTA) or Patent Term Extensions (PTE).

For US patent 7924296:

• Filing Date: February 20, 2007.
• Original 20-year expiration (without adjustments): February 20, 2027.
• Adjusted Expiration (due to PTA): The Google Patents entry explicitly states the patent's "Legal status" as "Active, expires 2029-08-23".

Therefore, the projected expiration date for US patent 7924296 is August 23, 2029. This date reflects the effect of Patent Term Adjustment applied during prosecution.

Defensive Disclosure Document for US Patent 7924296

Patent Under Analysis: US7924296B2
Title: System and method for DMA controlled image processing
Inventor: Rabindra Guha
Current Assignee: Mila US Inc
Priority Date: 2007-02-20
Current Date: 2026-07-15

This document details several derivative variations of the core invention described in US patent 7924296. The purpose of this defensive disclosure is to establish prior art, thereby precluding or limiting future patentability of incremental improvements or alternative implementations by competitors. The derivations focus on expanding the scope of the original claims through material/component substitution, operational parameter expansion, cross-domain applications, integration with emerging technologies, and inverse/failure modes.

The derivatives are primarily based on Claim 1 of US7924296:
"A system for direct memory access (DMA) controlled image processing, the system comprising:
a DMA fetching module, the DMA fetching module being configured to fetch image data from a plurality of image sources, the DMA fetching module including a DMA master and a plurality of DMA channels, the plurality of DMA channels fetching a plurality of image tiles of pixel data in a certain fetching order, each of the plurality of DMA channels fetching the plurality of image tiles from at least one of the plurality of image sources, the DMA master controlling the fetching; and
at least one processor operatively coupled with the DMA fetching module, the at least one processor generating a combined image for display, the combined image including images from the plurality of image sources,
wherein the plurality of image tiles are generated when the plurality of DMA channels perform the fetching, and
wherein the plurality of image sources generate a plurality of the image data to be fetched, that are of different resolution, orientation, and/or color space."

---

Derivative Variations

1. Material & Component Substitution

Derivative 1.1: System for Neuromorphic DMA-Controlled Image Processing

Enabling Description:
This derivative implements the DMA-controlled image processing system using neuromorphic computing elements and memristive crossbar arrays for the DMA fetching module and a specialized spiking neural network (SNN) processor. The DMA master and channels are realized as dedicated neuromorphic cores, which directly interface with non-volatile memristive memory (e.g., Ag/a-Si:H/Pt or TiO2-based memristors) organized in crossbar arrays to store image data and descriptors. Fetching of image "tiles" is achieved by configuring synaptic weights in the neuromorphic DMA cores, allowing for associative memory access patterns that correspond to pixel groups or "tiles." The "certain fetching order" is determined by the firing sequence and connectivity of neurons within the neuromorphic DMA module, which can dynamically adapt based on descriptor patterns stored in the memristive memory. The "at least one processor" is an SNN accelerator, configured for tasks like sparse coding, pattern recognition, and ultimately, alpha blending. This SNN processor takes the fetched neuromorphic-encoded image tiles (e.g., spike trains representing pixel intensity and color) and processes them through layers of artificial neurons to generate a combined, blended image output, represented as a high-dimensional feature vector or another spike train for display. The inherent parallelism and event-driven nature of neuromorphic computing enable ultra-low power consumption and high efficiency for real-time image processing, particularly advantageous for handling diverse resolutions, orientations, and color spaces by applying adaptive synaptic scaling or neural transfer functions.

graph TD
    A[Neuromorphic Image Sources] --> B{Neuromorphic DMA Fetching Module};
    B --> C[Neuromorphic DMA Master];
    B --> D[Neuromorphic DMA Channels (N DMA)];
    C --> D;
    D -- Fetch Image Tiles (Spike Trains) --> E[Memristive Crossbar Memory];
    E --> D;
    D -- Transferred Neuromorphic Tiles --> F[Spiking Neural Network (SNN) Processor];
    F -- Generate Combined Image (Feature Vector/Spike Train) --> G[Display Interface (Decoder)];
    G --> H[Display];
    C -- Control Fetching Order (Synaptic Weights) --> E;
    E -- Descriptors (Memristive State) --> C;
    style B fill:#f9f,stroke:#333,stroke-width:2px;
    style F fill:#add8e6,stroke:#333,stroke-width:2px;

---

2. Operational Parameter Expansion

Derivative 2.1: Ultrafast, Multi-Spectral DMA Image Processing for Scientific Simulation

Enabling Description:
This derivative extends the system for DMA-controlled image processing to handle extreme operational parameters, specifically focusing on ultrafast, multi-spectral image acquisition and processing for scientific simulations, such as those found in high-energy physics or astrophysical observation. The "plurality of image sources" now includes high-speed photon detectors, terahertz scanners, or X-ray crystallography sensors, generating image data at rates exceeding terabits per second, with spectral depths far beyond visible light (e.g., 64-bit per pixel, 256 spectral bands). The "DMA fetching module" is implemented with a custom-designed, multi-gigabit/sec FPGA-based DMA controller utilizing HBM2e (High Bandwidth Memory 2 extended) as temporary tile buffers. Each "DMA channel" operates asynchronously at frequencies up to hundreds of GHz, optimized for burst transfers of irregularly-sized "image tiles" representing discrete spatio-temporal events or spectral slices. The "certain fetching order" is dynamically optimized by a predictive algorithm running on the DMA master, which anticipates regions of interest or data anomalies based on real-time feedback from initial tile processing, ensuring minimal latency for critical data. The "at least one processor" consists of a distributed array of GPU-accelerated processing units (e.g., NVIDIA Hopper H200 or AMD Instinct MI300 series) with dedicated optical interconnects. These processors perform on-the-fly de-noising, spectral unmixing, and volumetric reconstruction, generating a combined, multi-dimensional data visualization for immediate analysis or projection onto high-resolution scientific displays. The "different resolution, orientation, and/or color space" refers to varying spatial resolutions across different detectors (e.g., high-res central sensor, lower-res peripheral sensors), different angular orientations of detectors, and diverse spectral ranges (e.g., UV, visible, IR, X-ray) treated as distinct "color spaces."

graph TD
    A[Multi-Spectral Detectors (Tera-Hz)] --> B(High-Speed Optical Links);
    B --> C{FPGA-based DMA Controller (HBM2e)};
    C --> D[DMA Master (Predictive Algo)];
    C --> E[DMA Channels (Asynchronous)];
    E -- Fetch Image Tiles (TB/s) --> F[High-Bandwidth Memory (HBM2e)];
    F --> E;
    E -- Multi-Dimensional Tiles --> G[Distributed GPU Array (Optical Interconnect)];
    G -- Real-time Processing (De-noising, Spectral Unmixing) --> H[Scientific Visualization Engine];
    H --> I[Ultra-High-Res Display];
    D -- Dynamic Fetch Order --> C;
    style C fill:#f9f,stroke:#333,stroke-width:2px;
    style G fill:#add8e6,stroke:#333,stroke-width:2px;

---

3. Cross-Domain Application

Derivative 3.1: DMA-Controlled Image Processing for Industrial Robotics & Defect Detection

Enabling Description:
In industrial robotics, this system is applied for high-throughput, real-time defect detection and quality control. The "plurality of image sources" comprises multiple synchronized industrial cameras (e.g., high-resolution GigE Vision cameras, thermal cameras, 3D laser scanners) positioned around a conveyor belt, each capturing different aspects (e.g., visible surface, thermal anomalies, volumetric shape) of manufactured components. These cameras often have varying resolutions, frame rates, and data formats (e.g., RGB, grayscale, depth maps). The "DMA fetching module" is embedded within a robotic vision controller, directly pulling "image tiles" from the various camera buffers via high-speed interfaces (e.g., 10GigE, CoaXPress). The DMA master uses a link list of descriptors configured to fetch specific regions of interest (ROI) as "tiles," dynamically adapting the fetching order based on the detected presence and movement of components on the conveyor, allowing for "virtual rotation" or alignment of parts on-the-fly. The "at least one processor" is a specialized Vision Processing Unit (VPU) or industrial-grade GPU (e.g., NVIDIA Jetson AGX Orin) performing real-time image analytics. This processor blends the multi-modal image tiles (e.g., overlaying thermal data onto visible light images, or superimposing 3D deviation maps) to generate a "combined image" that highlights potential defects, material stress, or dimensional inaccuracies. This combined analytical output is then used by the robotic system for automated sorting, rejection, or feedback to manufacturing processes, rather than direct human display, though a display for monitoring can be included.

graph TD
    A[GigE Vision Camera (Visible)] -- Stream 1 --> B{Robot Vision Controller (DMA)};
    C[Thermal Camera (IR)] -- Stream 2 --> B;
    D[3D Laser Scanner (Depth)] -- Stream 3 --> B;
    B --> E[DMA Master (ROI Descriptors)];
    B --> F[DMA Channels];
    F -- Fetch Image Tiles (Multi-modal) --> G[VPU/Industrial GPU];
    G -- Real-time Defect Analysis --> H[Robotic Arm (Actuation)];
    G -- Combined Defect Map --> I[Operator HMI Display];
    E -- Dynamic Fetch Order (Component Tracking) --> F;
    style B fill:#f9f,stroke:#333,stroke-width:2px;
    style G fill:#add8e6,stroke:#333,stroke-width:2px;

Derivative 3.2: DMA-Controlled Image Processing for Autonomous Vehicle Sensor Fusion

Enabling Description:
In autonomous vehicles, the system is used for real-time sensor fusion to create a comprehensive environmental perception map. The "plurality of image sources" includes high-resolution optical cameras (visible and IR), LiDAR scanners generating point cloud data, and radar sensors providing range and velocity information. These sensors inherently provide data of vastly "different resolution, orientation, and/or color space" (e.g., 2D pixel arrays from cameras, 3D point clouds from LiDAR, sparse radar detections). The "DMA fetching module" is integrated into the vehicle's central domain controller, directly accessing data from raw sensor buffers. The DMA master, driven by predictive algorithms for vehicle trajectory and environmental context, configures "DMA channels" to fetch "image tiles" (e.g., specific camera regions, LiDAR slices, or radar detection clusters) in a "certain fetching order" that prioritizes critical data for immediate obstacle detection or lane keeping. This dynamic fetching order can also handle sensor misalignments or dynamic re-orientation (e.g., when a steerable LiDAR changes its scan pattern). The "at least one processor" comprises specialized hardware accelerators (e.g., custom ASICs for point cloud processing, AI inference engines for object detection) working in concert. These processors blend the fetched multi-modal data (e.g., projecting LiDAR points onto camera images, fusing radar detections with object bounding boxes from cameras) to generate a "combined image" that represents a semantic environmental map. This map is used by the vehicle's driving algorithms for navigation, path planning, and collision avoidance, with a low-latency output provided to an in-cabin display for driver awareness.

graph TD
    A[Optical Camera] -- Stream 1 --> B{Vehicle Domain Controller (DMA)};
    C[LiDAR Sensor] -- Stream 2 --> B;
    D[Radar Sensor] -- Stream 3 --> B;
    B --> E[DMA Master (Context-Aware Descriptors)];
    B --> F[DMA Channels];
    F -- Fetch Data Tiles (Multi-modal) --> G[Hardware Accelerators (ASIC/AI Engine)];
    G -- Sensor Fusion (Object Detection, Path Planning) --> H[Vehicle Control System];
    G -- Semantic Environmental Map --> I[In-Cabin Display];
    E -- Dynamic Fetch Order (Trajectory/Obstacle) --> F;
    style B fill:#f9f,stroke:#333,stroke-width:2px;
    style G fill:#add8e6,stroke:#333,stroke-width:2px;

Derivative 3.3: DMA-Controlled Image Processing for Multi-Modal Medical Imaging Fusion

Enabling Description:
In medical imaging, this system enables real-time fusion of disparate diagnostic images for enhanced visualization and surgical guidance. The "plurality of image sources" includes a patient's pre-operative MRI, CT scans, real-time ultrasound, and endoscopic video feeds. These sources inherently present "different resolution, orientation, and/or color space" (e.g., volumetric MRI data, 2D slices from CT, live ultrasound frames, RGB endoscopic video). The "DMA fetching module" resides in a medical imaging workstation or surgical navigation system, optimized for accessing large medical datasets. The DMA master utilizes anatomical landmark registration data to configure "DMA channels" to fetch "image tiles" from the various sources in a "certain fetching order" that aligns them spatially and temporally for fusion. This fetching order dynamically compensates for patient movement or probe adjustments during a procedure. The "at least one processor" is a high-performance medical GPU (e.g., specifically certified for medical applications) augmented with hardware for fast volumetric rendering. This processor blends the fetched multi-modal image tiles (ee.g., overlaying real-time ultrasound onto a pre-operative 3D MRI volume, or fusing endoscopic video with CT reconstructions) to generate a "combined image" as a comprehensive, interactive 3D visualization. This combined image provides surgeons with augmented reality guidance, assisting in precise instrument placement and tumor localization, thereby minimizing invasiveness and improving outcomes.

graph TD
    A[Pre-op MRI (Volumetric)] -- Data Stream 1 --> B{Medical Workstation (DMA)};
    C[Pre-op CT (Slices)] -- Data Stream 2 --> B;
    D[Real-time Ultrasound] -- Data Stream 3 --> B;
    E[Endoscopic Video] -- Data Stream 4 --> B;
    B --> F[DMA Master (Registration Data)];
    B --> G[DMA Channels];
    G -- Fetch Image Tiles (Anatomically Aligned) --> H[Medical GPU (Volumetric Rendering)];
    H -- Real-time Fusion (AR Guidance) --> I[Surgical Navigation System];
    H -- Interactive 3D Visualization --> J[High-Res Medical Display];
    F -- Dynamic Fetch Order (Patient/Probe) --> G;
    style B fill:#f9f,stroke:#333,stroke-width:2px;
    style H fill:#add8e6,stroke:#333,stroke-width:2px;

---

4. Integration with Emerging Tech

Derivative 4.1: AI-Optimized DMA-Controlled Image Processing with Real-time IoT Context

Enabling Description:
This derivative integrates AI-driven optimization for the DMA fetching and processing, combined with real-time contextual data from IoT sensors. The "plurality of image sources" includes conventional cameras, but also specialized IoT vision sensors (e.g., low-power event cameras, thermal IoT sensors) distributed across an environment, each with potentially different resolutions, formats, and orientations. The "DMA fetching module" is dynamically managed by an AI-powered DMA master. This AI master (e.g., a reinforcement learning agent) observes the content of incoming "image tiles," system load, and contextual information from a network of "IoT sensors" (e.g., motion detectors, ambient light sensors, presence sensors, environmental parameters) to predict optimal fetching orders and resource allocation. For example, if an IoT motion sensor detects activity in a specific area, the AI-DMA master might prioritize fetching higher-resolution tiles from cameras covering that area, dynamically adjusting the "certain fetching order" and even the scaling parameters for less critical areas. The "at least one processor" includes an AI inference engine (e.g., specialized NPU or FPGA) that performs initial image processing (e.g., object recognition, event detection) on the fetched tiles. This AI processor then collaborates with a display processor to generate a "combined image" for display, which might include augmented overlays of IoT sensor data (e.g., temperature readings, object labels) directly onto the visual stream, or a synthesized view that intelligently blends disparate data streams based on real-time relevance determined by the AI. This allows for intelligent resource management and context-aware image rendering.

graph TD
    A[IoT Vision Sensors] --> B{AI-Driven DMA Fetching Module};
    C[Conventional Cameras] --> B;
    D[IoT Context Sensors] --> E[Contextual Data Aggregator];
    E -- Real-time Feedback --> F[AI DMA Master (RL Agent)];
    B --> F;
    B --> G[DMA Channels];
    G -- Fetch Image Tiles (Dynamic Priority) --> H[AI Inference Engine / NPU];
    H -- Processed Tiles + Context --> I[Display Processor];
    I -- Combined Context-Aware Image --> J[Display];
    F -- Optimal Fetching Orders --> G;
    style B fill:#f9f,stroke:#333,stroke-width:2px;
    style H fill:#add8e6,stroke:#333,stroke-width:2px;

Derivative 4.2: Blockchain-Verified DMA-Controlled Image Processing for Authenticated Visual Data

Enabling Description:
This derivative focuses on ensuring the integrity and provenance of image data through blockchain integration within the DMA-controlled processing pipeline. The "plurality of image sources" (e.g., surveillance cameras, forensic imaging devices, industrial inspection cameras) generates image data that requires verifiable authenticity. Each "image tile" fetched by the "DMA fetching module" has an associated cryptographic hash generated at the source or during initial DMA transfer. This hash, along with metadata (e.g., timestamp, sensor ID, fetching order parameters), is added to a local Merkle tree, and the root hash of this tree is periodically committed to a distributed ledger (blockchain). The "DMA master" is equipped with a hardware security module (HSM) that verifies the integrity of incoming descriptors and generated hashes before initiating data fetches. When "image tiles" are fetched and processed by the "at least one processor" (e.g., a secure image processor), intermediate processing steps (e.g., scaling, color transformation, blending parameters) are also hashed and their hashes linked into the blockchain, creating an immutable audit trail. The "combined image" generated for display includes a verifiable watermark or digital signature derived from the blockchain, assuring the viewer of the image's authenticity and an unadulterated processing history. Any attempt to tamper with the image data or processing parameters would result in a hash mismatch, invalidating the blockchain record and indicating data corruption.

graph TD
    A[Authenticated Image Sources] --> B{DMA Fetching Module (HSM)};
    B --> C[DMA Master (Hash Verification)];
    B --> D[DMA Channels];
    D -- Fetch Image Tiles (Hashed) --> E[Image Data (with Hashes)];
    E -- Hashes + Metadata --> F[Local Merkle Tree];
    F -- Root Hash --> G[Blockchain Ledger];
    D -- Fetched Tiles --> H[Secure Image Processor];
    H -- Processed Tiles (Hashed) --> I[Output Image (Watermarked/Signed)];
    I --> J[Display];
    C -- Validated Descriptors --> D;
    style B fill:#f9f,stroke:#333,stroke-width:2px;
    style H fill:#add8e6,stroke:#333,stroke-width:2px;
    style G fill:#ccffcc,stroke:#333,stroke-width:2px;

---

5. The "Inverse" or Failure Mode

Derivative 5.1: Fail-Safe DMA-Controlled Image Processing with Graceful Degradation

Enabling Description:
This derivative describes a DMA-controlled image processing system designed with fail-safe mechanisms and graceful degradation capabilities. In the event of resource constraints (e.g., low power, memory corruption, processor overload) or component failure, the system automatically transitions to a "low-power" or "limited-functionality" mode to maintain essential display or processing, rather than outright failure. The "DMA fetching module" includes a power management unit and a health monitoring subsystem. The "DMA master" is augmented with a "Failure Mode Manager (FMM)" that continuously assesses system health and available resources.
In a low-power mode, the FMM dynamically reconfigures DMA descriptors to fetch "image tiles" at significantly reduced resolution (e.g., quarter resolution) and/or from a subset of "image sources," potentially skipping non-critical sources entirely. The "certain fetching order" might prioritize essential overlay information (e.g., safety warnings) over background imagery. The DMA channels themselves can be individually disabled or clocked down to conserve power.
Upon detecting a critical failure (e.g., a specific DMA channel failure, or corruption in a source image memory area), the FMM reconfigures the DMA fetching to skip the faulty channel/source, fetching data from redundant sources if available, or substituting corrupted tiles with a placeholder (e.g., black, gray, or previous valid frame). The "at least one processor" (e.g., an FPGA or ASIC) is designed with redundant processing lanes or configurable logic. It automatically scales down image processing complexity (e.g., simpler blending algorithms, reduced color depth, disabling advanced filters like gamma correction or complex scaling interpolators) to maintain a minimum viable output. The "combined image" for display might exhibit reduced visual fidelity (e.g., lower resolution, fewer blended layers, simpler color representation) but remains functional and provides critical information, accompanied by system status indicators to alert users of the degraded mode.

stateDiagram-v2
    [*] --> Normal_Operation
    Normal_Operation --> Low_Power_Mode: Low Power Event / Resource Constraint
    Normal_Operation --> Degraded_Mode: Component Failure / Data Corruption
    Low_Power_Mode --> Normal_Operation: Power Restored / Resources Available
    Degraded_Mode --> Normal_Operation: Fault Remedied / System Reset
    Low_Power_Mode --> Degraded_Mode: Further Failure in Low Power
    Degraded_Mode --> Critical_Failure_Mode: Unrecoverable Errors

    state Normal_Operation {
        DMA_Full_Res_Fetch --> Processor_Full_Features: Full Resolution, All Sources
    }

    state Low_Power_Mode {
        DMA_Reduced_Res_Fetch --> Processor_Limited_Features: Reduced Resolution, Subset Sources
    }

    state Degraded_Mode {
        DMA_Fault_Tolerant_Fetch --> Processor_Reduced_Complexity: Skip Faults, Simpler Blending
    }

    state Critical_Failure_Mode {
        Error_Display --> System_Shutdown: Display Warning, Cease Ops
    }

    DMA_Master_with_FMM --> Normal_Operation
    DMA_Master_with_FMM --> Low_Power_Mode
    DMA_Master_with_FMM --> Degraded_Mode
    DMA_Master_with_FMM --> Critical_Failure_Mode

---

Combination Prior Art Scenarios with Open-Source Standards

These scenarios combine the teachings of US7924296 (DMA-controlled fetching of diverse image tiles for processing) with existing open-source standards, demonstrating how the core inventive concept would be obvious when integrated into standard frameworks.

1. DMA-Controlled Image Processing with OpenGL ES and OpenCL

Scenario: A system implementing DMA-controlled image processing as described in US7924296, specifically for mobile or embedded graphics.

Combination: The DMA fetching module (from US7924296) is used to directly transfer image tiles from various sources (e.g., camera sensor buffers, video decoders, application-generated textures) that may have different resolutions, orientations, or color spaces. This DMA module populates textures managed by OpenGL ES (Open Graphics Library for Embedded Systems), an open-source standard API for rendering 2D and 3D graphics on embedded systems. The "at least one processor" (or a graphics processing unit (GPU) within a SoC) then utilizes OpenCL (Open Computing Language), an open-source standard for parallel programming of heterogeneous platforms, to perform the image processing (e.g., alpha blending, scaling, color space conversion) directly on these fetched tiles/textures in GPU memory. The output of the OpenCL kernel is then rendered using OpenGL ES onto a display surface. The DMA fetching mechanism efficiently provides data to the GPU's texture memory, bypassing traditional CPU-driven transfers and intermediate frame buffers, while OpenGL ES and OpenCL provide the standardized, vendor-agnostic framework for rendering and general-purpose GPU compute required for diverse image processing.

2. DMA-Controlled Image Processing for GStreamer Pipeline Optimization

Scenario: A multimedia processing system requiring efficient handling and blending of multiple video streams.

Combination: The core DMA fetching module and processing architecture of US7924296 is integrated as a custom "GStreamer Element" within a GStreamer pipeline. GStreamer is an open-source multimedia framework for creating streaming media applications. Each "image source" (e.g., IP camera feeds, local video files, screen captures) is represented by a GStreamer source element. The DMA fetching module acts as a specialized GStreamer filter element, dynamically pulling "image tiles" from the various upstream GStreamer buffers (which can represent different resolutions, formats, or rotated states). The "certain fetching order" is controlled by a GStreamer message or event, allowing the DMA master to respond to pipeline state changes or user commands (e.g., dynamically changing which video feed is prioritized). The "at least one processor" performs operations like alpha blending, scaling, and color space conversion directly on the fetched tiles. This processed output is then pushed downstream into other GStreamer elements for encoding, rendering (e.g., using glimagesink), or network transmission. The DMA-controlled tiling and processing within a GStreamer element significantly reduces memory copies and CPU overhead, aligning with GStreamer's goal of efficient data flow.

3. DMA-Controlled Image Processing in a Linux Framebuffer Environment

Scenario: An embedded Linux system requiring efficient display of multiple overlapping graphical layers.

Combination: A Linux-based embedded system utilizes the DMA-controlled image processing approach of US7924296 to manage layers within the Linux framebuffer device (/dev/fbX). The "plurality of image sources" could include a graphical user interface (GUI) layer (e.g., rendered by Wayland/Weston), a video playback layer, and an overlay for system information. These layers inherently possess "different resolution, orientation, and/or color space." The DMA fetching module is implemented as a kernel-level driver, exposing its capabilities through a standard DMA-BUF (Direct Memory Access Buffer) framework in Linux. DMA-BUF allows different devices (like the DMA fetching module and the display controller) to share memory buffers without intermediate copies. The DMA master directly configures transfers of "image tiles" from various source memory regions (managed as DMA-BUF objects) in a "certain fetching order" that corresponds to desired blending and composition. The "at least one processor" (e.g., a display controller's hardware composer or a dedicated image processing block) performs the alpha blending and other image transformations on these directly fetched tiles, writing the final "combined image" into the display controller's scanout buffer (which might also be a DMA-BUF shared memory region). This leverages the Linux kernel's existing memory sharing and device interaction mechanisms for efficient, low-latency display composition without heavy reliance on CPU-intensive graphics libraries.