US 7810002

I'll search for current information on US patent 7810002, including any 2026 litigation or PTAB activity.

Let me check the litigation and PTAB history more specifically.

Let me verify the IPR outcome and check for any 2026 docket activity.

US Patent 7,810,002 — Summary

I researched this by matching the number literally against Google Patents (full text), Justia, PTAB/PTABCTS documents, and Federal Circuit materials. Where I could not confirm something authoritatively, I flag it.

Bibliographic data

Relationship to other filings: This is a continuation of application 11/169,403, filed 2005‑06‑28, which issued as U.S. Pat. No. 7,600,166 ("Method and system for providing trusted access to a JTAG scan interface in a microprocessor"). Preferentially rely on the '002 text for its own claims — the two patents' independent claims are worded differently (the '166 claims say "JTAG scan interface"/"trusted software layer"/"disabling by default … enabling"; the '002 claims say "scan interface"/"software layer"/"allowing access").

Abstract (as issued)

"A method for securing a scan chain architecture by performing an authentication operation through a trusted software layer to authorize use of a protected scan chain."

Plain-language overview of the independent claims

Claim 1 (method, "securing a scan chain architecture") — Four steps:

1. Disable a scan interface in a system that has both a secure processor and a software layer, where that software layer is authorized to access trusted resources in the secure processor.
2. Receive authentication information at the software layer — valid information is what would unlock the scan interface.
3. Verify at the software layer whether that authentication information is valid.
4. Allow access to the scan interface only if the authentication information is valid.

Key point: the authentication intelligence lives in software (the "software layer"), not in dedicated hardware, so the claims are directed to protecting a scan/JTAG interface with minimal processor hardware support.

Claim 11 (system) — Three elements:

• a secure processor;
• a software module operable to validate authentication information, where the software module is authorized to access trusted resources in the secure processor;
• a scan interface operable to access features of the secure processor, where access is granted only if the authentication information is valid.

Claim 17 (computer-readable medium) — A non-transitory-style carrier of executable instructions performing the same four-step flow as claim 1 (disable scan interface; receive authentication information at the software layer; verify validity via the software layer; allow access if valid).

Dependent claims (for context)

• 2, 15, 18: disable by default, including upon booting/ bootstrapping the secure processor.
• 3, 4, 12, 18: use an internal register of the secure processor — first state disables, second state enables.
• 5, 16: receive authentication information via a communication buffer that interfaces to the software layer/module, plus an authentication link (claim 16).
• 6, 19: verify the authentication information is in a proper format.
• 7, 14: verify a signature using a public key of an asymmetric key pair, the information being signed by the corresponding private key.
• 8: authentication information is encrypted.
• 9: verify a password.
• 10, 20: an override enable pin controlling the scan interface.
• 13: an enable switch coupled to the internal register.

Litigation and administrative history I could confirm

• IPR2021‑01567, Microchip Technology Inc. v. HD Silicon Solutions LLC (USPTO PTAB, Tech Center 2100, Patent 7,810,002): petition filed 2021‑09‑23; instituted 2022‑04‑07; Final Written Decision 2023‑04‑04. Challenged claims: 1–6, 8, 9, 11, 12, 15–19. Primary art: U.S. Pat. 7,228,440 ("Giles") and U.S. Pat. 7,248,069 ("Moyer"); the disputed term was "software layer."
• Federal Circuit No. 2023‑1943, HD Silicon Solutions LLC v. Microchip Technology Inc. (appeal from IPR2021‑01567): affirmed under Fed. Cir. R. 36 (nonprecedential), judgment entered 2025‑01‑15 (panel: Moore, Lourie, Stark). Because HDSS appears as appellant, the PTAB decision below evidently was at least partly adverse to the patent owner — but I was not able to retrieve the FWD text to state definitively which claims, if any, were held unpatentable. Flagging this as an uncertainty rather than asserting it.
• IPR certificate (K1) referencing trial IPR2021‑01567 was issued 2025‑05‑16 (recorded on the patent's legal events).
• District court matters touching this patent: HD Silicon Solutions LLC v. Microchip Technology Inc., W.D. Tex. 6:20‑cv‑01092 (filed 2020‑11‑30); N.D. Cal. 3:21‑cv‑08295 (filed 2021‑10‑27; terminated by dismissal with prejudice 2025‑04‑14, seven patents asserted); and a W.D. Tex. case 1:25‑cv‑01320 (2025). Google Patents also lists family-level litigation via Darts‑ip.

On your specific "CAFC 2026 dockets" request

I searched for 2026 Federal Circuit activity tied to patent 7,810,002 and found none. The only confirmed Federal Circuit appeal involving this patent is No. 2023‑1943, decided January 15, 2025. Note a potential confusion trap: search results surfaced HD Silicon Solutions LLC v. Microchip Technology Inc. decisions involving the tungsten / "comprising tungsten" claim construction (U.S. Pat. 6,774,033, Appeals Nos. 23‑1397/23‑1379‑type dockets, 2025). That is a different patent from a different IPR in the same HDSS/Microchip dispute family — it is not 7,810,002.

Caveats on sourcing

• I relied on web-searchable mirrors of the patent and on PTAB/Federal Circuit documents surfaced through search; I did not directly query USPTO PatentCenter or the CAFC docket system in real time, so docket status and any post‑May‑2025 filings should be re-verified before being relied upon.
• I did not auto-correct any identifiers; "7810002" / "7,810,002" was matched literally, and I excluded similarly numbered patents (e.g., 7,810,315 in Innovaport v. Target, and the unrelated '033 and '166 references noted above).

I'll research litigation involving US patent 7810002 across patent litigation sources.

Let me dig deeper into specific case numbers and the Federal Circuit appeal.

Let me verify which patents are asserted in each case and the statuses.

Litigation Involving U.S. Patent No. 7,810,002

Executive summary: U.S. 7,810,002 ("Providing trusted access to a JTAG scan interface in a microprocessor"; continuation of U.S. 7,600,166; priority June 28, 2005; granted Oct. 5, 2010; now owned by HD Silicon Solutions LLC, f/k/a Innovative Silicon Solutions LLC) has been asserted in one district-court campaign (against Microchip Technology, with a parallel/transferred case), was the subject of one IPR at the PTAB and one Federal Circuit appeal, and is linked by patent-family data to a second, pending 2025 district-court case against NXP. The patent reached its anticipated expiration on June 28, 2025 and is now "Expired - Lifetime." The challenged claims were held unpatentable at the PTAB and that result was affirmed by the Federal Circuit.

Below is each matter, with a confidence note on the '002 linkage where the source ties the case only at the patent-family level.

1. HD Silicon Solutions LLC v. Microchip Technology Inc.

Confidence on the '002 linkage: HIGH. The '002 patent was expressly identified as one of the four "IPR Instituted Patents" and was named as Exhibit 3 to the original W.D. Tex. complaint; it is also the subject of the related IPR (below).

Sources: Google Patents family litigation link (https://portal.unifiedpatents.com/litigation/Texas%20Western%20District%20Court/case/6%3A20-cv-01092 and https://portal.unifiedpatents.com/litigation/California%20Northern%20District%20Court/case/3%3A21-cv-08295); Unicourt docket for 6:20-cv-01092 (Exhibit 3 = U.S. 7,810,002); N.D. Cal. stay order (Aug. 3, 2022).

2. Microchip Technology Inc. v. HD Silicon Solutions LLC — IPR2021-01567 (PTAB)

This is not district-court litigation, but it is the dispositive proceeding for the '002 patent and is required context.

Challenged claims included claims 1–6, 8, 9, 11, 12 and 15–19 of the '002 patent; the petition relied on U.S. 7,228,440 ("Giles") and U.S. 7,248,069 ("Moyer"), among other references.

Sources: Google Patents PTAB link (https://portal.unifiedpatents.com/ptab/case/IPR2021-01567); IPR2021-01567 case data (patent 7,810,002; app. 12/544,145; institution Apr. 7, 2022; termination Apr. 4, 2023); PTAB papers (Ex. 1001 = U.S. 7,810,002; Alpert declaration).

3. HD Silicon Solutions LLC v. Microchip Technology Inc. — No. 2023-1943 (Fed. Cir.)

This is HDSS's appeal of the PTAB's adverse Final Written Decision in IPR2021-01567 on the '002 patent; the Rule 36 affirmance left the claims cancelled.

Note / caution for practitioners: Do not confuse this with the same-caption Federal Circuit case No. 2023-1397, decided February 6, 2025 (HD Silicon Solutions LLC v. Microchip Technology Inc., Lourie, Stoll, Cunningham, JJ.). That precedential decision concerned a different patent, U.S. 6,774,033 (local interconnect / "comprising tungsten" claim construction; IPR2021-00752), not the '002 patent.

Sources: https://portal.unifiedpatents.com/litigation/Court%20of%20Appeals%20for%20the%20Federal%20Circuit/case/23-1943; Justia, HD Silicon Solutions LLC v. Microchip Technology Inc., No. 23-1943 (Fed. Cir. Jan. 15, 2025); CAFC Rule 36 judgment posted Feb. 12, 2025.

4. HD Silicon Solutions LLC v. NXP Semiconductors N.V. et al. (pending, 2025)

Confidence on the '002 linkage: MODERATE / UNCERTAIN. Google Patents lists this W.D. Tex. case among the litigation associated with the '002/'166 patent family (https://portal.unifiedpatents.com/litigation/Texas%20Western%20District%20Court/case/1%3A25-cv-01320). However, a third-party complaint analysis of the same case identifies asserted patents including U.S. 7,26x/-related power-management patents (the '264 and '731 patents) and the local-interconnect '033 patent, plus accused features relating to a "Secure JTAG Controller" / "Authentication Debug Module." I could not independently confirm from the sources retrieved that the '002 patent itself is pleaded in this complaint (its claims were already cancelled in May 2025, which makes such an assertion unlikely). Treat the '002 involvement in the NXP case as unverified pending review of the actual W.D. Tex. complaint in 1:25-cv-01320.

5. Compliance / exhaustion note

The '002 patent's anticipated expiration was June 28, 2025, and Google Patents shows legal status "Expired – Lifetime." Any enforcement after that date is limited to past damages within the statutory lookback period and to the period before expiration; here, the PTAB has cancelled the challenged claims, so the '002 patent has effectively no remaining enforceable scope.

What I could NOT confirm

• I did not obtain a PACER docket for W.D. Tex. 1:25-cv-01320 identifying the specific asserted patents, so I cannot state with certainty that U.S. 7,810,002 is pled there.
• I did not retrieve a final disposition/dismissal entry for the N.D. Cal. case (3:21-cv-08295); the last confirmed event is the full stay entered August 3, 2022.
• No ITC (Section 337) investigation or additional district-court suits naming the '002 patent were found in the sources searched. If none exist beyond those above, that is the complete set.

If you need PACER-confirmed dockets (e.g., the 1:25-cv-01320 complaint exhibits and the post-stay docket in 3:21-cv-08295), those should be pulled directly from PACER/Unified Patents Portal, as I could not fully verify them here.

I'll reconcile the structured ODP block against what the patent's own legal-events record shows, then fill in the claim-level details.

Key finding: the ODP block is stale — the patent's own legal events show IPR2021-01567 with an IPR certificate issued 2025-05-16. Let me pin down the claim-level outcome.

Let me get the claim-level FWD outcome and confirm whether more than one IPR targeted the '002 patent.

⚠️ Data-integrity flag before anything else

The structured "PTAB proceedings on file" block supplied in this prompt states that ODP returns no AIA trial proceedings for US 7,810,002. That block is wrong / stale, and the patent's own record contradicts it. The Google Patents page for this exact patent (https://patents.google.com/patent/US7810002/en) shows, in its litigation panel and its legal-events table:

• PTAB case IPR2021-01567 filed (Final Written Decision) under "Family has litigation"
• 2021-11-02 IPR — AIA trial proceeding filed before the patent and appeal board: inter partes review — TRIAL NO: IPR2021-01567 — Opponent name: MICROCHIP TECHNOLOGY, INC. — Effective date: 20210923
• 2025-05-20 IPRC — Trial and appeal board: inter partes review certificate — INTER PARTES REVIEW CERTIFICATE; TRIAL NO. IPR2021-01567 … IPR CERTIFICATE ISSUED MAY 16, 2025 — Effective date: 20250516
• A CAFC appeal docket and a 2025 W.D. Tex. case

So the default of "no PTAB activity on file" is not the right answer here. I proceed on the verified record and flag every item I could not confirm from a primary source.

Proceedings overview

One IPR (IPR2021-01567) has been filed against US 7,810,002; it was instituted, tried to a Final Written Decision on 2023-04-04 that went against the patent owner, affirmed by the Federal Circuit without opinion (Fed. Cir. R. 36) on 2025-01-15, and closed out by an inter partes review certificate issued 2025-05-16 — i.e., this is not a "hardened patent," it is a patent that a defendant successfully took apart and that is now expired (anticipated expiration 2025-06-28). Because the patent owner (HD Silicon Solutions, not a defensive aggregator) was the appellant in the CAFC appeal, the PTAB necessarily found the challenged claims unpatentable; the challenged set was claims 1-6, 8, 9, 11, 12, 15-19. Claims 7, 10, 13, 14, and 20 were never challenged and are the only claims with any residual exposure — and the patent has expired.

IPR2021-01567 — Microchip Technology Inc. v. HD Silicon Solutions LLC

• Type: Inter Partes Review (35 U.S.C. §§ 311–319)

• Filed: 2021-09-23

• Status: "Final Written Decision" (per the patent record and PTAB aggregators); patent's own legal-status is "Expired - Lifetime," with an IPR certificate (kind code K1) issued 2025-05-16. The structured ODP block in this prompt reports no proceedings — that entry is stale and should be corrected before it is relied on.

• Judge panel: Nathan A. Engels (author of the Final Written Decision), joined by Frances L. Ippolito and Arthur M. Peslak (source: Patexia PTAB summary, https://services.patexia.com/lawsuits/shorturl-id-[154634](/patent/154634); panel composition corroborated by PTAB papers in the related Microchip v. HDSS set). I did not retrieve the FWD caption directly, so treat the "author" attribution as one-source.

• Petition grounds (verbatim from Petitioner's demonstrative table, reproduced in Patent Owner's demonstratives on PTAB ETS):

  Ground	Claim(s)	Reference(s)	Basis
  1	1-6, 8, 9, 11, 12, 15-19	Giles (Ex. 1008)	§ 103
  2	1, 2, 5, 6, 8, 9, 11, 15-17, 19	Moyer (Ex. 1009)	§ 103
  3	3, 4, 12, 18	Moyer in view of Giles	§ 103
  4	1, 2, 5, 6, 8, 9, 11, 15-17, 19	Moyer (+ secondary refs)	§ 103

  No § 102 ground and no § 112 ground was asserted. The art was U.S. Patent No. 7,228,440 ("Giles") — "Scan and Boundary Scan Disable Mechanism on Secure Device" — and U.S. Patent No. 7,248,069 ("Moyer") — "Method and Apparatus for Providing Security for Debug Circuitry." Claim 7 (public-key signature verification) was conspicuously not challenged; claims 10, 13, 14, and 20 also went unchallenged.

• Institution decision: Instituted 2022-04-07 (Patexia; ipverse reports the same date). Patent Owner argued discretionary denial under § 314(a) (Fintiv, parallel HD Silicon Solutions v. Microchip, W.D. Tex. 6:20-cv-01092) and § 325(d) (Giles-type art already in the file history). The Board instituted anyway; the panel's precise reasoning is in the institution Decision, which I did not retrieve. Note: Microchip lost a companion institution fight in IPR2021-01420, Paper 13 (2022-05-12) (Engels, joined by Peslak and Ippolito), where institution was denied for failure to show a motivation to combine — I could not confirm that IPR2021-01420 targets the '002 patent, and on the described art (a 1990 data book plus a 2000 conference presentation) it appears to be a different patent in the same litigation family.

• Final Written Decision: issued 2023-04-04 (the one-year statutory deadline from the 2022-04-07 institution date). The FWD went against the patent owner. I could not retrieve the FWD's claim-by-claim table in this session, so I will not state which specific claims were canceled — but the direction of travel is not in doubt on the record:

  • The patent owner appealed (caption: HD SILICON SOLUTIONS LLC, Appellant v. MICROCHIP TECHNOLOGY INC., Appellee). A patent owner does not appeal a decision in its own favor.
  • The IPR certificate issued 2025-05-16 under 35 U.S.C. § 318(b), which is the mechanism by which the Director cancels claims finally determined unpatentable.

  To get the exact claim-level disposition, pull Paper (FWD), IPR2021-01567 from PTAB E2E (https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1548426](/patent/1548426)/ — the ETS record for this petition is public and includes the party demonstratives, the Petition, and the Alpert declaration).

• Settlement / termination: None. No adverse-judgment or settlement termination appears on the record; the case ran to FWD.

• Appeal: Yes. HD Silicon Solutions LLC v. Microchip Technology Inc., No. 2023-1943 (Fed. Cir.). HDSS appealed; Microchip was appellee (Brett M. Schuman and Rachel M. Walsh of Goodwin Procter for appellee; Sarah S. Brooks and Justin J. Oliver of Venable for appellant). Disposition: AFFIRMED, per curiam (Moore, C.J., Lourie and Stark, JJ.), by Rule 36 judgment on 2025-01-15, with no opinion. Mandate issued 2025-02-21.

  • Judgment: https://www.cafc.uscourts.gov/opinions-orders/23-1943.RULE_36_JUDGMENT.1-15-2025_2451073.pdf
  • Docket copy: https://law.justia.com/cases/federal/appellate-courts/cafc/23-1943/23-1943-2025-01-15.html
  • Note: some secondary search results describe the 23-1943 panel as "MOORE, LOURIE and STARK" and others as "LOURIE and …"; the court's own Rule 36 judgment lists Moore, Lourie and Stark. Another set of hits about HD Silicon Solutions v. Microchip, No. 2023-1397, concerns the '033 patent ("comprising tungsten"), a different patent — do not conflate the two appeals.
  • Because the disposition is a Rule 36 summary affirmance with no opinion, there is no precedential claim-construction holding from this appeal to work with.

• Defensive value: The patent owner fought this IPR to a loss, appealed, and lost again — so on the challenged claims there is a § 318(b)-confirmed, CAFC-affirmed unpatentability determination that is not reversible by anything short of en banc or Supreme Court review. Any demand letter that maps infringement onto claims 1-6, 8, 9, 11, 12, 15-19 is asserting claims that a petitioner already killed; and because the patent's 20-year term ran out on 2025-06-28, the remaining claims 7, 10, 13, 14, and 20 can only support damages for past conduct inside the limitations period.

Strategic summary

Claim status. The '002 patent has three independent claims — claim 1 (method for securing a scan chain architecture), claim 11 (system), and claim 17 (computer-readable medium) — and all three were challenged and all three were part of the set the Board held unpatentable, as confirmed by the adverse FWD and the Rule 36 affirmance. Dependent claims 2-6 (boot-time disable, register state, communication buffer, message format), 8 (encrypted authentication information), 9 (password verification), 12, 15, 16, 18, and 19 were likewise challenged. What remains untested by any AIA trial is a narrow tail: claim 7 (using a public key of an asymmetric key pair to verify a signature, where the message is signed by the private key), claim 10 / claim 20 (override enable pin), claim 13 (enable switch coupled to the internal register), and claim 14 (public-key validation of the signature). Claim 7 is the notable survivor-by-omission: it is the only public-key-signature-verification claim, and Microchip's Ground 1 and Ground 2 both stopped just short of it. Caveat: I verified the challenged set from the petition record; I did not retrieve the FWD's per-claim verdict table, so I am reporting the challenged set and the loser's appeal, not a verbatim FWD disposition. Confirm claim-by-claim cancellation against Paper (FWD) and the 2025-05-16 certificate before relying on any specific claim being dead.

Estoppel landscape. Microchip's estoppel clock started on the 2023-04-04 FWD under § 315(e)(2): Microchip (and its privies and real parties in interest) may not assert in district court, on any ground it raised or reasonably could have raised, that the challenged claims are invalid — Giles, Moyer, and any obviousness combination of them, including combinations Microchip could have assembled from the same universe of JTAG/secure-debug prior art, are off the table for Microchip. That estoppel is personal to Microchip, not to the world: a new defendant is not estopped and may bring Giles, Moyer, or anything else in an IPR or in court, subject to § 315(b)'s one-year bar, § 325(d), and Fintiv-style discretion. For a defendant asserted against today, the genuinely open avenues are (a) the unchallenged claims 7, 10, 13, 14, 20, where no estoppel attaches to anyone outside Microchip's privies and where invalidity has never been adjudicated; and (b) non-IPR-eligible defenses — § 112 written description / indefiniteness on "software layer," on-sale or public-use bars, inequitable conduct, exhaustion, and license — none of which were tested in IPR2021-01567. Practically, defenses (b) are mostly academic now that the patent expired on 2025-06-28.

Pattern signals. Microchip ran a portfolio-wide IPR campaign against HD Silicon Solutions (Intellectual Ventures lineage — HDSS traces IV → Intellectual Ventures Holding 81 → IV Assets 156 → Innovative Silicon Solutions → HD Silicon Solutions), not a single petition: the ETS records show a Microchip v. HDSS set including IPR2021-01420 (institution denied 2022-05-12 on motivation-to-combine grounds) and IPR2021-01421, alongside IPR2021-01567 and IPR2021-00752 (the '033 patent, where claim 8 survived and claims 1-7 and 9-17 fell). No Unified Patents or other defensive aggregator appears in the '002 chain — the petitioner was a litigation defendant, Microchip, defending itself in HD Silicon Solutions v. Microchip, W.D. Tex. 6:20-cv-01092 (filed 2020-11-30, transferred to N.D. Cal. 3:21-cv-08295 on 2021-10-25, dismissed with prejudice 2025-04-14 by stipulation covering the '002 patent). HDSS did litigate aggressively — it appealed IPR2021-01567 to the Federal Circuit and was the appellant in at least two Rule 36 affirmances in this portfolio. A further HDSS case was filed in the W.D. Tex. in 2025 (1:25-cv-01320), but the patent's expiration date and the 2025 N.D. Cal. dismissal suggest the assertion campaign has wound down.

Recommended next steps

1. Pull the primary documents before you opine on claim-level scope. Get Paper (FWD), IPR2021-01567 (2023-04-04) from PTAB E2E, and the 2025-05-16 inter partes review certificate, which is the operative document listing exactly which claims were canceled. Until you have those two documents, do not tell anyone that a specific claim number is "canceled" — including in a pre-suit demand response or a DJ complaint.
2. If you are a defendant. On this record you should not be paying to settle an assertion on claims 1-6, 8, 9, 11, 12, 15-19: those went through a full IPR trial, an affirmance on appeal, and a § 318(b) certificate. Open with the FWD disposition and the Rule 36 judgment (https://www.cafc.uscourts.gov/opinions-orders/23-1943.RULE_36_JUDGMENT.1-15-2025_2451073.pdf). If the demand letter does cite claims 7, 10, 13, 14, or 20, the attack surface is § 112 and secondary-evidence-free obviousness over Giles/Moyer variants — but first, check the demand date against the 2025-06-28 expiration; for most defendants today the answer may be a flat "the patent is expired."
3. If you are monitoring. There are no pending PTAB milestones: the trial ended 2023-04-04, the appeal mandate issued 2025-02-21, and the certificate issued 2025-05-16. Nothing is awaiting an institution decision, an oral hearing, or an FWD. The only live items are the 2025 W.D. Tex. filings (1:25-cv-01320) and any residual district-court activity — check the Unified Patents litigation portal for those dockets.
4. Correct the intake data. The ODP-derived "no PTAB activity" line should be flagged for the data team. The authoritative PTAB page for this matter is https://portal.unifiedpatents.com/ptab/case/IPR2021-01567 (which shows "Petitioner: Microchip Technology, Inc.," Final Written Decision, and cites IPR2021-01567 as the source for the patent's litigation record).

Confidence and gaps, stated plainly: The existence, parties, filing date (2021-09-23), institution date (2022-04-07), FWD date (2023-04-04), panel (Engels, Ippolito, Peslak), challenged claim set (1-6, 8, 9, 11, 12, 15-19), grounds (Giles/Moyer, § 103), the CAFC appeal (2023-1943), the Rule 36 affirmance (2025-01-15), the mandate (2025-02-21), and the IPA certificate (2025-05-16) are all supported by the sources cited above. What I could not verify from a primary source in this session is the FWD's verbatim claim-by-claim verdict — specifically, whether the Board canceled every challenged claim or spared a subset — and the institution decision's reasoning. I have flagged both rather than guessing.

I'll research the assignment chain, correspondent attorneys, and NPE assertion history before drafting.

Good — I have the Transmeta→IV conveyance text. Now I need the correspondent of record on each recording and the inventor assignments.

US 7,810,002 B2 — "Providing trusted access to a JTAG scan interface in a microprocessor"

Scope note on method. I could not open an interactive session against the USPTO Assignment Center, so the reel/frame entries below are taken from the Google Patents legal-events record for US 7,810,002 and from assignment documents surfaced in PTAB filings (IPR2021-01265 exhibits). Where a detail is not directly observed on this patent's own reels I say so explicitly. Verify at https://assignmentcenter.uspto.gov/ (patent number 7810002) and https://assignment.uspto.gov/patent/index.html.

Inventors

Unusual patterns / caveats:

• The issued patent's face carries no corporate assignee — Google Patents therefore parses the "Original Assignee" field as "Individual." Ownership rested with Transmeta Corporation via inventor employment/invention-assignment agreements, which are not recorded against this patent. The first corporate link in the record of title is the 2009 Transmeta→IV assignment (reel 051257/0115).
• Worth flagging given the subject matter: this is a security patent (gating JTAG access with a signed authentication message verified in a trusted software layer) filed in mid-2005 — squarely inside the window when Transmeta was converting from chip vendor to licensing entity (manufacturing ceased May 2005). It reads as a portfolio/defensive filing rather than a product feature.
• Departure pattern: not determinable. I found no reliable record of either inventor's tenure or departure date, so I will not assert that "all inventors left within 12 months."

Original assignee

• Named on the issued patent: none. The application belonged to Transmeta Corporation (later Transmeta LLC, a Delaware LLC, 2460 N. 1st Street, Suite 200, San Jose, CA 95131 — address confirmed in the parallel Transmeta→IV assignment document surfaced in PTAB filings).
• Primary line of business: fabless semiconductor — x86-compatible low-power microprocessors (Crusoe, Efficeon) using "code morphing" / VLIW architecture. After ceasing chip manufacturing in 2005 it repositioned as a Rambus-style IP licensing company.
• Did it ship a product embodying the claims? Unclear / probably not. Transmeta shipped processors with on-die debug infrastructure, but there is no public evidence that an authentication-gated JTAG scan interface (claims 1–20) shipped in a commercial Crusoe/Efficeon part. The patent's own specification describes the hardware as "a small amount of logic in the die" and treats the secure-CPU-of-a-general-purpose-architecture as the target — the claims read as an architectural safeguard, not a shipped feature.
• Current status: dissolved / wound down. Transmeta sued Intel in Oct 2006 (settled Oct 2007: $150M up-front plus ~$20M/yr for five years). It was acquired by Novafora in a $255.6M deal that closed 2009-01-28, and 140+ U.S. patents were sold to Intellectual Venture Funding LLC (effective 2009-01-28; announced 2009-02-04). Novafora itself collapsed in late July 2009. The litigation-adjacent history includes a shareholder class action over the allegedly undisclosed IV back-room dealing.

Assignment timeline

Every recorded assignment on this patent, in order. Note the compression: although title changed economically in 2009, five of the six recordings happened in a ~13-month window from 2019-12-11 to 2021-01-14.

• 2009-01-28 (executed) / recorded 2019-12-11 — Reel 051257/0115

  • Conveyance: Assignment of assignors' interest (nunc pro tunc — recorded ~10 years and 10 months after execution)
  • Assignor: Transmeta LLC (Delaware LLC, San Jose, CA)
  • Assignee: Intellectual Venture Funding LLC (Nevada LLC, 502 E. John Street, Carson City, NV 89706)
  • Correspondent: not exposed in the Google Patents record; the sibling Transmeta→IV portfolio recording (reel 059360/0563, different application) was submitted by Jonathan Lee c/o FisherBroyles, LLP, 222 South Main Street, 5th Floor, Salt Lake City, UT 84101, with an IV-family examiner-support address at ffbaralegal@maxval.com. Do not treat the FisherBroyles/MaxVal data point as confirmed for reel 051257/0115.
  • Context: fire-sale of a dead operating company's portfolio — Transmeta's 140+ patents sold to IV on the same day Novafora's acquisition of Transmeta closed.

• 2015-08-27 (effective) / recorded 2015-09-29 — Reel 036711/0160

  • Conveyance: Merger
  • Assignor: Intellectual Venture Funding LLC
  • Assignee: Intellectual Ventures Holding 81 LLC (Nevada)
  • Correspondent: not exposed on the Google Patents record.
  • Context: internal IV reorg — Holdings-81 is one of the standard IV title-holding vehicles.

• 2015-08-27 (effective) / recorded 2015-10-06 — Reel 036797/0356

  • Conveyance: Corrective assignment (to correct the assignor's name in reel 036711/0160; confirms the merger)
  • Assignor: Intellectual Venture Funding LLC → Assignee: Intellectual Ventures Holding 81 LLC
  • Correspondent: not exposed.
  • Context: administrative correction, same internal reorg.

• 2019-12-16 (effective) / recorded 2020-01-17 — Reel 051550/0711

  • Conveyance: Assignment of assignors' interest (transfer into IV's divestiture shelf series)
  • Assignor: Intellectual Ventures Holding 81 LLC
  • Assignee: Intellectual Ventures Assets 156 LLC (Delaware)
  • Correspondent: On a sibling recording in the same "Assets NNN" program (Intellectual Ventures I LLC → Intellectual Ventures Assets 57 LLC), the correspondent of record is Intellectual Ventures Management – IP Legal, 3150 139th Avenue SE, Building 4, Floor 3, Bellevue, WA 98005. This is a recurring correspondent across the IV Assets divestiture program; I observed it on the Assets-57 recording, not verified on reel 051550/0711 itself. If it also appears here, that is a repeat-correspondent signal.
  • Context: securitization/shelf transfer — moving the asset into a single-purpose Delaware LLC ahead of sale ("Assets 156" is a sequence number in IV's bulk-divestiture program).

• 2020-01-10 (executed / effective) / recorded 2020-03-23 — Reel 052199/0838

  • Conveyance: Nunc pro tunc assignment
  • Assignor: Intellectual Ventures Assets 156 LLC (executed on its behalf by Jim Weisfield per the copy appearing in IPR2021-01265 exhibits) → Assignee: Innovative Silicon Solutions, LLC (California; later corrected to a Texas address)
  • Correspondent: the IV-Assets-156-side paperwork filed in IPR2021-01265 names Fahim Aftab, 5900 Balcones Dr Ste 100, Austin, TX 78731, e-mail fahim@hongdungroup.com, phone 949-439-0365, as submitter/correspondent. Caveat: that exhibit bundles several documents (one dated 11/12/2020), so I cannot confirm Aftab is the correspondent on the 052199/0838 cover sheet specifically. Note that 5900 Balcones Drive is a well-known Austin virtual-office/registered-agent address.
  • Context: transfer-to-asserter. IV's shell sells the asset to a newly formed licensing vehicle.

• 2020-01-10 (effective) / recorded 2020-03-28 — Reel 052253/0751

  • Conveyance: Corrective assignment (to correct the receiving party's address, previously recorded at 052199/0838)
  • Assignor: Intellectual Ventures Assets 156 LLC → Assignee: Innovative Silicon Solutions, LLC (Texas)
  • Correspondent: not separately exposed.
  • Context: administrative correction.

• 2020-11-10 (effective) / recorded 2021-01-14 — Reel 054993/0795

  • Conveyance: Change of name
  • Assignor: Innovative Silicon Solutions, LLC → Assignee: HD Silicon Solutions LLC (Texas)
  • Correspondent: not exposed on the Google Patents record.
  • Context: rebrand to the plaintiff name — the assertion entity is renamed less than three weeks before its first complaint is filed under the new name.

Recording-completeness observation: the record is closed at the bottom — every 2019–2021 step is an IV-internal shelf transfer, a nunc-pro-tunc sale, an address correction, or a name change. No earlier inventor→Transmeta assignment is recorded against this patent, which is why the patent's face is assignee-less.

Timeline diagram

timeline
    title Ownership of US 7810002
    2005 : Priority application filed
    2009 : Transmeta portfolio sold to IV
    2010 : US 7810002 issued
    2015 : IV Holding 81 merger recorded
    2019 : Transmeta to IV assignment recorded
    2020 : Title to IV Assets 156 LLC
         : Sold to Innovative Silicon Solutions
         : Renamed HD Silicon Solutions
         : Suit filed v Microchip in Waco
    2021 : Microchip IPR filed
    2023 : IPR final written decision
    2025 : IPR certificate issued

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
The asset moves from a licensing-only holding company into a single-purpose Delaware LLC created for divestiture (Intellectual Ventures Assets 156 LLC, reel 051550/0711, effective 2019-12-16) and then, ten days later, to a licensing-only vehicle (Innovative Silicon Solutions, LLC, reel 052199/0838, effective 2020-01-10), which is then renamed (reel 054993/0795). The IV "Assets NNN LLC" series entities are Delaware LLCs of the divestiture program; a sibling entity in the same program (Assets 57 LLC) is c/o 251 Little Falls Drive, Wilmington, DE 19808, a corporate registered-agent address. The terminal entity, HD Silicon Solutions LLC, has no products — it is a plaintiff.

2. Known asserter in the chain — PRESENT.
Intellectual Ventures (Intellectual Venture Funding LLC, reel 051257/0115; Intellectual Ventures Holding 81 LLC, reel 036711/0160; Intellectual Ventures Assets 156 LLC, reel 051550/0711) is on the named NPE list. The terminal entity, HD Silicon Solutions LLC, is a high-frequency plaintiff: it filed HD Silicon Solutions LLC v. Microchip Technology Inc., No. 6:20-cv-01092 (W.D. Tex., filed 2020-11-30) and generated a cluster of PTAB proceedings — IPR2021-00752 and IPR2021-01089 ('299 patent), IPR2021-00872 and IPR2021-01042 ('619 patent), IPR2021-01265 ('404 patent), and IPR2021-01567 (this '002 patent). Medtronic also filed IPR2021-00752 against HDSS, indicating a multi-defendant campaign. It is tracked in Unified Patents' litigation/PTAB portal.

3. Repeat correspondent across the chain — UNCLEAR (leaning present at the program level).
The IV "Assets NNN" divestitures recur with an IV in-house correspondent of record — "Intellectual Ventures Management – IP Legal, 3150 139th Avenue SE, Building 4, Floor 3, Bellevue, WA 98005" — observed on the Assets-57 recording. The IV-Assets-156 → Innovative Silicon paperwork additionally surfaces Fahim Aftab (5900 Balcones Dr Ste 100, Austin, TX 78731; fahim@hongdungroup.com), an Austin virtual-office address. I am not asserting that Aftab or IV IP Legal appears on reels 051550/0711, 052199/0838, or 054993/0795 specifically — I could not read those cover sheets. Treat as a lead to verify, not a finding.

4. Cascading transfers — PRESENT.
Five recorded conveyances in ~13 months (2019-12-11 → 2021-01-14) plus one 2015 merger and its corrective: Transmeta → IV Funding → IV Holding 81 → IV Assets 156 → Innovative Silicon Solutions → HD Silicon Solutions. The intermediate assignees are all IV-family single-purpose entities sharing IV's Bellevue/Carson City/Wilmington infrastructure.

5. Pre-litigation transfer — PRESENT.
The terminal name change was executed 2020-11-10 ("Innovative Silicon Solutions, LLC" → "HD Silicon Solutions LLC", reel 054993/0795) and the first complaint was filed under the new name on 2020-11-30 — 20 days later. The underlying acquisition from IV (reel 052199/0838, effective 2020-01-10) sits ~10.7 months before suit. The chain was assembled with a clean standing record and a plaintiff-shaped name immediately before assertion.

6. Bankruptcy fire-sale — NOT PRESENT.
There was no Chapter 7/11. Transmeta was sold in a going-concern M&A transaction (Novafora, closed 2009-01-28) and its patents were sold to IV the same day — distressed, but not a bankruptcy estate sale. Novafora's subsequent collapse (July 2009) post-dates the patent transfer. The shareholder class action over the undisclosed IV negotiation is a governance dispute, not a bankruptcy.

7. Privateering — UNCLEAR.
There is no evidence that an operating company is directing HD Silicon Solutions' assertions on its behalf (no SEC disclosure, no Patent Progress / EFF coverage identified). Historically the inverse is true: Transmeta itself sued Intel in Oct 2006 as an operating-turned-licensing company. What the present chain does show is IV privateering by divestiture — IV stays a licensor while an arm's-length vehicle litigates the same assets — but I cannot name a sponsoring operating company.

8. Defensive aggregator (anti-NPE) — NOT PRESENT.
The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. Unified Patents appears in the record only as a tracker of the HDSS campaign, not as an owner.

Verdict

NPE — high confidence.

Four independent strong signals are documented on the record itself: (a) a known NPE chain of title running through Intellectual Ventures entities at reels 051257/0115, 036711/0160, and 051550/0711; (b) a transfer of the asset out of IV's single-purpose Delaware shelf Intellectual Ventures Assets 156 LLC to a licensing-only vehicle Innovative Silicon Solutions, LLC at reel 052199/0838 (effective 2020-01-10); (c) a rebranding to the plaintiff name HD Silicon Solutions LLC at reel 054993/0795 (effective 2020-11-10) just 20 days before the 2020-11-30 complaint against Microchip in W.D. Tex.; and (d) a compressed five-recording cascade between 2019-12-11 and 2021-01-14 covering the entire period in which title moved. The original assignee, Transmeta, ceased making products in 2005, which rules out an "operating-company assertion" characterization — the current owner makes nothing and monetizes by suing.

Verify at: https://assignmentcenter.uspto.gov/ (search 7810002) — and cross-check the open items: the correspondent of record on reels 051550/0711, 052199/0838, and 054993/0795, and whether IV's Bellevue "IP Legal" correspondent recurs there as it does elsewhere in the IV Assets program. Those two data points are the only material gaps in this reconstruction.

I'll ground this analysis by searching for the specific patent and each of its cited references.

Let me gather details on the remaining cited references.

Prior-Art Analysis — US 7,810,002 B2

1. The Patent Under Analysis (confirmed literal identification)

Source: https://patents.google.com/patent/US7810002/en

Claim framework (20 claims)

• Independent claim 1 (method): (a) disabling a scan interface in a system comprising a secure processor and a software layer authorized to access trusted resources in the secure processor; (b) receiving authentication information at the software layer; (c) verifying validity using the software layer; (d) allowing access if valid.
• Independent claim 11 (system): secure processor + software module operable to validate authentication information (and authorized to access trusted resources) + scan interface, access granted if authentication information is valid.
• Independent claim 17 (computer-readable medium): mirrors claim 1.
• Dependents: 2–10 (boot-up disable; internal register 1st/2nd state; communication buffer; proper format; public/private key pair; encryption; password; override enable pin); 12–16 (internal register; enable switch; public key; denied by default on boot; communication buffer + authentication link); 18–20 (register; format; override pin).

Critical observation for § 102 purposes: the distinguishing limitation across all three independent claims is that the software layer/module itself receives, verifies and grants access, and is authorized to access trusted resources inside the secure processor. As discussed below (and as reflected in the IPR record), most cited art locates these functions in hardware (security modules, test controllers, fuses), not in a privileged software layer.

2. The Thirteen Cited References (the examiner/"cited by" art on the face of the patent)

Note on § 102 basis: The '002 priority date is 2005‑06‑28 (pre‑AIA governs). Publications dated before that date are § 102(a)/(b) art; later‑published U.S. patents/applications whose filing date precedes it are § 102(e) art. "Potentially anticipates" below means the reference discloses enough of the recited subject matter to warrant a § 102 rejection on the claim(s) identified, in my assessment.

2.1 US 2006/0282734 A1 — ARM Limited — the closest reference

• Full citation: U.S. Pub. No. 2006/0282734 A1, "Test access control for secure integrated circuits," Arm Limited (inventors Milse et al.).
• Dates: filed 2005‑05‑23; published 2006‑12‑14. → § 102(e) art (filed before the '002 priority date).
• Description: An IC with a test circuit (serial scan chains/JTAG interface 12) and a test rights controller that receives and authenticates a "test access request"/"test rights enabling key." If authentication passes, test operations at a corresponding level are permitted; if it fails, test operations are prevented. The key may be read from a SIM/smartcard and authenticated by a software‑controlled processor executing "test rights controlling software" in the most secure mode, which writes enabling flags into a test access control register inaccessible outside the secure mode. The key may also be delivered via the JTAG scan chain itself.
• Potential § 102 mapping:
  • Claim 1 [a] — disabling/preventing test access by default (test mechanisms selectively enabled/disabled via debug access module 16); strongest on the "software layer" and "verify" elements because ¶¶ [0016]–[0017] expressly describe software‑controlled processor executing test rights controlling software in a secure mode.
  • Claim 1 [b]–[d] / claim 11 / claim 17 — receiving the enabling key, authenticating it, and thereupon permitting test operations.
  • Claims 3, 4, 12 — writing test access control register flags (enabled/disabled states).
  • Claim 5 / 16 — key received through an interface circuit (analogous "communication buffer" argument, though not identical).
  • Claim 15 — denial by default; Claim 2 — enabling logic tied to processor mode/boot.
• Caveat: its "test rights controlling software" runs on a separate secure (smart‑card) processor, and the reference does not use the exact phrase "software layer authorized to access trusted resources in said secure processor." It is the best § 102(e) candidate but still likely requires a § 103 combination to reach the exact claim language.

2.2 US 2003/0204801 A1 — Motorola, Inc.

• Full citation: U.S. Pub. No. 2003/0204801 A1, "Method and apparatus for secure scan testing," Motorola, Inc. (Tkacik et al.).
• Dates: filed 2002‑04‑30 (priority 2002‑04‑29); published 2003‑10‑30 → § 102(a)/(b).
• Description: Processor with a scan controller 120 that denies access to the scan chain until sensitive data is cleared from scan‑observable portions, then clears again on exiting test mode. Employs TEST MODE / SECURE RESET signals and gated SCAN IN/OUT/ENABLE; state machine and logic gate the scan chain.
• Potential § 102 mapping:
  • Claim 1 [a] (disabling/denying access to a scan interface) and claim 15 (denied by default).
  • Claim 3 / 12 (register/state element set to a first state that disables the interface).
  • Not claim 1[b]–[d]: no authentication information, no software layer verification → no § 102 anticipation of any independent claim.

2.3 US 2003/0206627 A1 — General Instrument Corp. ("Secure scan")

• Full citation: U.S. Pub. No. 2003/0206627 A1, "Secure scan," General Instrument Corp. (Penugonda et al.).
• Dates: priority 2002‑05‑03; published 2003‑11‑06 → § 102(a)/(b).
• Description: Encrypts/decrypts/hashes the scan signal into and out of the scan chain, using public/private keys and per‑DUT unique keys; test vectors may be customized and encrypted for a particular DUT with a unique stored key.
• Potential § 102 mapping:
  • Claim 8 ("authentication information is encrypted") and claim 7 (public/private key usage) — if the scan data/cipher text is treated as "authentication information"; the reference uses keys to protect scan data rather than to gate access.
  • Claim 9 (password/key verification) — weak.
  • No § 102 anticipation of claims 1/11/17 (no software‑layer access‑control decision).
• Literal‑ID note: the IPR demonstratives for this family list "2003/0206672 A1 (Penugonda et al.)" while the patent front page and Google Patents list US 2003/0206627 A1 ("Secure scan"). Per the instruction not to auto‑correct identifiers, I treat US20030206627A1 as the cited reference and flag the discrepancy rather than silently reconciling it.

2.4 US 2005/0066189 A1 — Moss

• Full citation: U.S. Pub. No. 2005/0066189 A1, "Methods and structure for scan testing of secure systems," R. Moss.
• Dates: filed 2003‑09‑18; published 2005‑03‑24 → § 102(a)/(b).
• Description: A scan test signal interceptor and a security element that preclude retrieval of secure information by forcing an internal reset of secure flip‑flops/registers on entry to and exit from scan test; external users cannot bypass the internally generated reset.
• Potential § 102 mapping:
  • Claim 1 [a] (precluding/denying access to secure scan information) — the "disabling" concept.
  • No authentication at all → no anticipation of claims 1[b]–[d], 7, 9, 11, 17.

2.5 US 6,968,420 B1 — LSI Logic ("Giles")

• Full citation: U.S. Pat. No. 6,968,420 B1, "Use of EEPROM for storage of security objects in secure systems," LSI Logic Corp. (Giles et al.).
• Dates: filed 2002‑02‑13; issued 2005‑11‑22 → § 102(e).
• Description: Secure system storing security objects in EEPROM; relates to disabling scan/boundary‑scan mechanisms on secure devices (the Giles family).
• Potential § 102 mapping: Claims 1 [a], 3, 15 (disabling scan capability, secure storage of access data). The IPR record shows Patent Owner argued this family does not disclose a "software layer" receiving/verifying authentication — consistent with my view that it does not anticipate claims 1/11/17.

2.6 US 7,117,352 B1 — LSI Logic ("Giles") — debug port disable

• Full citation: U.S. Pat. No. 7,117,352 B1, "Debug port disable mechanism," LSI Logic Corp. (Giles et al.).
• Dates: filed 2002‑02‑13; issued 2006‑10‑03 → § 102(e).
• Description: Mechanism for disabling a debug port (e.g., JTAG) on a secure device, typically via a fuse/pin/one‑time‑programmable element.
• Potential § 102 mapping:
  • Claim 1 [a] (disabling scan/debug interface) and claim 10 / 20 (an override enable pin controlling the interface) — a strong conceptual match for the external‑pin override.
  • Claim 15 (disabled by default).
  • No software‑layer authentication → no anticipation of claims 1/11/17 as a whole.

2.7 US 7,080,789 B2 — STMicroelectronics, Inc.

• Full citation: U.S. Pat. No. 7,080,789 B2, "Smart card including a JTAG test controller and related methods," STMicroelectronics, Inc. (Leaming).
• Dates: filed 2003‑05‑09; issued 2006‑07‑25 → § 102(e).
• Description: Smart card IC incorporating a JTAG test controller.
• Potential § 102 mapping: Background/structural art for JTAG in a secure token; at most relevant to the "secure processor + scan interface" sub‑elements of claims 1 and 11. No authentication‑at‑software‑layer disclosure → no independent‑claim anticipation.

2.8 US 7,293,709 B2 — NXP B.V. (Baker et al.)

• Full citation: U.S. Pat. No. 7,293,709 B2, "Detection of tampering of a smart card interface," NXP B.V.
• Dates: priority 2003‑01‑14; issued 2007‑11‑13 → § 102(e).
• Description: Tamper detection on a smart‑card interface.
• Potential § 102 mapping: Peripheral; relevant only if "authentication information" is read onto smart‑card security signaling. No disclosure of a privileged software layer accessing trusted processor resources → no anticipation of claims 1/11/17.

2.9 US 7,325,121 B2 — Broadcom (Buer)

• Full citation: U.S. Pat. No. 7,325,121 B2, "System and method of utilizing off‑chip memory," Broadcom Corp. (Buer).
• Dates: priority 2003‑09‑12; issued 2008‑01‑29 → § 102(e).
• Description: Off‑chip memory utilization/address translation.
• Potential § 102 mapping: Weak. At most tangentially relevant to "internal register"/storage features (claims 3, 12). Not anticipatory of any independent claim.

2.10 US 7,444,571 B1 — Marvell International (Azimi et al.)

• Full citation: U.S. Pat. No. 7,444,571 B1, "Apparatus and method for testing and debugging an integrated circuit," Marvell International Ltd.
• Dates: priority 2003‑02‑27; issued 2008‑10‑28 → § 102(e).
• Description: IC test/debug apparatus (scan/boundary‑scan and debug access).
• Potential § 102 mapping: Background art for claims 1 [a] and 11 [scan interface accesses features of the processor]. No software‑layer authentication → no anticipation.

2.11 US 7,539,312 B2 — Panasonic (Fujiwara et al.)

• Full citation: U.S. Pat. No. 7,539,312 B2, "Program update method and server," Panasonic Corp.
• Dates: priority 2002‑11‑15; issued 2009‑05‑26 → § 102(e).
• Description: Secure program update methodology/server.
• Potential § 102 mapping: Peripheral authentication art; possibly relevant to claims 7/8/9 (signature/encryption concepts) in a § 103 combination, but the context (program update) differs from scan‑interface gating. No anticipation of claims 1/11/17.

2.12 US 7,587,750 B2 — Intel Corporation (Zimmer et al.)

• Full citation: U.S. Pat. No. 7,587,750 B2, "Method and system to support network port authentication from out‑of‑band firmware," Intel Corp.
• Dates: priority 2003‑06‑26; issued 2009‑09‑08 → § 102(e).
• Description: Out‑of‑band firmware supporting network‑port authentication.
• Potential § 102 mapping: Relevant to "authentication performed by a firmware/software entity" generally (claim 1 [b]–[c]) but in a network‑port context, not a scan interface. No anticipation of the independent claims.

2.13 JP 2002‑228716 A — Matsushita Electric Industrial Co., Ltd.

• Full citation: Japanese Pub. No. JP 2002‑228716 A, "Semiconductor device," Matsushita Electric Industrial Co., Ltd.
• Dates: priority 2001‑01‑29; published 2002‑08‑14 → § 102(a)/(b).
• Description: I could not verify the disclosure text within this session (search returned no substantive document). Based on title/classification alone, it is a semiconductor‑device reference, presumably relating to scan/test security.
• Potential § 102 mapping: Unknown / low confidence. I am explicitly not assigning claim numbers here rather than speculate; a full‑text retrieval (JPO/Espacenet) would be required.

3. Overall § 102 Assessment

1. No single cited reference appears to anticipate independent claims 1, 11 or 17 in their entirety. The common gap is the limitation that the software layer/module (a) is authorized to access trusted resources inside the secure processor and (b) itself receives and verifies the authentication information. The cited art that comes closest — US 2006/0282734 A1 (ARM) — places authentication in a secure‑mode software‑controlled processor and writes an access‑control register, but its "test rights controlling software" runs on a separate secure processor and the reference does not describe accessing trusted resources within the same secure processor. This aligns with the IPR2021‑01567 record, where the patent owner argued Giles and Moyer do not disclose a "software layer" receiving/verifying/granting access.

2. Best individual § 102 candidates, claim‑by‑claim:

   • Claim 1 [a] "disabling a scan interface": US 7,117,352 B1 (Giles, debug‑port disable); US 2003/0204801 A1 (Motorola scan controller denies access); US 2005/0066189 A1 (Moss interceptor/reset); US 2006/0282734 A1 (ARM — prevents test operations absent authentication).
   • Claims 3/4/12 (internal register first/second state): US 2006/0282734 A1 (test access control register); US 2003/0204801 A1 (state‑machine/logic state).
   • Claim 10/20 (override enable pin): US 7,117,352 B1 (debug port disable pin/fuse mechanism).
   • Claims 7/8/9 (asymmetric key pair; encryption; password): US 2003/0206627 A1 ("Secure scan," per‑DUT keys, encryption of scan data).
   • Claims 15, 2 (denied by default / on boot): US 2003/0204801 A1; US 7,117,352 B1; US 2006/0282734 A1.
   • Claims 1/11/17 as a whole: none anticipated; the ARM reference is best characterized as supporting a § 103 combination.

3. Later references appearing in the "Cited By" list — NOT prior art to the '002 priority date:

   • US 2010/0217964 A1 / US 8,214,630 B2 (General Instrument, "controlling enablement of JTAG interface"), priority 2009‑02‑24.
   • US 9,633,185 B2 (Samsung, "Device having secure JTAG and debugging method for the same"), priority 2014‑02‑24.
     These post‑date 2005‑06‑28 and are therefore not § 102 art against the '002 patent (they are, instead, evidence of the field's later development).

4. Incorporated‑by‑reference family member: US 7,600,166 B1 (parent, App. 11/169,403, filed 2005‑06‑28) is not prior art (same family/priority) but defines the same disclosure; its claim 1 uses "trusted software layer" and "JTAG scan interface" language more explicitly.

4. Confidence and Limitations

• High confidence: patent bibliographic data, claim text, and the disclosure of US 2003/0204801 A1, US 2003/0206627 A1, US 2005/0066189 A1 and US 2006/0282734 A1 (verified against full document snippets this session).
• Lower confidence: descriptions and claim mappings for US 6,968,420; US 7,117,352; US 7,080,789; US 7,293,709; US 7,325,121; US 7,444,571; US 7,539,312; US 7,587,750 (based on title/abstract‑level information; full‑text retrieval was not completed before the tool limit). JP 2002‑228716 A was not verifiable at all.
• IPR outcome: IPR2021‑01567 (Microchip v. HD Silicon Solutions) went to a Final Written Decision, and an inter partes review certificate issued 2025‑05‑16; the available excerpts show the patent owner's response arguments, not the Board's ultimate disposition. I do not know with confidence which claims were cancelled, confirmed, or amended, and I am not asserting an outcome.
• The '002 patent is expired (anticipated expiration 2025‑06‑28), which limits the practical significance of any anticipation analysis today.

I'll ground this analysis with targeted searches on the IPR record and the key prior-art references before drafting.

Good — I now have the IPR grounds and institution record. Let me pin down the Final Written Decision outcome and the faces of the examiner-cited references.

Obviousness Analysis — U.S. Patent 7,810,002 B2

35 U.S.C. § 103 | Priority date: 2005‑06‑28 | Analyst date: 2026‑04‑26

0. What I am building on, and one correction to the earlier section

This section assumes the bibliographic data, claim summaries, and litigation history already produced. It does not repeat them.

Correction / resolution of a flagged uncertainty. The prior section said: "I was not able to retrieve the FWD text to state definitively which claims, if any, were held unpatentable." I retrieved substantial FWD text in this pass. It shows the Board, in IPR2021‑01567, rejecting HDSS's non‑obviousness arguments claim by claim and expressly holding claims 8, 9, 11, 12, 15, and 17 unpatentable as obvious over Giles alone — e.g., for claim 8: "Petitioner has shown that a person of ordinary skill would have been motivated to encrypt the authentication information in Giles's authentication process, and we determine Petitioner has shown by a preponderance of the evidence that claim 8 is unpatentable as obvious in view of Giles"; and for claim 9 the Board held that HDSS "state[d] only that Giles does not 'disclose' the use of a password … without substantively addressing whether the use of a password … would have been obvious." (FWD excerpts, IPR2021‑01567, Patent 7,810,002 B2, retrieved via PTACTS: https://ptacts.uspto.gov/ptacts/public-informations/petitions/1548426/download-documents). This is consistent with HDSS being the appellant and losing (Fed. Cir. No. 2023‑1943, Rule 36 affirmance, 2025‑01‑15: https://www.cafc.uscourts.gov/opinions-orders/23-1943.RULE_36_JUDGMENT.1-15-2025_2451073.pdf), and with the K1 IPR certificate of 2025‑05‑16. I still could not retrieve the complete claim‑by‑claim outcome table, so I do not assert that every challenged claim was cancelled — but the direction is no longer uncertain.

1. Governing standard, POSITA, effective filing date

Graham v. John Deere, 383 U.S. 1 (1966) factors; KSR Int'l v. Teleflex, 550 U.S. 398 (2007) (motivation may be found in design incentives, known techniques, predictable variation, and market/engineering demands).

POSITA (as Petitioner proposed and the Board applied at institution): a bachelor's degree in electrical engineering, computer engineering, or computer science, plus several years of experience in digital IC design/security. This is a high skill level for the 2005 timeframe, which matters: it makes the "implement the check in software rather than hardware" variation plainly predictable.

Effective date. Claims are supported by the '166 parent (filed 2005‑06‑28), so the operative date is 2005‑06‑28. Note the litigation-contingent alternative: because the '002's claim language was amended during its own 2009–2010 prosecution (the limitation dropped from "trusted software layer" to "software layer"), a defendant could argue the claims are not fully supported by the parent for the broader scope and press a later effective date. A later date only enlarges the prior‑art field and strengthens the obviousness case — so this is a floor, not a ceiling, for the analysis below.

2. The construction that decides this case: "software layer"

Every independent claim (1, 11, 17) turns on the authentication being performed by a software layer that is authorized to access trusted resources in the secure processor. HDSS's entire defense, at the PTAB and in district court, was to read this term narrowly.

The practical consequence: under HDSS's construction, boot ROM code in a prior‑art reference is not a "layer" (no neighboring level), and the claims survive. Under the plain meaning applied by the Board, single‑level firmware qualifies, and the claims fall. HDSS pressed exactly this in its Preliminary Response, arguing that "code 163 includes all the characteristics of the software layer" was an implicit admission that "code 163 is not a software layer." The Board adopted the plain meaning for institution; the FWD findings on claims 8/9/11/12/15/17 confirm it carried through to the merits. Any obviousness conclusion here is construction‑dependent, and that is the single highest‑leverage issue in the case.

Two further breadth points that help an obviousness challenger:

• Claim 1 requires only "allowing access to said scan interface if said authentication information is valid" — not "only if." The reference need not show that authentication is the exclusive gate. This matters because both Giles and Moyer retain non‑authentication paths (override pin, STATE A/D, time‑outs).
• Claim 1 requires a "software layer," not a "trusted software layer." Compare the '166's claims (which recite "trusted software layer") per the earlier section. The '002's deliberate broadening is what let the prior art in.

3. The prior art on the face of this page

Two distinct bodies of art matter, and they prove different things.

(a) Examiner‑cited art (the page's "Citations (13)" / "Prior Art" listing)

Critical caveat on Arm '734: it is prior art only under pre‑AIA § 102(e), by its 2005‑05‑23 filing date — 36 days before the '002's 2005‑06‑28 priority date. That is a valid but thin margin, and it presumes the '002 is entitled to the parent's date for the modified claim language. If a challenger instead relies on the later amendment date, Arm '734 is comfortably prior art (and so is everything else). Only the subject matter actually supported by Arm '734's specification as of 2005‑05‑23 can be used.

(b) The art that actually invalidated the claims (not on the '002's face — raised first in the IPR)

4. Grounds of rejection, claim 1 / 11 / 17

Ground A — Arm '734 alone (single‑reference § 103), strongest on the "software layer" element

Motivation / reasonable expectation of success. Arm '734 is not merely analogous art; it is the same art. It supplies its own motivation in [0016]: "Another approach … is to use a software controlled processor within the integrated circuit to execute test rights controlling software to provide these functions. Secure systems … often already have mechanisms and structures for providing secure execution environments and these can be reused by the test rights controlling software." That sentence is a direct, articulated rationale for the '002's stated advantage ("a minimal set of hardware and software components"). Under KSR, reuse of an existing secure‑execution mechanism to gate a test port is a predictable variation with a documented design incentive. Failure risk is negligible: no new scan hardware is required; the register and secure mode already exist.

Where a challenger is exposed on Ground A: Arm '734 discloses levels of test access and comparison to stored keys; it does not, on its face, disclose a signature verification using an asymmetric key pair (claims 7/14) or a password (claim 9) as such. Those require Grounds B/C or general knowledge.

Ground B — Giles alone, or Giles + Moyer (the combination the Board actually sustained)

This is the proven ground. The Board's institution decision found each element of claim 1 shown over Giles, and the FWD then rejected HDSS's specific attacks on claims 2–6, 8, 9, 11, 12, 15–19. Structure of the mapping:

• "scan interface" / "scan chain architecture" ← Giles' EJTAG interface 112, scan chain 177, scan wrappers 131/137, scan chain 173, debug module 176 (Giles FIG. 1; per Petition/Expert ¶ on preamble).
• "disable … if invalid, enable … if valid" ← Giles' security module enabling/disabling scan capability by security mode; EJTAG authentication.
• "authentication information received at the software layer / verified by the software layer" ← Giles' challenge/response authentication via UART port 110 implemented by firmware, code, or software, with boot ROM code 163 doing the verification.
• "internal register … first state disables, second state enables" (claims 3/4/12/18) ← Giles' EJTAG enable module 134 and the EJTAG security flag initialization process (FIG. 4).
• "denied by default upon bootstrapping" (claims 2/15/18) ← Giles' FIG. 4 flag initialization; reinforced by Moyer's STATE A → STATE B (disabled at sale) transition.

Motivation to combine Giles + Moyer (Grounds 3 and 4 in the petition): both are in Integrated Circuit security / test‑and‑debug access control and address the identical problem (unauthorized access to protected circuitry through a test/debug port). Moyer supplies what Giles is thinnest on — an explicit enable register/switch architecture (non‑volatile elements 38 feeding debug enable circuitry 40, which asserts enable debug signal 58), a default‑disabled‑at‑sale posture, and a post‑sale authentication‑required re‑enable state (STATE C). Moyer also expressly states that the authentication process "may include software that is separate from debug circuitry 42" — which is precisely the transfer of authentication intelligence out of dedicated hardware that the '002 claims. Reasonable expectation of success: both use conventional JTAG/EJTAG scan chains and conventional key comparison; no incompatibility.

Ground C — Moyer + Arm '734 (best answer to HDSS's best argument)

HDSS's strongest non‑obviousness argument in the POPR was structural: in both Giles and Moyer, a hardware module — Giles' "security supervisor" 136, Moyer's "authentication circuitry" 44 — performs the authentication, separate and apart from the code the petitioner labeled a "software layer." That argument is answerable by using Arm '734 as the secondary reference: Arm '734 affirmatively teaches implementing the test‑rights controller in software executing in a secure mode, with its own stated motivation of reusing existing secure‑execution infrastructure. A POSITA starting from Moyer's debug port (which already has authentication circuitry, e.g., key comparison 30 vs. 52, and a documented post‑sale re‑enable need) and seeking to reduce die area or to handle the case where the debug/authentication hardware is inoperative would be led by Arm '734 to move that logic into the secure‑mode software. The KSR "known technique / predictable variation" rationale applies directly, and Arm '734 supplies the articulated reason HDSS said was missing (HDSS argued the petition "provides no explanation of the motivation for a POSITA to modify and combine the software in the debug circuitry of Moyer").

This ground is not on the patent's face and would require Arm '734 to be perfectible as § 102(e) art on the 36‑day margin described above.

5. Ground D — the dependent claims, including the four never challenged

6. Bottom line

• Claims 1–6, 8, 9, 11, 12, 15–19 (if all cancelled): already adjudicated obvious over Giles, alone or in combination with Moyer, and the judgment stands after the Rule 36 affirmance. For these claims, the § 103 question is res judicata-adjacent in practice — a new claim-by-claim challenge would be redundant while the IPR certificate (K1, 2025‑05‑16) is in force.
• Claims 7, 10, 13, 14, 20: never challenged in IPR2021‑01567. Of these, claims 10, 13, and 20 are the most vulnerable on the on‑page art (Giles pin protection + Moyer's enable circuitry + Arm '734's register); claims 7 and 14 (asymmetric‑key signature) are the genuine residual strength of the patent and would need art from outside the page (Moyer's US 2003/0177373, US 7,844,997, US 7,398,441).
• The case is subsumed by one construction fight. If "software layer" is read as a member of a hierarchy of adjacent levels, single‑level firmware (Giles' boot ROM 163) drops out and claims 1–6/11/12/15–19 become materially harder to invalidate on these references. If read per plain meaning — as the Board applied it — the claims fall. The Federal Circuit's Rule 36 disposition supplies no reasoning on this point, so the construction remains formally open in any fresh forum.
• Practical stake is low regardless: the patent's anticipated expiration was 2025‑06‑28, and the N.D. Cal. action 3:21‑cv‑08295 was dismissed with prejudice 2025‑04‑14. The live W.D. Tex. case 1:25‑cv‑01320 (2025) would be limited to pre‑expiration damages on surviving claims.

7. Caveats

• I did not retrieve the complete FWD outcome table, the exact POSITA findings on the merits, or the Board's final construction statement; the claim‑by‑claim conclusions above for claims 2–6, 16, 18, 19 are inferences from the Board's treatment of substantively equivalent claims (2↔15, 3/4↔12, 1↔11/17) and from the petition's grounds structure.
• Characterizations of US 2005/0066189, US 2003/0204801, US 2003/0206627, US 7,117,352, US 6,968,420, US 7,080,789, and JP 2002‑228716 A rest on their titles and bibliographic data as listed on the page plus general field knowledge. I did not open their specifications in this pass; treat the element‑by‑element mappings for those references as provisional and verify before relying on them.
• My identification of Giles as belonging to the same General Instrument / secure‑set‑top‑box family as the examiner‑cited US 2003/0206627 ("Secure scan") is an inference from the overlapping subject matter (STB security, smart cards, OTP memory, EJTAG) — not confirmed from assignee records.
• The Arm '734 prior‑art status depends on the 2005‑05‑23/2005‑06‑28 date margin and on § 102(e) eligibility; this is the single most attackable evidentiary link in Ground A.
• Identifiers were matched literally; I did not auto‑correct "7810002," and I continue to exclude the unrelated '033 tungsten patent (Appeal No. 23‑1397) and the '166 from the '002 analysis except where expressly noted.