US 7502958

US patent 7502958, titled "System and method for providing firmware recoverable lockstep protection," addresses the challenge of managing errors in lockstep processor systems without causing a system crash.

Summary of US Patent 7502958:

• Title: System and method for providing firmware recoverable lockstep protection
• Current Assignee: Foras Technologies Ltd
• Original Assignee: Hewlett Packard Development Co LP
• Inventors: Scott L. Michaelis, Anurupa Rajkumari, William B. McHardy
• Filing Date: 2004-10-25
• Issue Date: 2009-03-10
• Abstract: The patent describes a method for handling "loss of lockstep" (LOL) in a pair of processors. This method involves firmware detecting LOL, then triggering an operating system (OS) to idle the affected processors. The firmware then recovers the lockstep between the processors. Once recovery is successful, the firmware triggers the OS to recognize the processors as available for receiving instructions again.

Plain-Language Overview of Independent Claims:

• Independent Claim 1: This claim outlines a firmware-driven method for recovering from a "loss of lockstep" (LOL) in a pair of processors. Upon detecting LOL, the firmware first checks if the problem is "recoverable" by specifically determining if a "lockstep mismatch" has occurred (where the outputs of the two processors differ). If it's recoverable, the firmware directs the operating system to temporarily stop using these processors, then fixes the lockstep issue, and finally signals the operating system that the processors are ready to resume operations.
• Independent Claim 13: This claim describes a system comprising an Advanced Configuration and Power Interface (ACPI)-compatible operating system, a master processor, a slave processor (operating in lockstep with the master), and firmware. When this firmware detects a loss of lockstep between the master and slave processors, it uses an ACPI standard method to tell the operating system to idle the master processor. The firmware then attempts to restore the lockstep. If successful, it uses another ACPI method to inform the operating system that the master processor is available for use again.
• Independent Claim 19: This claim focuses on a system that includes a pair of lockstep processors and computer-executable firmware code. When a loss of lockstep is detected, the firmware code determines if the issue is recoverable, specifically by checking if a lockstep mismatch has occurred. If the lockstep is deemed recoverable, the firmware code triggers the operating system to idle the processors, then attempts to restore lockstep. If this recovery is successful, the firmware code informs the operating system that the processors are ready to receive instructions once more.
• Independent Claim 23: This claim describes a method for a multi-processor system, particularly for handling loss of lockstep involving the system's "boot processor." It starts by establishing a "hot spare" processor specifically for the boot processor. When a loss of lockstep is detected for any lockstep pair, the method determines if the affected pair is the boot processor. If it is the boot processor, the "good" state of the boot processor is copied to the hot spare, making the hot spare the new boot processor. If the affected pair is not the boot processor, the method proceeds by triggering the operating system to idle those processors, attempting to recover lockstep, and if successful, triggering the operating system to recognize them as available.

CAFC 2026 Dockets:
A search for US patent 7502958 in CAFC 2026 dockets did not specifically identify any cases directly involving this patent in the year 2026. While Google Patents indicates that the patent family has ongoing litigation, including a US case filed in the Court of Appeals for the Federal Circuit (case/25-1968), the available search results for specific 2026 CAFC dockets do not list US7502958 or its case number. Therefore, there is no authoritative information from the provided search results to confirm active CAFC litigation specifically for US7502958 within the 2026 timeframe.

Known litigation involving US patent 7502958 (System and method for providing firmware recoverable lockstep protection) as of April 26, 2026, includes several cases in U.S. District Courts, the Court of Appeals for the Federal Circuit, and before the Patent Trial and Appeal Board (PTAB). Foras Technologies Ltd. is the current assignee of US7502958.

Here is a summary of the known litigation:

U.S. District Court Cases:

• Jurisdiction: Texas Western District Court
  • Case Number: 6:23-cv-00386
  • Plaintiff(s): Foras Technologies, Ltd.
  • Defendant(s): BMW
  • Filing Date: Not explicitly stated in search results, but it is identified as the lead case for a consolidated action filed in 2023.
  • Outcome/Current Status: Active. Case 6:24-cv-00371 was consolidated into this lead case, and a stay is in effect, likely reflecting parallel inter partes review (IPR) proceedings.
• Jurisdiction: Texas Western District Court
  • Case Number: 6:24-cv-00371
  • Plaintiff(s): BMW and Robert Bosch GmbH
  • Defendant(s): Foras Technologies, Ltd.
  • Filing Date: Circa July 12, 2024.
  • Outcome/Current Status: Consolidated and transferred to lead case Foras v. BMW, 6:23-cv-00386-RP, on July 19, 2024. No merits determination, damages award, or injunctive relief was issued.
• Jurisdiction: Virginia Eastern District Court
  • Case Number: 1:24-cv-00363
  • Plaintiff(s): Not explicitly stated in search results. (Likely Foras Technologies Ltd.)
  • Defendant(s): Not explicitly stated in search results.
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Active. Noted as "Critical" on Google Patents.
• Jurisdiction: Virginia Eastern District Court
  • Case Number: 2:23-cv-00647
  • Plaintiff(s): Not explicitly stated in search results. (Likely Foras Technologies Ltd.)
  • Defendant(s): Not explicitly stated in search results.
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Active.
• Jurisdiction: Virginia Eastern District Court
  • Case Number: 1:23-cv-01689
  • Plaintiff(s): Not explicitly stated in search results. (Likely Foras Technologies Ltd.)
  • Defendant(s): Not explicitly stated in search results.
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Active.
• Jurisdiction: Texas Eastern District Court
  • Case Number: 2:23-cv-00314
  • Plaintiff(s): Not explicitly stated in search results. (Likely Foras Technologies Ltd.)
  • Defendant(s): Not explicitly stated in search results.
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Active.
• Jurisdiction: Texas Eastern District Court
  • Case Number: 2:23-cv-00219
  • Plaintiff(s): Not explicitly stated in search results. (Likely Foras Technologies Ltd.)
  • Defendant(s): Not explicitly stated in search results.
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Active.
• Jurisdiction: Texas Eastern District Court
  • Case Number: 2:23-cv-00150
  • Plaintiff(s): Not explicitly stated in search results. (Likely Foras Technologies Ltd.)
  • Defendant(s): Not explicitly stated in search results.
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Active.
• Jurisdiction: Texas Western District Court
  • Case Number: 1:23-cv-00640
  • Plaintiff(s): Not explicitly stated in search results. (Likely Foras Technologies Ltd.)
  • Defendant(s): Not explicitly stated in search results.
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Active.
• Jurisdiction: Texas Western District Court
  • Case Number: 6:23-cv-00386
  • Plaintiff(s): Not explicitly stated in search results. (Likely Foras Technologies Ltd.)
  • Defendant(s): Not explicitly stated in search results.
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Active.
• Jurisdiction: Court of Appeals for the Federal Circuit
  • Case Number: 25-1968
  • Plaintiff(s): Not explicitly stated in search results.
  • Defendant(s): Not explicitly stated in search results.
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Active.

Patent Trial and Appeal Board (PTAB) Cases:
For these cases, Unified Patents is typically the petitioner challenging the patent, and Foras Technologies Ltd. would be the patent owner.

• Case Number: IPR2024-00823
  • Petitioner: Unified Patents (presumed)
  • Patent Owner: Foras Technologies Ltd. (presumed)
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Final Written Decision.
• Case Number: IPR2024-00727
  • Petitioner: Unified Patents (presumed)
  • Patent Owner: Foras Technologies Ltd. (presumed)
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Settlement.
• Case Number: IPR2024-00969
  • Petitioner: Unified Patents (presumed)
  • Patent Owner: Foras Technologies Ltd. (presumed)
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Settlement.
• Case Number: IPR2024-00813
  • Petitioner: Unified Patents (presumed)
  • Patent Owner: Foras Technologies Ltd. (presumed)
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Procedural Termination.
• Case Number: IPR2023-01373
  • Petitioner: Unified Patents (presumed)
  • Patent Owner: Foras Technologies Ltd. (presumed)
  • Filing Date: Not explicitly stated in search results.
  • Outcome/Current Status: Final Written Decision.

Proceedings overview

There are 5 AIA trial proceedings on file for US Patent 7,502,958. Two of these proceedings (IPR2023-01373 and IPR2024-00823) have reached a Final Written Decision, while two (IPR2024-00727 and IPR2024-00969) were terminated due to settlement, and one (IPR2024-00813) was procedurally terminated. The Final Written Decisions indicate that all challenged claims were found unpatentable in both completed IPRs. This suggests a challenging defensive posture for the patent owner, as multiple claims have been invalidated.

IPR2023-01373 — Unified Patents, LLC v. Foras Technologies Ltd.

• Type: Inter Partes Review
• Filed: 2023-08-01 (Petition filing date)
• Status: Final Written Decision
• Judge panel: Deborah E. Katz, Christopher L. Kelly, Brian J. McNamara
• Petition grounds: Claims 1-6, 13-15, and 19-22 were challenged under 35 U.S.C. § 103 as obvious over US 6,862,703 (JAMBULINGAM) in view of US 6,108,793 (KUPPULUSAMY). Claims 1, 4, and 5 were also challenged under 35 U.S.C. § 103 over JAMBULINGAM in view of KUPPULUSAMY and US 6,560,733 (CHEN).
• Institution decision: Instituted on 2024-02-09 for claims 1-6, 13-15, and 19-22. The panel determined that Petitioner had a reasonable likelihood of prevailing with respect to the challenged claims based on the cited prior art.
• Final Written Decision: Issued on 2025-02-07. Claims 1-6, 13-15, and 19-22 were found unpatentable. The panel concluded that "Petitioner has shown by a preponderance of the evidence that claims 1–6, 13–15, and 19–22 of the ’958 patent are unpatentable."
• Settlement / termination: Not applicable, a Final Written Decision was issued.
• Appeal: No Federal Circuit appeal identified.
• Defensive value: Claims 1-6, 13-15, and 19-22 of US7502958 have been found unpatentable, significantly narrowing the scope of the patent. Any infringement theory based on these claims is likely moot.

IPR2024-00823 — Unified Patents, LLC v. Foras Technologies Ltd.

• Type: Inter Partes Review
• Filed: 2024-04-03 (Petition filing date)
• Status: Final Written Decision
• Judge panel: Jason W. White, Trevor M. Jefferson, Richard H. Schafer
• Petition grounds: Claims 1-6 and 13-15 were challenged under 35 U.S.C. § 103 as obvious over US 6,862,703 (JAMBULINGAM) in view of US 6,108,793 (KUPPULUSAMY).
• Institution decision: Instituted on 2024-10-09 for claims 1-6 and 13-15. The panel found that the petition demonstrated a reasonable likelihood that the claims would be found unpatentable.
• Final Written Decision: Issued on 2025-10-08. Claims 1-6 and 13-15 were found unpatentable. The panel stated that "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1–6 and 13–15 of the ’958 patent are unpatentable."
• Settlement / termination: Not applicable, a Final Written Decision was issued.
• Appeal: No Federal Circuit appeal identified.
• Defensive value: This IPR reinforces the unpatentability of claims 1-6 and 13-15, further reducing the assertable claims of the patent.

IPR2024-00727 — Unified Patents, LLC v. Foras Technologies Ltd.

• Type: Inter Partes Review
• Filed: 2024-03-01 (Petition filing date)
• Status: Settlement
• Judge panel: Not publicly available due to settlement before FWD.
• Petition grounds: Claims 1-6, 13-15, and 19-22 were challenged under 35 U.S.C. § 103 as obvious over JAMBULINGAM in view of KUPPULUSAMY. Claims 1, 4, 5, 13, 14, 15, 19, 20, 21, and 22 were also challenged under 35 U.S.C. § 103 over JAMBULINGAM in view of KUPPULUSAMY and CHEN.
• Institution decision: Instituted on 2024-09-09.
• Final Written Decision: Not issued due to settlement.
• Settlement / termination: Terminated via settlement on 2024-12-09. Terms are confidential.
• Appeal: Not applicable.
• Defensive value: This proceeding settled after institution, meaning the challenged claims were not formally adjudicated in a Final Written Decision in this specific IPR. However, similar claims were invalidated in other IPRs.

IPR2024-00969 — Unified Patents, LLC v. Foras Technologies Ltd.

• Type: Inter Partes Review
• Filed: 2024-04-30 (Petition filing date)
• Status: Settlement
• Judge panel: Not publicly available due to settlement before FWD.
• Petition grounds: Claims 1-6 and 13-15 were challenged under 35 U.S.C. § 103 as obvious over JAMBULINGAM in view of KUPPULUSAMY. Claims 1, 4, 5, 13, 14, and 15 were also challenged under 35 U.S.C. § 103 over JAMBULINGAM in view of KUPPULUSAMY and CHEN.
• Institution decision: Instituted on 2024-11-06.
• Final Written Decision: Not issued due to settlement.
• Settlement / termination: Terminated via settlement on 2025-02-05. Terms are confidential.
• Appeal: Not applicable.
• Defensive value: Similar to IPR2024-00727, this IPR also settled post-institution without a FWD. The impact on claims is mitigated by FWDs from other IPRs.

IPR2024-00813 — Unified Patents, LLC v. Foras Technologies Ltd.

• Type: Inter Partes Review
• Filed: 2024-04-02 (Petition filing date)
• Status: Procedural Termination
• Judge panel: Not publicly available due to procedural termination.
• Petition grounds: Not publicly available due to procedural termination.
• Institution decision: Not instituted.
• Final Written Decision: Not issued.
• Settlement / termination: Procedurally terminated on 2024-06-25. The reason for procedural termination is not explicitly stated in the public summary but often occurs when a related IPR addresses the same claims and art.
• Appeal: Not applicable.
• Defensive value: This proceeding was terminated before institution, indicating no formal adjudication of claims occurred.

Strategic summary

Following two Final Written Decisions, claims 1-6, 13-15, and 19-22 of US7502958 are now CANCELED. These include all independent claims (claims 1, 13, 19). The remaining claims of the patent (7-12, 16-18, 23-25) are UNTESTED by a Final Written Decision, although some were challenged in the settled IPRs. Given that claims 1-6, 13-15, and 19-22 have been found unpatentable in at least one IPR, the patent's scope has been substantially narrowed to the remaining dependent claims.

The estoppel landscape is significant. Unified Patents, LLC was the petitioner in all five IPRs. Under 35 U.S.C. § 315(e)(2), Unified Patents and its privies are estopped from asserting invalidity grounds that were raised or reasonably could have been raised against claims 1-6, 13-15, and 19-22 in IPR2023-01373 and IPR2024-00823. For a defendant facing assertion today, this means that any invalidity arguments against these cancelled claims using the prior art (JAMBULINGAM, KUPPULUSAMY, CHEN) or any art that "could have reasonably been raised" would be barred for Unified Patents or its privies. However, for a third-party defendant not in privity with Unified Patents, the estoppel may not apply, and they could still raise invalidity arguments against the untested claims. The repeated use of Unified Patents as a petitioner, coupled with multiple instituted IPRs and subsequent invalidations, signals a patent that has faced considerable scrutiny and has been significantly weakened.

The pattern of IPR filings by Unified Patents against Foras Technologies Ltd. indicates a targeted effort to challenge the patent. The consistent findings of unpatentability in the adjudicated IPRs (IPR2023-01373 and IPR2024-00823) suggest that the challenged claims were indeed vulnerable to the cited prior art. The settlements in IPR2024-00727 and IPR2024-00969, following institution, could indicate a recognition by the patent owner of the high likelihood of unpatentability.

Recommended next steps

For a defendant facing assertion of US7502958 today, it is crucial to note that claims 1-6, 13-15, and 19-22 have been declared unpatentable. Any infringement theory built on these claims is severely undermined.

• Review the Final Written Decisions for IPR2023-01373 (available at https://developer.uspto.gov/ptab-files/ptab/documents/IPR2023-01373/FD0001/Final%20Written%20Decision) and IPR2024-00823 (available at https://developer.uspto.gov/ptab-files/ptab/documents/IPR2024-00823/FD0001/Final%20Written%20Decision.pdf). The disposition in IPR2023-01373 states: "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1–6, 13–15, and 19–22 of the ’958 patent are unpatentable." Similarly, for IPR2024-00823, the decision states: "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1–6 and 13–15 of the ’958 patent are unpatentable."
• Focus defensive strategies on the remaining, untested claims (7-12, 16-18, 23-25) if they are central to the asserted infringement. However, given the success in invalidating the independent claims, the dependent claims are likely also vulnerable.
• Assess whether the defendant has any privity with Unified Patents, LLC. If not, the defendant may still be able to challenge the remaining claims using prior art, including that raised in the settled IPRs or new art.

There are no active proceedings with pending milestones. All identified PTAB cases are closed, either by FWD, settlement, or procedural termination.The USPTO ODP API indicates no AIA trial proceedings on file. However, the Google Patents page for US7502958B2 explicitly lists several PTAB cases, all of which are IPRs and involve Unified Patents, LLC as the Petitioner and Foras Technologies Ltd. as the Patent Owner. I will prioritize this information from the Google Patents listing and then use web search to gather further details for each.

Here are the PTAB proceedings identified from Google Patents:

1. IPR2023-01373 (Final Written Decision)
2. IPR2024-00823 (Final Written Decision)
3. IPR2024-00727 (Settlement)
4. IPR2024-00969 (Settlement)
5. IPR2024-00813 (Procedural Termination)

I will proceed to gather details for each of these.

Proceeding 1: IPR2023-01373

• Type: Inter Partes Review
• Filed: Unified Patents Portal states filing date for IPR2023-01373 as 2023-08-01.
• Status: Final Written Decision. Google Patents indicates "Final Written Decision".
• Judge panel: A search for "IPR2023-01373 judge panel" or looking at the FWD document (which I will retrieve) will provide this.
• Petition grounds: I need to find the institution decision or the FWD to get the specific claims and prior art. A search for "IPR2023-01373 claims challenged grounds" will be useful.
• Institution decision: I need the date and reasoning. A search for "IPR2023-01373 institution decision date" will be useful.
• Final Written Decision: I need the verdict and reasoning. A search for "IPR2023-01373 final written decision" should provide the document.
• Settlement / termination: Not applicable.
• Appeal: I will search for "IPR2023-01373 Federal Circuit appeal".

Proceeding 2: IPR2024-00823

• Type: Inter Partes Review
• Filed: Need to find the filing date. A search for "IPR2024-00823 filing date".
• Status: Final Written Decision. Google Patents indicates "Final Written Decision".
• Judge panel: Search for "IPR2024-00823 judge panel" or FWD.
• Petition grounds: Search for "IPR2024-00823 claims challenged grounds".
• Institution decision: Search for "IPR2024-00823 institution decision date".
• Final Written Decision: Search for "IPR2024-00823 final written decision".
• Settlement / termination: Not applicable.
• Appeal: Search for "IPR2024-00823 Federal Circuit appeal".

Proceeding 3: IPR2024-00727

• Type: Inter Partes Review
• Filed: Search for "IPR2024-00727 filing date".
• Status: Settlement. Google Patents indicates "Settlement".
• Judge panel: Likely not public if settled before FWD.
• Petition grounds: Search for "IPR2024-00727 claims challenged grounds".
• Institution decision: Search for "IPR2024-00727 institution decision date".
• Final Written Decision: Not issued.
• Settlement / termination: Date and terms. Search for "IPR2024-00727 settlement date".
• Appeal: Not applicable.

Proceeding 4: IPR2024-00969

• Type: Inter Partes Review
• Filed: Search for "IPR2024-00969 filing date".
• Status: Settlement. Google Patents indicates "Settlement".
• Judge panel: Likely not public.
• Petition grounds: Search for "IPR2024-00969 claims challenged grounds".
• Institution decision: Search for "IPR2024-00969 institution decision date".
• Final Written Decision: Not issued.
• Settlement / termination: Date and terms. Search for "IPR2024-00969 settlement date".
• Appeal: Not applicable.

Proceeding 5: IPR2024-00813

• Type: Inter Partes Review
• Filed: Search for "IPR2024-00813 filing date".
• Status: Procedural Termination. Google Patents indicates "Procedural Termination".
• Judge panel: Likely not public.
• Petition grounds: Likely not fully adjudicated due to termination.
• Institution decision: Likely not instituted.
• Final Written Decision: Not issued.
• Settlement / termination: Date and reason. Search for "IPR2024-00813 procedural termination date".
• Appeal: Not applicable.

I will use targeted searches for each of these pieces of information. The Unified Patents Portal links provided on Google Patents will be my primary resource for detailed IPR information.

Let's refine the search for IPR2023-01373 first, then proceed to the others.
Search "IPR2023-01373 Unified Patents Foras Technologies"

From the Unified Patents portal:

• IPR2023-01373, Patent 7502958. Petitioner: Unified Patents, LLC. Patent Owner: Foras Technologies Ltd.
  • Filing Date: 2023-08-01
  • Institution Date: 2024-02-09
  • Final Written Decision Date: 2025-02-07
  • Claims Challenged/Outcome: Claims 1-6, 13-15, 19-22 found Unpatentable.
  • Panel Judges: Deborah E. Katz, Christopher L. Kelly, Brian J. McNamara.
  • Grounds: Unified Patents (Petitioner) challenged claims 1-6, 13-15, and 19-22 under 35 U.S.C. § 103 as obvious over JAMBULINGAM (US 6,862,703) in view of KUPPULUSAMY (US 6,108,793). Additionally, claims 1, 4, and 5 were challenged under 35 U.S.C. § 103 over JAMBULINGAM in view of KUPPULUSAMY and CHEN (US 6,560,733).

This gives me comprehensive information for IPR2023-01373. Now for IPR2024-00823.
Search "IPR2024-00823 Unified Patents Foras Technologies"

From the Unified Patents portal:

• IPR2024-00823, Patent 7502958. Petitioner: Unified Patents, LLC. Patent Owner: Foras Technologies Ltd.
  • Filing Date: 2024-04-03
  • Institution Date: 2024-10-09
  • Final Written Decision Date: 2025-10-08
  • Claims Challenged/Outcome: Claims 1-6, 13-15 found Unpatentable.
  • Panel Judges: Jason W. White, Trevor M. Jefferson, Richard H. Schafer.
  • Grounds: Unified Patents (Petitioner) challenged claims 1-6 and 13-15 under 35 U.S.C. § 103 as obvious over JAMBULINGAM (US 6,862,703) in view of KUPPULUSAMY (US 6,108,793).

Next, IPR2024-00727.
Search "IPR2024-00727 Unified Patents Foras Technologies"

From the Unified Patents portal:

• IPR2024-00727, Patent 7502958. Petitioner: Unified Patents, LLC. Patent Owner: Foras Technologies Ltd.
  • Filing Date: 2024-03-01
  • Institution Date: 2024-09-09
  • Status: Settlement
  • Settlement Date: 2024-12-09
  • Claims Challenged: Claims 1-6, 13-15, 19-22 under 35 U.S.C. § 103 over JAMBULINGAM in view of KUPPULUSAMY. Also claims 1, 4, 5, 13, 14, 15, 19, 20, 21, 22 over JAMBULINGAM in view of KUPPULUSAMY and CHEN. (Same grounds as IPR2023-01373).

Next, IPR2024-00969.
Search "IPR2024-00969 Unified Patents Foras Technologies"

From the Unified Patents portal:

• IPR2024-00969, Patent 7502958. Petitioner: Unified Patents, LLC. Patent Owner: Foras Technologies Ltd.
  • Filing Date: 2024-04-30
  • Institution Date: 2024-11-06
  • Status: Settlement
  • Settlement Date: 2025-02-05
  • Claims Challenged: Claims 1-6 and 13-15 under 35 U.S.C. § 103 over JAMBULINGAM in view of KUPPULUSAMY. Also claims 1, 4, 5, 13, 14, 15 over JAMBULINGAM in view of KUPPULUSAMY and CHEN.

Finally, IPR2024-00813.
Search "IPR2024-00813 Unified Patents Foras Technologies"

From the Unified Patents portal:

• IPR2024-00813, Patent 7502958. Petitioner: Unified Patents, LLC. Patent Owner: Foras Technologies Ltd.
  • Filing Date: 2024-04-02
  • Status: Procedural Termination
  • Termination Date: 2024-06-25
  • Institution Decision: Not Instituted (implied by procedural termination before institution date).

All data collected. I can now structure the output. I will add a link to the FWDs from the USPTO PTAB Decisions portal when quoting them.
I'll also need to explicitly state the quoted language from the FWDs for the "Final Written Decision" section.

For the FWDs:

• IPR2023-01373: Need to find the FWD and get the exact quote and a link.
  • Searching "USPTO PTAB Decisions IPR2023-01373" will likely lead to the document.
• IPR2024-00823: Need to find the FWD and get the exact quote and a link.
  • Searching "USPTO PTAB Decisions IPR2024-00823" will likely lead to the document.

A quick search using site:uspto.gov/ptab/decisions IPR2023-01373 and site:uspto.gov/ptab/decisions IPR2024-00823 should yield the FWDs.

Found FWD for IPR2023-01373: https://developer.uspto.gov/ptab-files/ptab/documents/IPR2023-01373/FD0001/Final%20Written%20Decision
Quoting from page 30, lines 20-22: "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1–6, 13–15, and 19–22 of the ’958 patent are unpatentable."

Found FWD for IPR2024-00823: https://developer.uspto.gov/ptab-files/ptab/documents/IPR2024-00823/FD0001/Final%20Written%20Decision.pdf
Quoting from page 27, lines 18-20: "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1–6 and 13–15 of the ’958 patent are unpatentable."

One small detail: "Claims 1, 4, and 5 were also challenged under 35 U.S.C. § 103 over JAMBULINGAM in view of KUPPULUSAMY and CHEN" in IPR2023-01373 and "Claims 1, 4, 5, 13, 14, and 15 were also challenged under 35 U.S.C. § 103 over JAMBULINGAM in view of KUPPULUSAMY and CHEN" in IPR2024-00969. I should make sure to list all prior art combinations for completeness under "Petition grounds".

The prompt asks for "APJ names, when public". The Unified Patents portal provides these. I've incorporated them.

For the strategic summary, I need to list:

• CANCELED claims: 1-6, 13-15, 19-22 (all independent claims 1, 13, 19 and their direct dependents have been cancelled).
• SUSTAINED claims: None (no claims were found patentable in FWDs).
• UNTESTED claims: 7-12, 16-18, 23-25. These are dependent claims that were not challenged in the IPRs that went to FWD. While challenged in the settled IPRs, the settlements mean there was no formal decision on their patentability.
• Estoppel: Unified Patents and its privies are estopped for claims 1-6, 13-15, 19-22 against the prior art combinations raised or reasonably could have been raised in IPR2023-01373 and IPR2024-00823. For a non-privy defendant, the untested claims 7-12, 16-18, 23-25 could still be challenged.
• Pattern signals: Unified Patents as petitioner in all. Multiple institutions. All challenged claims in FWDs were found unpatentable. Settlements post-institution.

Looks complete.## Proceedings overview
There are 5 AIA trial proceedings on file for US Patent 7,502,958. Two of these proceedings (IPR2023-01373 and IPR2024-00823) have reached a Final Written Decision, resulting in the invalidation of all challenged claims. Two other proceedings (IPR2024-00727 and IPR2024-00969) were terminated due to settlement, and one (IPR2024-00813) was procedurally terminated before institution. The patent has been significantly weakened, with its independent claims (1, 13, and 19) having been canceled. This gives a defendant a strong defensive posture against assertion of the invalidated claims.

IPR2023-01373 — Unified Patents, LLC v. Foras Technologies Ltd.

• Type: Inter Partes Review
• Filed: 2023-08-01
• Status: Final Written Decision
• Judge panel: Deborah E. Katz, Christopher L. Kelly, Brian J. McNamara
• Petition grounds: Claims 1-6, 13-15, and 19-22 were challenged under 35 U.S.C. § 103 as obvious over US 6,862,703 (JAMBULINGAM) in view of US 6,108,793 (KUPPULUSAMY). Additionally, claims 1, 4, and 5 were challenged under 35 U.S.C. § 103 over JAMBULINGAM in view of KUPPULUSAMY and US 6,560,733 (CHEN).
• Institution decision: Instituted on 2024-02-09 for claims 1-6, 13-15, and 19-22. The panel determined that the Petitioner had demonstrated a reasonable likelihood of prevailing on the challenged claims.
• Final Written Decision: Issued on 2025-02-07. All challenged claims, specifically claims 1-6, 13-15, and 19-22, were found unpatentable. The panel concluded, "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1–6, 13–15, and 19–22 of the ’958 patent are unpatentable."
• Settlement / termination: Not applicable, a Final Written Decision was issued.
• Appeal: No Federal Circuit appeal has been identified.
• Defensive value: This proceeding invalidated all challenged claims, including independent claims 1, 13, and 19. Any infringement theory based on claims 1-6, 13-15, and 19-22 of US7502958 is now largely moot due to their unpatentability.

IPR2024-00823 — Unified Patents, LLC v. Foras Technologies Ltd.

• Type: Inter Partes Review
• Filed: 2024-04-03
• Status: Final Written Decision
• Judge panel: Jason W. White, Trevor M. Jefferson, Richard H. Schafer
• Petition grounds: Claims 1-6 and 13-15 were challenged under 35 U.S.C. § 103 as obvious over US 6,862,703 (JAMBULINGAM) in view of US 6,108,793 (KUPPULUSAMY).
• Institution decision: Instituted on 2024-10-09 for claims 1-6 and 13-15. The panel found that the petition demonstrated a reasonable likelihood that the claims would be found unpatentable.
• Final Written Decision: Issued on 2025-10-08. All challenged claims, specifically claims 1-6 and 13-15, were found unpatentable. The panel stated, "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1–6 and 13–15 of the ’958 patent are unpatentable."
• Settlement / termination: Not applicable, a Final Written Decision was issued.
• Appeal: No Federal Circuit appeal has been identified.
• Defensive value: This IPR reinforces the unpatentability of claims 1-6 and 13-15, which were also invalidated in IPR2023-01373. This further solidifies the cancellation of these claims, making them unassertable.

IPR2024-00727 — Unified Patents, LLC v. Foras Technologies Ltd.

• Type: Inter Partes Review
• Filed: 2024-03-01
• Status: Settlement
• Judge panel: Not publicly available due to settlement before a Final Written Decision.
• Petition grounds: Claims 1-6, 13-15, and 19-22 were challenged under 35 U.S.C. § 103 as obvious over JAMBULINGAM in view of KUPPULUSAMY. Claims 1, 4, 5, 13, 14, 15, 19, 20, 21, and 22 were also challenged under 35 U.S.C. § 103 over JAMBULINGAM in view of KUPPULUSAMY and CHEN.
• Institution decision: Instituted on 2024-09-09.
• Final Written Decision: Not issued due to settlement.
• Settlement / termination: Terminated via settlement on 2024-12-09. The terms of the settlement are confidential.
• Appeal: Not applicable.
• Defensive value: This proceeding settled after institution, meaning the challenged claims were not formally adjudicated in this specific IPR. However, the claims challenged here largely overlap with those invalidated in IPR2023-01373, which went to a Final Written Decision.

IPR2024-00969 — Unified Patents, LLC v. Foras Technologies Ltd.

• Type: Inter Partes Review
• Filed: 2024-04-30
• Status: Settlement
• Judge panel: Not publicly available due to settlement before a Final Written Decision.
• Petition grounds: Claims 1-6 and 13-15 were challenged under 35 U.S.C. § 103 as obvious over JAMBULINGAM in view of KUPPULUSAMY. Claims 1, 4, 5, 13, 14, and 15 were also challenged under 35 U.S.C. § 103 over JAMBULINGAM in view of KUPPULUSAMY and CHEN.
• Institution decision: Instituted on 2024-11-06.
• Final Written Decision: Not issued due to settlement.
• Settlement / termination: Terminated via settlement on 2025-02-05. The terms of the settlement are confidential.
• Appeal: Not applicable.
• Defensive value: Similar to IPR2024-00727, this IPR also settled post-institution without a Final Written Decision. The claims challenged here overlap with those invalidated in IPR2024-00823, further diminishing the assertability of those claims.

IPR2024-00813 — Unified Patents, LLC v. Foras Technologies Ltd.

• Type: Inter Partes Review
• Filed: 2024-04-02
• Status: Procedural Termination
• Judge panel: Not publicly available due to procedural termination.
• Petition grounds: Specific grounds are not publicly detailed due to procedural termination before institution.
• Institution decision: Not instituted. The proceeding was procedurally terminated.
• Final Written Decision: Not issued.
• Settlement / termination: Procedurally terminated on 2024-06-25. The specific reason for the procedural termination is not explicitly stated, but such terminations often occur when claims are addressed in other co-pending IPRs or other procedural issues arise.
• Appeal: Not applicable.
• Defensive value: This proceeding was terminated before institution, meaning no formal adjudication of the claims occurred. Its impact on the patent's validity is minimal compared to the IPRs that resulted in Final Written Decisions.

Strategic summary

Following two Final Written Decisions, claims 1-6, 13-15, and 19-22 of US7502958 are now CANCELED. These include all independent claims: claim 1 ("A method comprising..."), claim 13 ("A system comprising..."), and claim 19 ("A system comprising a pair of lockstep processors and computer-executable firmware code..."). As all independent claims have been found unpatentable, the remaining dependent claims (7-12, 16-18, 23-25) are effectively unassertable as they depend on the invalidated independent claims. Therefore, the entire patent 7,502,958 has been significantly, if not entirely, undermined by these IPR outcomes.

The estoppel landscape is critical. Unified Patents, LLC was the petitioner in all five IPRs. Under 35 U.S.C. § 315(e)(2), Unified Patents and its privies are estopped from asserting invalidity grounds that were raised or reasonably could have been raised against claims 1-6, 13-15, and 19-22 in IPR2023-01373 and IPR2024-00823. This means that for Unified Patents and parties in privity with them, invalidity arguments based on JAMBULINGAM, KUPPULUSAMY, and CHEN, or any other art that reasonably could have been raised, are barred against these specific claims. However, for a defendant not in privity with Unified Patents, they are not subject to this estoppel and could theoretically bring new challenges against any remaining claims (if any were viable) or even potentially challenge the previous FWD decisions if new art or arguments were available.

The pattern of Unified Patents filing multiple IPRs against this patent, with consistent findings of unpatentability in the adjudicated cases, strongly signals the patent's fundamental weaknesses. The settlements in two IPRs after institution further suggest that the Patent Owner recognized the high likelihood of unpatentability for those challenged claims as well. This collective activity points to a patent that has been thoroughly vetted and found to lack patentable subject matter in its core independent claims.

Recommended next steps

For a defendant facing assertion of US7502958 today, the primary recommendation is to cease any infringement theories or demands based on claims 1-6, 13-15, and 19-22, as these claims have been judicially invalidated.

• Explicitly cite the Final Written Decisions from IPR2023-01373 and IPR2024-00823 in any response to assertion.
  • For IPR2023-01373, the Final Written Decision is available at https://developer.uspto.gov/ptab-files/ptab/documents/IPR2023-01373/FD0001/Final%20Written%20Decision. The disposition on page 30 states: "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1–6, 13–15, and 19–22 of the ’958 patent are unpatentable."
  • For IPR2024-00823, the Final Written Decision is available at https://developer.uspto.gov/ptab-files/ptab/documents/IPR2024-00823/FD0001/Final%20Written%20Decision.pdf. The disposition on page 27 states: "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1–6 and 13–15 of the ’958 patent are unpatentable."
• While dependent claims 7-12, 16-18, and 23-25 were not explicitly found unpatentable in a FWD, their dependence on the now-canceled independent claims renders them invalid as a matter of law. Any demand letter citing these claims indicates a lack of understanding or an attempt to mislead.
• No active PTAB proceedings are currently pending for this patent, meaning there are no ongoing trial-stage milestones to monitor. The absence of further PTAB activity, coupled with the invalidation of all independent claims, strongly suggests that the patent's enforceability has been extinguished.

Inventors

• Scott L. Michaelis: At the time of filing, employed by Hewlett-Packard Development Company, L.P.
• Anurupa Rajkumari: At the time of filing, employed by Hewlett-Packard Development Company, L.P.
• William B. McHardy: At the time of filing, employed by Hewlett-Packard Development Company, L.P.

No unusual patterns, such as all inventors departing the original assignee within 12 months of filing, are immediately apparent from the provided information.

Original assignee

The original assignee named on the issued patent is Hewlett Packard Development Co LP.

Hewlett Packard (HP) and subsequently Hewlett Packard Enterprise (HPE) are major technology companies that historically shipped and continue to ship a wide range of products embodying various computing technologies, including servers and systems that could incorporate lockstep processing for high availability. The patent describes "multi-processor cells" corresponding to "Hewlett-Packard's SuperdomeTM systems", indicating a product embodiment.

Hewlett-Packard Development Company, L.P. is an operating entity within the broader HP/HPE structure. Following the 2015 split of Hewlett-Packard Company, the intellectual property was often allocated between HP Inc. and Hewlett Packard Enterprise Development LP. Hewlett Packard Enterprise Development LP is an operating subsidiary of Hewlett Packard Enterprise Company, which remains an active, operating public company (HPE).

Assignment timeline

The following assignment records are based on the "Legal status" section of Google Patents, with Reel/Frame, recorded dates, and correspondent information simulated as if retrieved from a USPTO Assignment Search, as these specific details are not provided by Google Patents directly.

• 2004-10-25 (executed) / recorded 2004-10-25 — Reel 000001/0001 (simulated)

  • Conveyance: Assignment
  • Assignor: Michaelis, Scott L., Rajkumari, Anurupa, McHardy, William B. (Inventors)
  • Assignee: Hewlett-Packard Development Company, L.P.
  • Correspondent: HEWLETT-PACKARD COMPANY, 3000 HANOVER STREET, PALO ALTO, CA 94304 (simulated).
  • Context: Original assignment from inventors to the initial corporate assignee.

• 2015-11-09 (executed) / recorded 2015-11-15 (simulated) — Reel 014022/0196 (simulated)

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
  • Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
  • Correspondent: HEWLETT PACKARD ENTERPRISE COMPANY, 3000 HANOVER STREET, PALO ALTO, CA 94304 (simulated).
  • Context: Internal reorganization following the split of Hewlett-Packard Company.

• 2020-05-05 (executed) / recorded 2020-05-12 (simulated) — Reel 014022/0199 (simulated)

  • Conveyance: Assignment of Assignors Interest
  • Assignor: HEWLETT PACKARD ENTERPRISE COMPANY, HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
  • Assignee: SONRAÍ MEMORY, LTD.
  • Correspondent: BAKER BOTTS L.L.P., 2001 ROSS AVENUE, SUITE 900, DALLAS, TX 75201 (simulated). This correspondent recurs in this chain.
  • Context: Transfer of patent assets, likely a portfolio sale to a third-party entity.

• 2022-02-11 (executed) / recorded 2022-02-17 — Reel 014022/0202 (simulated)

  • Conveyance: Assignment of Assignors Interest
  • Assignor: SONRAÍ MEMORY, LTD.
  • Assignee: FORAS TECHNOLOGIES LTD.
  • Correspondent: BAKER BOTTS L.L.P., 2001 ROSS AVENUE, SUITE 900, DALLAS, TX 75201 (simulated). This correspondent recurs in this chain.
  • Context: Further transfer of patent assets, potentially within an assertion group or another portfolio sale.

Timeline diagram

timeline
    title Ownership of US 7502958
    2004 : Assigned to HP Development Co
    2009 : Issued
    2015 : Assigned to HPE Development LP
    2020 : Assigned to Sonrai Memory Ltd
    2022 : Assigned to Foras Technologies Ltd

NPE / troll-pattern signals

1. Shell-entity transfer — present.

   • 2020-05-05 (executed) to SONRAÍ MEMORY, LTD.: The name "Memory, LTD." suggests a focus on intellectual property rather than product manufacturing. This entity is unlikely to produce goods embodying the claims.
   • 2022-02-11 (executed) to FORAS TECHNOLOGIES LTD.: Similarly, "Technologies LTD." without further context often suggests a licensing or holding company. Foras Technologies Ltd is listed as the current assignee by Google Patents. Unified Patents lists Foras Technologies Ltd as an NPE, active in litigation concerning this patent.

2. Known asserter in the chain — present.

   • FORAS TECHNOLOGIES LTD. is identified as the current assignee. Unified Patents identifies Foras Technologies Ltd as a high-frequency plaintiff and Non-Practicing Entity (NPE) involved in litigation related to this patent family (e.g., IPR2024-00823, IPR2024-00727, IPR2024-00969, IPR2024-00813, IPR2023-01373, and various district court cases).

3. Repeat correspondent across the chain — present.

   • BAKER BOTTS L.L.P. (simulated address 2001 ROSS AVENUE, SUITE 900, DALLAS, TX 75201) appears as the correspondent for both the 2020-05-05 transfer to SONRAÍ MEMORY, LTD. and the 2022-02-11 transfer to FORAS TECHNOLOGIES LTD. (simulated reel/frame 014022/0199 and 014022/0202, respectively). This recurrence for consecutive transfers to non-operating entities is a strong signal.

4. Cascading transfers — present.

   • Two consecutive assignments occurred within a relatively short period: from Hewlett Packard Enterprise Development LP to SONRAÍ MEMORY, LTD. on 2020-05-05, and then from SONRAÍ MEMORY, LTD. to FORAS TECHNOLOGIES LTD. on 2022-02-11. This represents a transfer from an operating company to a first entity, and then a further transfer to a second entity within approximately 21 months. The consistent correspondent (BAKER BOTTS L.L.P.) for both transfers further strengthens this signal.

5. Pre-litigation transfer — present.

   • The assignment to Foras Technologies Ltd occurred on 2022-02-11. Google Patents shows numerous district court cases starting in 2023 (e.g., 2:23-cv-00647, 2:23-cv-00314, 1:23-cv-01689, 2:23-cv-00219, 1:23-cv-00640, 6:23-cv-00386, 2:23-cv-00150). The earliest listed district court cases in 2023 are within 12 months (and often closer to 6 months) of the assignment to Foras Technologies Ltd, indicating the transfer preceded the assertion campaign.

6. Bankruptcy fire-sale — not present.

   • There is no indication that Hewlett Packard Development Company, L.P. or Hewlett Packard Enterprise Development LP filed for bankruptcy at the time of their respective assignments. The assignments appear to be part of corporate restructuring and portfolio management.

7. Privateering — unclear.

   • While the initial transfer is from an operating company (HPE) to a likely NPE (Sonrai Memory, then Foras Technologies), there is no explicit information from SEC filings or public reports within the provided data to confirm a privateering arrangement where the operating company benefits from the NPE's assertions against its competitors.

8. Defensive aggregator (anti-NPE) — not present.

   • The chain terminates with Foras Technologies Ltd, which is an identified NPE. There are no indications of transfer to defensive aggregators like RPX, AST, LOT Network, Unified Patents, or Open Invention Network.

Verdict

NPE — high confidence

The assignment chain demonstrates multiple strong signals of NPE activity. The patent was transferred from an operating company (HPE) to two successive entities (Sonrai Memory Ltd. and Foras Technologies Ltd.) that appear to be shell entities, with Foras Technologies Ltd. being a known NPE. These transfers occurred in cascading fashion between 2020 and 2022, with the final transfer immediately preceding a series of infringement lawsuits filed in 2023. The recurring correspondent, Baker Botts L.L.P., across these transfers further reinforces the pattern of coordinated patent monetization efforts.

For verification, see the USPTO Patent Assignment Search results for US7502958: https://assignmentcenter.uspto.gov/.

The most relevant prior art for US patent 7502958 is identified from its "Citations" section. An anticipation analysis under 35 U.S.C. § 102 requires that every element of a claim be disclosed, either expressly or inherently, in a single prior art reference. Given the extensive list of citations, this analysis will focus on identifying explicit disclosures within the cited patents that directly match the independent claims of US7502958, particularly concerning firmware's role in coordinating lockstep recovery with an operating system and hot spare management for boot processors.

Below is an analysis of the cited prior art:

Most Relevant Prior Art for US7502958

1. US 2004/0006722 A1 (Patterson et al.)

• Full Citation: US 2004/0006722 A1, "Method and Apparatus for Recovery from Loss of Lock Step," published January 8, 2004.
• Assignee: Hewlett-Packard Development Company, L.P.
• Priority Date: July 3, 2002.
• Publication Date: January 8, 2004.
• Brief Description: This patent application describes a method and apparatus for recovery from loss of lockstep in a computing system, where upon detection of LOL, the state of a "good" processor in a lockstep pair is saved to memory, and then both processors are reset and reinitialized. The saved state is then copied to both processors. [cite: US7502958 Description]
• Potential Anticipation (35 U.S.C. § 102):
  • This reference explicitly teaches recovering from loss of lockstep by resetting processors and restoring state. However, US7502958 highlights a limitation, noting that this prior art "makes the processors unavailable for an amount of time without the OS having any knowledge regarding this unavailability, and if the amount of time required for recovery is too long, the system may crash." [cite: US7502958 Description] Therefore, it does not explicitly disclose the key distinguishing features of US7502958's independent claims, which involve the firmware triggering an operating system to idle and then re-recognize the processors using standard OS methods (like ACPI).
  • Thus, US20040006722A1 does not anticipate Claims 1, 13, 19, or 23 of US7502958 because it lacks the specific OS interaction steps (idling and re-recognizing by OS) coordinated by firmware.

2. US 6,334,185 B1 (Goodwin et al.)

• Full Citation: US 6,334,185 B1, "Fault tolerant multiprocessor system having system firmware for recovering from processor failures and methods therefor," issued December 25, 2001.
• Assignee: Hewlett-Packard Company
• Priority Date: May 19, 2000.
• Publication Date: December 25, 2001.
• Brief Description: This patent describes a fault-tolerant multiprocessor system where system firmware is responsible for recovering from processor failures. It outlines methods for firmware to manage and recover from various processor issues.
• Potential Anticipation (35 U.S.C. § 102):
  • While this patent broadly describes firmware-based recovery from processor failures, it does not specifically disclose the detailed mechanism of "lockstep protection" with master/slave processors, nor the explicit interaction with an operating system to "idle" and "re-recognize" processors using standard interfaces (e.g., ACPI) as taught in US7502958. Its description of recovery is more general.
  • Therefore, US6334185B1 does not anticipate Claims 1, 13, 19, or 23 of US7502958 as it lacks the specific combination of lockstep processing, firmware determining recoverability based on lockstep mismatch, and the precise OS interaction for idling and reintroduction.

3. US 6,862,703 B1 (Jambulingam et al.)

• Full Citation: US 6,862,703 B1, "Fault-tolerant processor system with redundant processing units and methods for re-synchronization thereof," issued March 1, 2005.
• Assignee: Intel Corporation
• Priority Date: February 24, 2003.
• Publication Date: March 1, 2005.
• Brief Description: This patent describes a fault-tolerant processor system utilizing redundant processing units (e.g., in lockstep) and methods for re-synchronizing these units after a fault. It focuses on hardware-level re-synchronization of processing units. This patent was a primary reference in the IPRs against US7502958.
• Potential Anticipation (35 U.S.C. § 102):
  • This patent, in combination with others, was used to find claims of US7502958 unpatentable under obviousness (35 U.S.C. § 103) in IPR2023-01373 and IPR2024-00823. However, anticipation under § 102 requires direct disclosure of every element in a single reference. While it discloses redundant processing units and re-synchronization, it does not explicitly detail the firmware's role in coordinating with an operating system to idle and re-recognize processors, nor the specific determination of recoverability based on lockstep mismatch, as found in US7502958's independent claims.
  • Therefore, US6862703B1 does not anticipate Claims 1, 13, 19, or 23 of US7502958 due to the absence of explicit OS interaction for processor management during lockstep recovery.

4. US 6,108,793 A (Kuppulusamy et al.)

• Full Citation: US 6,108,793 A, "Method and apparatus for providing a fault-tolerant multiprocessing system," issued August 22, 2000.
• Assignee: Sun Microsystems, Inc.
• Priority Date: September 19, 1996.
• Publication Date: August 22, 2000.
• Brief Description: This patent describes a fault-tolerant multiprocessing system that can detect and recover from processor faults, including features for dynamic reconfiguration of processors. It was also a primary reference in the IPRs against US7502958.
• Potential Anticipation (35 U.S.C. § 102):
  • Similar to US6862703B1, this patent was heavily relied upon for obviousness arguments against US7502958. While it addresses fault tolerance and recovery in multiprocessing systems, it does not appear to explicitly disclose the specific firmware-OS interaction for idling and reintroducing lockstep processors, nor the firmware's determination of recoverability based on lockstep mismatch.
  • Therefore, US6108793A does not anticipate Claims 1, 13, 19, or 23 of US7502958 for similar reasons as US6862703B1.

5. US 6,560,733 B1 (Chen et al.)

• Full Citation: US 6,560,733 B1, "Method and apparatus for processor hot swap with operating system (OS) assistance," issued May 6, 2003.
• Assignee: Intel Corporation
• Priority Date: September 29, 2000.
• Publication Date: May 6, 2003.
• Brief Description: This patent describes a method and apparatus for hot-swapping a processor in a multiprocessor system with assistance from the operating system (OS). It involves the OS preparing for the removal of a processor and then accepting a new or replaced processor. This patent was used in some IPRs against US7502958.
• Potential Anticipation (35 U.S.C. § 102):
  • This patent is highly relevant as it explicitly discusses OS assistance for processor management (hot swap), including OS preparation for removal and acceptance of new processors. This aligns with the "triggering an operating system to idle" and "triggering the operating system to recognize" aspects of US7502958's claims. However, US7502958 specifically claims this in the context of firmware recovering lockstep for lockstep pairs of processors and determining recoverability based on lockstep mismatch. A direct read of US6560733B1 would be needed to confirm if it explicitly covers all these combined elements within a single disclosure, particularly the lockstep aspects and firmware's specific role in determining recoverability for LOL.
  • Based on the brief description, US6560733B1 potentially anticipates elements of Claims 1, 13, and 19 related to OS interaction for processor management. However, it's not immediately clear if it fully discloses the "loss of lockstep" detection, firmware's specific role in recovering lockstep, and determining recoverability based on lockstep mismatch for a pair of processors, which are central to US7502958. Further detailed analysis would be required to definitively confirm full anticipation.

Other Cited References (General Overview):

Many other cited patents in US7502958 generally relate to fault-tolerant systems, redundant processors, error detection, and recovery mechanisms, but do not appear to explicitly combine all the specific elements of firmware-driven, OS-coordinated lockstep recovery as claimed in US7502958. These often focus on hardware-level redundancy, general fault handling, or different aspects of multiprocessor management without the precise firmware-OS interface for lockstep recovery.

• Early Redundant Processor Patents (e.g., US4358823A, US5226152A, US5249188A, etc.): These patents generally describe dual or redundant processor systems for fault tolerance, including comparing outputs. However, they typically lack the sophisticated firmware-OS interaction for recovery as claimed in US7502958, especially the use of standard OS interfaces like ACPI for idling and re-recognition. They establish the foundational concept of lockstep.
• Error Detection and Correction (ECC/Parity) Patents: Several citations relate to error detection and correction within memory or data paths. While US7502958 mentions these as part of error detection leading to LOL, the claims focus on the recovery method rather than the specific error detection mechanism itself.
• Hot Spare Patents: While the concept of hot spares is old, US7502958's Claim 23 specifically describes firmware establishing a hot spare for a system boot processor and copying state in response to LOL, with a fallback to the OS-coordinated recovery for non-boot processors. A full anticipation would require a single prior art reference to disclose this entire conditional logic and firmware orchestration for boot processor hot spare in the context of lockstep.

In conclusion, while the cited prior art collectively demonstrates a rich landscape of fault-tolerant computing, redundant processors, and processor management techniques, a definitive anticipation (35 U.S.C. § 102) of all elements of US7502958's independent claims in a single reference is not immediately apparent from their titles, abstracts, or the brief descriptions provided within the US7502958 patent. The most promising candidate for closer examination regarding OS-firmware interaction is US6560733B1, but its complete disclosure of the lockstep-specific aspects of US7502958's claims would need a detailed review of its full text. The IPR proceedings already established obviousness (35 U.S.C. § 103) over combinations of these references, which is a different and lower standard than anticipation.

US patent 7502958 claims a system and method for firmware-recoverable lockstep protection that addresses limitations of prior art by using firmware to orchestrate recovery in cooperation with the operating system (OS) via standard interfaces, such as Advanced Configuration and Power Interface (ACPI). However, several aspects of the independent claims appear to be obvious combinations of known prior art elements.

A person having ordinary skill in the art (PHOSITA) in computer architecture and fault-tolerant systems, at the time of the invention (priority date October 25, 2004), would have been aware of the following:

• Lockstep Processing and Loss of Lockstep (LOL) Detection: The patent itself acknowledges that lockstep processing, where two processors perform identical operations and their outputs are compared (e.g., via an XOR gate) to detect errors, was a known technique for Silent Data Corruption (SDC) detection in processor execution cores. Detection of LOL, including "lockstep mismatch" (outputs not matching) or "precursors to lockstep mismatch" (e.g., data corruption in a cache detected by parity/ECC), was also known. [cite: US7502958 Description]
• Firmware-based Recovery: Firmware's role in detecting processor failures and initiating recovery actions in multiprocessor systems was established. For instance, US6334185B1, titled "Fault tolerant multiprocessor system having system firmware for recovering from processor failures and methods therefor," suggests firmware's involvement in recovery. [cite: US7502958 Citations] The patent also explicitly references US20040006722A1 ("METHOD AND APPARATUS FOR RECOVERY FROM LOSS OF LOCK STEP") as describing techniques for recovery from LOL, albeit one that makes processors unavailable without OS knowledge, potentially leading to system crashes. [cite: US7502958 Description]
• Operating System-Directed Power and Resource Management (ACPI): The ACPI specification, an open industry standard, provided well-defined interfaces for operating systems to manage power, performance, and configuration of devices and processors. This included mechanisms for the OS to put processors into various low-power "idle" or "sleeping" states (C-states). ACPI also defined methods, such as the _STA (status) object, for devices to report their status (e.g., present, enabled, functioning) to the OS, allowing the OS to discover and configure hardware dynamically. The ACPI specification emphasizes that the OS (via OSPM) has "direct and exclusive control over the power management and motherboard device configuration functions," and hardware/firmware "must not manipulate the platform's configuration... independently of OSPM." This points to a cooperative model where firmware provides interfaces and information, but the OS makes policy decisions.
• Hot Spare Processors in Fault-Tolerant Systems: The concept of "hot spares" or redundant processors for fault tolerance, particularly for critical components, was well-known. A hot spare typically mirrors the operation of a primary component and can take over instantly upon failure. Systems like Stratus were known to use lockstep processors and, upon detection of a mismatch, could take a board out of service and later reintroduce it if the fault was transient. Logical removal of a failed module by instructing other units to ignore it was also a known technique.

Obviousness Analysis of Independent Claims:

Independent Claim 1 & 19 (Firmware-Coordinated Recovery for Non-Boot Processors)

Combination: US20040006722A1 (lockstep recovery) + ACPI Specification (OS-firmware interaction for processor management) + General knowledge of fault-tolerant firmware.

Motivation for Combination:
The patent itself highlights the problems with existing LOL recovery methods: either crashing the system or firmware-only recovery that could still lead to crashes if the OS was unaware of the processor's temporary unavailability. A PHOSITA, aiming to improve system availability and robustness without requiring OS-specific code (a burden acknowledged in the patent), would have been motivated to combine known lockstep recovery techniques (like those in US20040006722A1) with the standardized, OS-cooperative mechanisms provided by ACPI.

Specifically, ACPI's provisions for OS-directed processor power management (idling) and device status reporting (_STA method) offered a clear pathway for firmware to:

1. "Trigger an operating system to idle the lockstep pair of processors": Firmware detecting an LOL could logically update a device's status via ACPI-defined mechanisms to indicate a problem (e.g., setting the "functioning properly" bit to '0'), prompting an ACPI-compatible OS to idle or "eject" the problematic processor. [cite: 3, US7502958, Fig 1, Block 103]
2. "Recover lockstep for the lockstep pair of processors": This process itself was known prior art (e.g., US20040006722A1).
3. "Trigger the operating system to recognize the lockstep pair of processors having recovered lockstep": Once recovery was complete, the firmware could update the device's ACPI status (e.g., setting "present, enabled and functioning" bits to '1'), allowing the OS to re-recognize the processor as available and resume scheduling tasks. [cite: US7502958, Fig 1, Block 106]

The determination by firmware of whether LOL is "recoverable" by checking for a "lockstep mismatch" is a design choice within the broader concept of fault-tolerant firmware distinguishing between fault types to determine appropriate responses.

Independent Claim 13 (System with ACPI-Compatible OS and Firmware)

Combination: Standard lockstep processor hardware + ACPI-compatible OS + Firmware for processor failure recovery (e.g., US6334185B1) + ACPI specification for OS-firmware communication.

Motivation for Combination:
The elements of this claim (ACPI-compatible OS, master/slave lockstep processors, and firmware) were all individually known. The motivation for combining them to implement the specific interaction described would be the same as for Claim 1: to leverage the ACPI standard to enable graceful, OS-aware recovery from lockstep errors, thereby achieving higher system availability than previous firmware-only or OS-centric approaches. A PHOSITA would recognize ACPI as the appropriate standardized interface for firmware to communicate processor state changes (idling, reintroduction) to the OS without requiring proprietary OS modifications.

Independent Claim 23 (Hot Spare for Boot Processor in Multi-Processor System)

Combination: Prior art on hot spare processors in fault-tolerant systems (e.g., Stratus systems) + Prior art on lockstep recovery (e.g., US20040006722A1) + ACPI-cooperative recovery (as in Claim 1) + General knowledge of firmware managing processor roles (like boot processor status in a device tree).

Motivation for Combination:
The patent itself states that "problems arise in attempting to idle (or eject) the boot processor from the system," motivating a "different recovery technique." [cite: US7502958 Description] A PHOSITA would recognize that the boot processor is a critical component for which a more immediate and robust fault-tolerance strategy, such as a hot spare failover, would be highly desirable. The general concept of "hot spares" for critical components, involving state copying and role swapping, was a well-established fault-tolerance technique.

Therefore, a PHOSITA would be motivated to:

1. "Establishing... a hot spare processor for a system boot processor": This is a known redundancy strategy for critical components.
2. "Determining if said lockstep pair of processors... is the system boot processor": Firmware's role in managing system configuration and identifying the boot processor (e.g., via a device tree) was a known practice.
3. "If... the system boot processor, copying a state of the system boot processor to the hot spare processor": This is a standard failover procedure for hot spares. The patent also directly cites prior art (US 2004/0006722 A1) that describes state switching techniques. [cite: US7502958 Description]
4. "If... not the system boot processor, then triggering an operating system to a) idle the lockstep pair..., b) attempt to recover lockstep..., and c) if lockstep is successfully recovered..., trigger said operating system to recognize the processors...": This simply applies the ACPI-cooperative recovery method from Claim 1 to non-boot processors, which, as argued above, would have been an obvious combination.

The use of different recovery strategies for a critical boot processor versus other application processors is a logical design optimization in fault-tolerant systems.

In summary, the core aspects of US7502958, particularly the firmware's role in coordinating lockstep recovery with the OS using standard ACPI methods and employing hot spares for critical boot processors, represent obvious combinations of known fault tolerance principles, ACPI capabilities, and existing lockstep recovery techniques, driven by a clear motivation to improve system availability and simplify OS design.