US 6871264

Patent Overview: US 6871264 B2

Title: System and method for dynamic processor core and cache partitioning on large-scale multithreaded, multiprocessor integrated circuits

Patent number: US 6871264 B2 (application US10/092,645; publication US20030172234A1)

Inventor: Donald C. Soltis, Jr.

Original assignee: Hewlett Packard Development Co LP (later reassignments listed, including Hewlett Packard Enterprise Development LP and Valtrus Innovations Ltd)

Key dates: Priority/filing 2002-03-06; publication 2005-03-22; legal status listed as "Expired – Lifetime," adjusted expiration 2022-09-16.

Purpose: The invention pertains to design and packaging of large, complex integrated circuits such as multiprocessor circuits. It relates to an apparatus and method for dynamically repartitioning Multiple CPU integrated circuits so that critical-path threads may receive needed resources and system performance may thereby be optimized.

Plain-language scope (from the supplied excerpt): Modern high-performance processor circuits include on-die cache built as multiple memory blocks with control logic; some designs allow cache portions to be disabled via bonding options or defective blocks to be replaced with spare blocks. Multiprocessor and multithreaded machines run multiple threads, and operating systems (Windows 2000, VMS, UNIX) maintain thread priorities derived from administrator-set base priorities, which govern thread execution and preemption. On such machines, different processors may execute different ready threads. Because cache size and architecture strongly affect hit rate—and low hit rates drastically impair performance—and because multiple-processor circuits typically allocate predetermined cache amounts per processor (requiring total cache equal to processors times the cache needed by the most cache-intensive expected thread), the invention addresses dynamically repartitioning processor cores and cache so critical-path threads get needed resources.

Source: https://patents.google.com/patent/US6871264/en

What the excerpt does not establish: It contains no claims, no detailed description of the repartitioning mechanism, no stated figures, and no named prior-art references beyond general background mentions (e.g., IBM Power-4, PA 8800). It does not establish claim scope, validity, infringement, or specifics of how partitioning is triggered or implemented.