Invalidity dossier

US 6836290

Combined single-ended and differential signaling interface

Current assignee: Re Secured Networks LLC

Added 9/23/2026, 2:57:17 PM

At a glanceNo PTAB challengesNo litigation on file

Active provider: DeepSeek · deepseek-flash

Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

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Patent Overview — US 6836290 B1

Title: Combined single-ended and differential signaling interface

Patent number / application: US 6836290 B1; Application US09/302,090, filed 1999-04-29.

Inventors: Randall M. Chung, Ferry Gunawan, Dino D. Trotta.

Original assignee: Conexant Systems LLC (later listed current assignees include Re Secured Networks LLC and Conexant Systems LLC).

Key dates: Priority date 1998-04-17; filing date 1999-04-29; granted/publication date 2004-12-28; anticipated expiration 2018-04-17. Status listed as "Expired - Lifetime."

Purpose and plain-language scope (from the supplied text): The invention relates to interface circuits, and more particularly to interface circuitry for providing selectable single-ended and differential signal output from a CMOS image sensor to an external digital signal processor. The problem described is that single-ended interfaces are simple and common but can introduce noise and ground bounce at high data rates, while differential interfaces reduce power and noise but normally require twice the number of pins (true and complement lines per bit). The stated desired solution is an interface selectable to support either single-ended or differential operation using the same number of pins, allowing flexibility with both commonly available single-ended image processing devices and newer low-noise differential devices. The background discusses single-ended driver/receiver arrangements, conventional LVDS current-mode signaling into a 100 Ω termination resistor, power comparisons with RS 422 and PECL/ECL, and LVDS receiver fail-safe behavior. A CMOS imager chip with ADC and companion image processor chip with A/D-converted digital signals Din0…Dinn, drivers, receivers, and outputs Dout0…Doutn are described. However, the excerpt cuts off mid-sentence and does not present the claims, detailed description of the selectable circuit, or figures.

What the excerpt does not establish: It does not establish the actual claim scope, the specific circuit implementation, how pin sharing is achieved, enable/select mechanisms, or any comparison results. It also does not establish validity, enforceability, ownership history, or prior-art effect. No litigation, transfer, or validity analysis is offered here, and none should be inferred.

Source: https://patents.google.com/patent/US6836290/en

Generated 10/1/2026, 9:51:52 PM

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Litigation summary

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Proceedings on file (0)

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No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.

PTAB challenges

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Assignment history

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Prior art

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Obviousness

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Extensions

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Derivative works

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