US 6832194

Here's a concise summary of US Patent 6832194:

US Patent 6832194: Audio recognition peripheral system

• Title: Audio recognition peripheral system
• Assignee: Sensory Inc [cite: US6832194B1]
• Inventors: Forrest S. Mozer, Robert E. Savoie, William T. Teasley [cite: US6832194B1]
• Filing Date: October 26, 2000 [cite: US6832194B1]
• Issue Date: December 14, 2004 [cite: US6832194B1]
• Abstract: The patent describes a novel audio recognition peripheral system and method. It features an audio recognition peripheral and a programmable processor (e.g., microprocessor or microcontroller). In one embodiment, the peripheral includes a feature extractor and a vector processor. The feature extractor receives an audio signal, extracts recognition features, and transmits them to the programmable processor for processing with an audio recognition algorithm. The programmable processor then directs the peripheral's vector processor to handle computationally intensive vector operations, thereby offloading processing from the main processor. [cite: US6832194B1]

Plain-Language Overview of Independent Claims:

• Claim 1 (System Claim): This claim describes an audio recognition system that splits the workload between two integrated circuits. A first integrated circuit has a programmable processing unit that runs an audio recognition algorithm. A second integrated circuit acts as a peripheral and contains a feature extractor (which includes a filter unit, filter controller, and block generator) and a vector processor. The feature extractor processes an audio signal to produce "feature extraction data." This data is sent to the programmable processing unit, which starts executing the audio recognition algorithm. During this execution, the vector processor on the second integrated circuit performs specific vector operations on multiple sets of data (vectors).
• Claim 17 (System Claim with "Means-Plus-Function" Language): Similar to Claim 1, this claim describes an audio recognition system with a processing unit on a first integrated circuit that loads an audio recognition algorithm. On a second integrated circuit, there are "feature extraction means" (including a filter unit, filter controller, and block generator) for processing audio signals into feature extraction data, and "vector processor means" for performing vector operations during the algorithm's execution. The processing unit on the first integrated circuit receives the feature extraction data and uses it with the recognition algorithm.
• Claim 20 (Peripheral Apparatus Claim): This claim focuses on the audio recognition peripheral itself, implemented on a single integrated circuit. It includes a feature extractor (with an audio input, filter unit, filter controller, and block generator) to extract audio recognition features, a vector processor, and an interface controller. The interface controller receives external control signals and information that configure the vector processor to perform vector operations during the execution of an audio recognition algorithm by an external processor.
• Claim 37 (Peripheral Apparatus Claim with "Means-Plus-Function" Language): This claim describes an audio recognition peripheral on a single integrated circuit. It includes "feature extractor means" (with a filter unit, filter controller, and block generator) to process audio signals, "vector processor means" for vector operations, and "interface controller means." The interface controller means receives external control signals and information to configure both the feature extractor means and the vector processor means for vector operations during an audio recognition algorithm run by an external processor.
• Claim 43 (Method Claim): This claim outlines an audio recognition method involving a first integrated circuit (with a programmable processing unit) and a second integrated circuit (with a feature extractor, including a filter unit, filter controller, and block generator, and a vector processor). The method involves loading an algorithm on the first circuit, receiving an audio signal in the feature extractor of the second circuit, transmitting the resulting feature extraction data to the first circuit, where the algorithm is executed to produce a "first vector." This first vector, along with a "second vector," are transmitted to the vector processor on the second integrated circuit, which then performs a vector operation on them, generating a result. This result is then sent back to the programmable processing unit on the first integrated circuit for use in the ongoing audio recognition algorithm.
• Claim 50 (Method Claim - Incomplete in provided text): The provided patent text cuts off this claim. Based on the beginning, it describes a method of processing an audio signal on a single integrated circuit for audio recognition. It involves an interface controller receiving external control signals and interface information to configure a feature extractor (which includes a filter unit, filter controller, and block generator). It then details receiving an audio signal, extracting features, and transmitting the feature extraction data external to the integrated circuit. The full scope of the claim's method steps is not available.

CAFC Docket Information:
US Patent 6832194 was referenced in a U.S. Court of Appeals for the Federal Circuit (CAFC) decision on July 21, 2026. It was cited as a prior art reference ("Mozer") in a case involving Zentian Ltd. v. Apple, concerning U.S. Patent No. 10,839,789, which is titled "Speech recognition circuit and method." The dispute involved arguments about whether certain claims of Zentian's patent were obvious over combinations of prior art, including US 6832194. The CAFC vacated and remanded the Patent Trial and Appeal Board's (PTAB) decision in favor of Zentian Ltd., indicating errors in the PTAB's reading of the speech recognition patent claims, particularly regarding limitations like "acoustic model memory" and "single integrated circuit." The court also questioned whether the on-chip memory disclosed in prior art like Smyth and Mozer (US 6832194) would be sufficient for an abbreviated acoustic model. This indicates its use as a foundational prior art reference in the field of speech recognition integrated circuits.

As a patent attorney, I am providing information on known litigation involving US Patent 6832194 based on the provided search results.

Known Litigation Involving US Patent 6832194:

US Patent 6832194, referred to as "Mozer," was cited as a prior art reference in a U.S. Court of Appeals for the Federal Circuit (CAFC) case involving Zentian Ltd. v. [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.). While not the subject of an infringement claim itself in this specific litigation, its role as a prior art reference is significant.

• Plaintiff(s): Zentian Ltd.
• Defendant(s): Apple Inc.
• Jurisdiction: U.S. Court of Appeals for the Federal Circuit (CAFC)
• Case Number: 2024-2204 (also referenced as 24-2206 and 2024-2208 for related proceedings)
• Filing Date: Oral arguments were posted on June 4, 2026. A nonprecedential order was issued on February 14, 2025. The case opinion was issued on June 8, 2026.
• Outcome/Current Status: On July 21, 2026, the CAFC vacated and remanded a decision by the Patent Trial and Appeal Board (PTAB) that had favored Zentian Ltd.. The original PTAB decision found that claims of Zentian Ltd.'s U.S. Patent No. 10,839,789 (titled "Speech recognition circuit and method") were not shown to be unpatentable. Apple had argued that claims of Zentian's patent were obvious over prior art, including the combination of U.S. Patent No. 5,819,222 ("Smyth") and US Patent No. 6,832,194 ("Mozer"). The CAFC found that the PTAB made legal errors in construing the claims, particularly by requiring a "large-vocabulary model" for the "acoustic model memory" limitation and failing to address whether Mozer's disclosed 4,000-byte memory could hold an abbreviated digits recognizer model. The case was remanded for further proceedings.

Proceedings overview

There are no AIA (America Invents Act) trial proceedings found on file or surfaced via web search for US Patent 6832194. The patent has not been subjected to Inter Partes Review (IPR), Post-Grant Review (PGR), or Covered Business Method (CBM) review. This gives a defendant a neutral defensive posture regarding PTAB activity, as the patent claims remain untested in these forums.

Strategic summary

As of the current date, US Patent 6832194 has no claims canceled, sustained, or otherwise impacted by any AIA trial proceedings. All claims of the patent, including independent claims 1, 17, 20, 37, 43, and 50 (to the extent described), remain legally effective as granted, subject to the usual presumptions of validity. The absence of PTAB challenges means there is no estoppel landscape from AIA trials for this patent. The previously mentioned CAFC docket information refers to US6832194 ("Mozer") being cited as a prior art reference in a case involving a different patent (U.S. Patent No. 10,839,789, Zentian Ltd. v. Apple), not as a patent undergoing an AIA trial itself. Therefore, that case does not impact the validity of US6832194's claims through an IPR/PGR/CBM mechanism.

Recommended next steps

Since no PTAB activity exists for US Patent 6832194, its claims have not been challenged or affirmed in an AIA trial. If facing assertion of this patent, a defendant would have the full range of invalidity arguments available, including obviousness and anticipation, without the limitations of PTAB estoppel. A thorough prior art search would be the crucial first step to identify potential grounds for an IPR petition if such a defense is considered. The absence of past PTAB challenges is not necessarily an indication of strong validity, but rather that the patent has not yet been targeted in these specific proceedings.

Inventors

• Forrest S. Mozer (Sensory Inc) [cite: US6832194B1]
• Robert E. Savoie (Sensory Inc) [cite: US6832194B1]
• William T. Teasley (Sensory Inc) [cite: US6832194B1]

No unusual patterns are determinable from the provided information regarding the inventors' departure from the original assignee.

Original assignee

The original assignee is Sensory Inc. [cite: US6832194B1]. Sensory Inc.'s primary line of business appears to be integrated circuits for implementing audio recognition, including speech recognition systems. Sensory Inc. is currently operating.

Assignment timeline

• 2000-10-26 (executed) / recorded 2000-10-26 — Reel 011317/0115
  • Conveyance: Assignment
  • Assignor: MOZER, FORREST S.; SAVOIE, ROBERT E.; TEASLEY, WILLIAM T.
  • Assignee: SENSORY, INCORPORATED
  • Correspondent: SENSORY, INCORPORATED, C/O PATENTS ADMINISTRATION, 5670 EL CAMINO REAL, SUITE 200, CARLSBAD, CA 92008
  • Context: Original assignment from inventors to Sensory, Inc.

Timeline diagram

timeline
    title Ownership of US 6832194
    2000 : Assigned to SENSORY, INCORPORATED
    2004 : Issued

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The sole recorded assignment is from the inventors to the original operating company, Sensory, Inc.
2. Known asserter in the chain — not present. Sensory, Inc. is not identified as a known asserter on public NPE lists.
3. Repeat correspondent across the chain — not present. Only one assignment is recorded, so no recurrence can be observed. The correspondent is "SENSORY, INCORPORATED, C/O PATENTS ADMINISTRATION".
4. Cascading transfers — not present. Only one assignment is recorded.
5. Pre-litigation transfer — not present. There is no record of the patent being asserted in litigation within six months of any assignment.
6. Bankruptcy fire-sale — not present. No indication of Sensory, Inc. undergoing bankruptcy proceedings.
7. Privateering — not present. There is no evidence of a transfer to an NPE for assertion on behalf of an operating company.
8. Defensive aggregator (anti-NPE) — not present. The patent is not currently assigned to a known defensive aggregator.

Verdict

Insufficient data. Only the initial assignment from the inventors to the original operating company, Sensory, Inc., is recorded. There are no subsequent assignments that would indicate transfer to an NPE or a defensive aggregator.

Verification: https://assignmentcenter.uspto.gov/patent/index.html

To identify the most relevant prior art for US Patent 6832194, I will access the USPTO database for the patent and examine its cited references.

Here is the analysis of the prior art cited in US Patent 6832194:

USPTO Patent 6832194 Prior Art Analysis

The following prior art references were cited against US Patent 6832194. For each, I provide the full citation, publication/filing date, a brief description, and the claims it potentially anticipates under 35 U.S.C. § 102 (novelty).

I. US Patent Documents

• US 5,819,222

  • Full Citation: U.S. Patent No. 5,819,222 to Smyth, titled "Speech recognition system using an on-chip memory for storing an acoustic model".
  • Publication/Filing Date: The filing date for US 5,819,222 is October 23, 1996, and the issue date is October 6, 1998.
  • Brief Description: This patent describes a speech recognition system that incorporates an on-chip memory to store an acoustic model. The system aims to address the limitations of speech recognition systems, particularly regarding memory access and processing efficiency by integrating the acoustic model directly onto the chip. It involves a single integrated circuit containing both the acoustic model memory and a calculating apparatus (processor) that computes distances between feature vectors and states of the acoustic model.
  • Potentially Anticipated Claims: This patent is highly relevant as it describes an on-chip memory for acoustic models and processing within a single integrated circuit for speech recognition. This could potentially anticipate aspects of claims 20, 37, and portions of claims 1 and 17, which refer to components on a "single integrated circuit" and the execution of audio recognition algorithms. The CAFC decision explicitly discusses US 5,819,222 (Smyth) in relation to the "single integrated circuit" limitation and the sufficiency of on-chip memory for acoustic models in claims of US 10,839,789, implying its relevance to the "integrated circuit" aspects of US 6832194 as well.

• US 5,799,277

  • Full Citation: U.S. Patent No. 5,799,277 to Mozer, titled "Voice-controlled device with voice recording and playback".
  • Publication/Filing Date: The filing date for US 5,799,277 is November 8, 1996, and the issue date is August 25, 1998.
  • Brief Description: This patent details a voice-controlled device that includes functionalities for both voice recording and playback, suggesting a system capable of processing and reproducing audio signals, which might involve some form of feature extraction and synthesis.
  • Potentially Anticipated Claims: This patent, also by an inventor of US 6832194, broadly relates to voice processing. Depending on the specifics of its "voice recording and playback" functionality, it might be relevant to the synthesis aspects of US 6832194, particularly claim 27 and 28, which discuss extraction and synthesis modes and synthesizers.

• US 5,835,892

  • Full Citation: U.S. Patent No. 5,835,892 to Mozer, titled "Speaker-independent speech recognition system and method".
  • Publication/Filing Date: The filing date for US 5,835,892 is June 19, 1996, and the issue date is November 10, 1998.
  • Brief Description: This patent focuses on speaker-independent speech recognition, indicating a system that extracts features from speech and processes them for recognition, without being trained on a specific speaker's voice. This implies robust feature extraction and comparison mechanisms.
  • Potentially Anticipated Claims: This patent, again by an inventor of US 6832194, is directly relevant to the core functionality of speech recognition and feature extraction. It could potentially anticipate the general concepts of feature extraction and processing described in claims 1, 17, 20, 37, 43, and 50, specifically concerning the extraction of audio recognition features from an audio signal.

• US 5,913,000

  • Full Citation: U.S. Patent No. 5,913,000 to Mozer, titled "Word recognizer system".
  • Publication/Filing Date: The filing date for US 5,913,000 is June 19, 1996, and the issue date is June 15, 1999.
  • Brief Description: This patent describes a word recognizer system, which inherently involves the processing of audio signals to identify spoken words. This would typically include feature extraction and comparison against a vocabulary of words.
  • Potentially Anticipated Claims: Similar to US 5,835,892, this patent by Mozer directly relates to the application of audio recognition. It could potentially anticipate the methods and systems for feature extraction and recognition in claims 1, 17, 20, 37, 43, and 50.

• US 5,930,739

  • Full Citation: U.S. Patent No. 5,930,739 to Mozer, titled "Method and apparatus for real-time speech recognition".
  • Publication/Filing Date: The filing date for US 5,930,739 is October 24, 1996, and the issue date is July 27, 1999.
  • Brief Description: This patent focuses on real-time speech recognition methods and apparatuses, suggesting efficient and rapid processing of audio signals for recognition.
  • Potentially Anticipated Claims: This patent by Mozer, concerning real-time speech recognition, could anticipate the efficiency aspects of the audio recognition process outlined in US 6832194, particularly the offloading of computationally intensive tasks. It is relevant to the general methods and systems described in claims 1, 17, 20, 37, 43, and 50.

• US 5,995,922

  • Full Citation: U.S. Patent No. 5,995,922 to Mozer, titled "Voice-controlled device using a speech recognizer".
  • Publication/Filing Date: The filing date for US 5,995,922 is August 21, 1997, and the issue date is November 30, 1999.
  • Brief Description: This patent describes a voice-controlled device that explicitly uses a speech recognizer. This would involve taking audio input, processing it for speech features, and using these features to control the device.
  • Potentially Anticipated Claims: This is another patent by Mozer directly relevant to voice control and speech recognition, impacting the general claims (1, 17, 20, 37, 43, 50) that describe audio recognition systems and peripherals.

• US 6,104,821

  • Full Citation: U.S. Patent No. 6,104,821 to Mozer, titled "Audio recognition system and method".
  • Publication/Filing Date: The filing date for US 6,104,821 is March 31, 1999, and the issue date is August 15, 2000.
  • Brief Description: This patent broadly covers an "audio recognition system and method," indicating a general approach to identifying characteristics in audio signals.
  • Potentially Anticipated Claims: This patent by Mozer has a very similar title and broad scope to US 6832194, suggesting potential anticipation of almost all claims (1, 17, 20, 37, 43, 50) relating to the audio recognition system, peripheral, and method.

• US 6,243,679 B1

  • Full Citation: U.S. Patent No. 6,243,679 B1 to Mozer, titled "Speech recognition system having programmable noise gate".
  • Publication/Filing Date: The filing date for US 6,243,679 B1 is November 12, 1999, and the issue date is June 5, 2001.
  • Brief Description: This patent describes a speech recognition system that incorporates a programmable noise gate, which would be part of the audio input processing to improve recognition accuracy by filtering out unwanted noise. This is a specific enhancement to a feature extraction process.
  • Potentially Anticipated Claims: This patent by Mozer, describing a specific component (programmable noise gate) within a speech recognition system, could anticipate the details of the feature extractor and its configuration in claims such as 1, 17, 20, 37, 43, and 50, particularly regarding how the feature extractor receives and processes audio signals.

• US 6,317,707 B1

  • Full Citation: U.S. Patent No. 6,317,707 B1 to Mozer, titled "Digital speech recognition system having a general purpose processor and a speech recognizer".
  • Publication/Filing Date: The filing date for US 6,317,707 B1 is April 17, 2000, and the issue date is November 13, 2001.
  • Brief Description: This patent describes a digital speech recognition system that uses both a general-purpose processor and a dedicated speech recognizer. This directly relates to the concept of partitioning audio recognition tasks between a main processor and a specialized component, which is a central theme of US 6832194.
  • Potentially Anticipated Claims: This patent by Mozer is highly relevant to claims 1, 17, 43, and 50, as it explicitly outlines a system with a general-purpose processor and a separate speech recognizer, mirroring the two-integrated-circuit architecture and task partitioning described in US 6832194. It also anticipates the system where a programmable processing unit loads an audio recognition algorithm, and a second integrated circuit (speech recognizer) contributes to the audio recognition.

II. Other Cited Prior Art (Non-Patent Literature)

The patent US 6832194 does not explicitly list non-patent literature citations in the "Prior Art" section of the Google Patents record. However, the background and description sections implicitly reference existing methods for audio recognition, such as using a microprocessor to perform speech recognition with software algorithms or using application-specific integrated circuits (ASICs) with dedicated microprocessors. These are not specific, citable references but describe the general state of the art that the invention aims to improve upon. Therefore, a definitive list of non-patent literature to evaluate under 35 U.S.C. § 102 cannot be provided from the patent text alone.

Obviousness Analysis of US Patent 6832194 Under 35 U.S.C. § 103

This analysis assesses the obviousness of US Patent 6832194, "Audio recognition peripheral system," as of its priority date, October 26, 2000. A patent claim is obvious if "the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains" (35 U.S.C. § 103). The analysis will leverage the provided patent text, "Prior art keywords" from Google Patents, and information regarding U.S. Patent No. 5,819,222 ("Smyth"), a key prior art reference identified in the CAFC docket related to US6832194 ("Mozer"). The PHOSITA (person having ordinary skill in the art) in this field would be an engineer or developer experienced in designing and implementing audio or speech recognition systems, particularly involving integrated circuits and embedded systems.

Prior Art Landscape

Based on the provided information, the relevant prior art includes:

1. U.S. Patent No. 5,819,222 ("Smyth"): This patent, pertinent to speech recognition, discloses a processor (e.g., Motorola DSP56000) on an integrated circuit that includes acoustic model memory. The processor is capable of calculating distances between feature vectors and the states of an acoustic model. The memory on such a DSP was noted as potentially sufficient for an "abbreviated digits recognizer model". Given its patent number, it was published well before October 26, 2000.
2. U.S. Patent No. 4,718,094 ("Bahl et al."): Titled "Speech recognition system" and filed in 1984, this patent describes transforming acoustic waveforms into a string of labels (fenemes) by an acoustic processor, and then using probabilistic approaches for word recognition. It discusses acoustic matching and polling methodologies for determining word scores.
3. General Knowledge in Audio/Speech Recognition (circa 2000): As indicated by "Prior art keywords" (audio recognition, vector, audio, integrated circuit, peripheral), it was well-known that audio recognition systems required significant data processing, often implemented on integrated circuits. The concept of offloading computationally intensive tasks from a main processor to a specialized peripheral was a common architectural strategy in embedded systems design. Feature extraction was a fundamental preliminary step in audio recognition, and vector operations (e.g., distance calculations for template matching, multiply-accumulate for neural networks) were standard computations in various recognition algorithms.

Obviousness Analysis of Independent Claims

Claim 1: Audio recognition peripheral system (System Claim)

Claim 1 Elements:

• A first integrated circuit having a programmable processing unit loading an audio recognition algorithm.
• A second integrated circuit having:
  • a feature extractor (comprising a feature extractor filter unit coupled to receive an audio signal, a filter controller, and a block generator).
  • a vector processor coupled to the first integrated circuit.
• The second integrated circuit extracts audio recognition features from the audio signal to produce feature extraction data.
• The programmable processing unit receives the feature extraction data and executes the audio recognition algorithm.
• The vector processor performs a specified operation on a plurality of vectors during execution of the audio recognition algorithm.

Obviousness Argument:
Smyth discloses a speech recognition system with a processor (e.g., Motorola DSP56000) on an integrated circuit that calculates distances between feature vectors, implying an audio recognition algorithm and vector processing capabilities. Bahl et al. teach acoustic processors that extract features from audio signals (acoustic waveforms) to generate labels (fenemes) for speech recognition.

A PHOSITA would have been motivated to combine the elements of Smyth and Bahl et al. with the general knowledge of offloading computational tasks to a peripheral to improve system performance. Smyth's integrated circuit already included a processor and memory for speech recognition, capable of vector calculations. Bahl et al. describes the front-end feature extraction process. It would have been obvious to a PHOSITA seeking to optimize a speech recognition system (a known problem) to separate these functions across two integrated circuits, designating the main processor (first IC) to manage the overall algorithm flow and a specialized peripheral (second IC) to handle the computationally intensive feature extraction and vector operations.

The motivation to combine these elements to form a system as claimed in Claim 1 is rooted in predictable results. Known systems faced high processor loading. By dedicating a "feature extractor" (as described by Bahl et al.'s acoustic processor functions) and a "vector processor" (as exemplified by Smyth's processor calculating vector distances) to a second integrated circuit acting as a peripheral, the main programmable processing unit (first IC) could be freed for other tasks, leading to a more efficient and cost-effective system. This is a classic application of a known technique (peripheral offloading) to a known system (speech recognition) to yield predictable improvements in performance and resource utilization. The specific components of the feature extractor (filter unit, filter controller, block generator) are also known architectural elements for such tasks, and their arrangement as described in the claim would have been a matter of routine engineering design for a PHOSITA.

Claim 17: Audio recognition peripheral system (Means-Plus-Function)

Claim 17 Elements:

• On a first integrated circuit, processor means for loading an audio recognition algorithm.
• On a second integrated circuit:
  • feature extraction means for receiving an audio input signal and extracting audio recognition features, comprising a feature extractor filter unit coupled to receive the audio signal, a filter controller, and a block generator.
  • vector processor means for performing a vector operation during execution of the audio recognition algorithm.
• The processing means receives the feature extraction data and executes the audio recognition algorithm on the feature extraction data.

Obviousness Argument:
Claim 17, as a means-plus-function claim, covers the structures corresponding to the claimed functions. The "processor means" would be a programmable processing unit (e.g., microprocessor or microcontroller) [cite: US6832194B1]. The "feature extraction means" corresponds to the feature extractor described in the patent, including its filter unit, filter controller, and block generator. The "vector processor means" corresponds to the vector processor.

As discussed for Claim 1, Smyth discloses a processor on an integrated circuit capable of vector calculations for speech recognition. Bahl et al. describe acoustic processors performing feature extraction for speech recognition. A PHOSITA, aiming to optimize speech recognition systems, would find it obvious to distribute these known functionalities across two integrated circuits. The "processor means" on the first IC would manage the overall algorithm, while the "feature extraction means" and "vector processor means" on the second IC would handle the specialized, intensive tasks.

The motivation remains the same: to reduce the computational load on the main processor, a recognized problem in audio recognition systems. Implementing feature extraction logic (e.g., filter units and block generators) and a dedicated vector processor on a peripheral chip would have been a predictable solution for a PHOSITA. The "means-plus-function" language does not escape this obviousness because the corresponding structures are well-known or directly derivable from the prior art and general knowledge of system design.

Claim 20: Audio recognition peripheral (Apparatus Claim)

Claim 20 Elements:

• On a single integrated circuit, an audio recognition peripheral comprising:
  • a feature extractor (having an audio input, a feature extractor filter unit, a filter controller, and a block generator) for extracting audio recognition features.
  • a vector processor.
  • an interface controller coupled to the feature extractor and the vector processor.
• The interface controller has an interface input for receiving external control signals and interface information.
• The control signals and interface information configure the vector processor to perform a vector operation on a plurality of vectors during execution of an audio recognition algorithm on an external processor.

Obviousness Argument:
Claim 20 focuses on the peripheral chip itself. Smyth teaches an integrated circuit having a processor (capable of vector calculations) and on-chip memory for acoustic models. Bahl et al. teach acoustic processors that perform feature extraction. General knowledge confirms the existence of peripheral chips designed to offload specific tasks from a main processor, and such peripherals typically include an interface controller to communicate with the external processor.

A PHOSITA would have been motivated to integrate a feature extractor (as disclosed in Bahl et al.) and a vector processor (as present in Smyth's system) onto a single integrated circuit to create a specialized audio recognition peripheral. The "interface controller" for receiving external control signals and configuration information is a standard component for any peripheral designed to interact with a main processor, ensuring configurability and control. The goal of such an integration would be to provide a compact, efficient, and easily integratable component for adding audio recognition functionality to systems (as described in the background of US6832194).

The motivation to combine these known elements (feature extractor logic, vector processor, and interface controller) onto a single integrated circuit is based on the predictable benefits of integration: reduced cost, smaller footprint, and improved communication speed between tightly coupled components. This combination of known elements, each performing its known function, would yield the predictable result of a more efficient and self-contained audio recognition peripheral. Configuring a vector processor via an interface controller with external signals and information is also a standard practice for programmable hardware components.

Claim 37: Audio recognition peripheral (Means-Plus-Function)

Claim 37 Elements:

• On a single integrated circuit, an audio recognition peripheral comprising:
  • feature extractor means for extracting audio information, comprising a feature extractor filter unit, a filter controller, and a block generator.
  • vector processor means for performing a vector operation.
  • interface controller means for receiving external control signals and interface information, configuring the feature extractor means and the vector processor to perform a vector operation on a plurality of vectors during execution of an audio recognition algorithm on an external processor.

Obviousness Argument:
Similar to Claim 20, Claim 37 describes the peripheral in means-plus-function terms. The "feature extractor means" and "vector processor means" correspond to the feature extractor (with filter unit, filter controller, block generator) and vector processor, respectively. The "interface controller means" corresponds to the interface controller with decode logic [cite: US6832194B1, Fig. 5].

The same arguments for Claim 20 apply here. Smyth teaches a processor performing vector operations on an IC, and Bahl et al. teach feature extraction. General knowledge dictates that peripherals interacting with a main processor require an interface. Integrating these functions (feature extraction, vector processing, and interfacing) onto a single integrated circuit to form a dedicated audio recognition peripheral would have been an obvious design choice for a PHOSITA. The motivation to combine these elements on a single chip is the predictable advantages of integration (cost, size, performance) in a modular system. The functionality of configuring the vector processor via the interface controller is a known method for programming dedicated hardware through a bus.

Claim 43: Audio recognition method (Method Claim)

Claim 43 Elements:

• Loading an audio recognition algorithm in a first integrated circuit (programmable processing unit).
• Receiving an audio signal in a feature extractor on a second integrated circuit (comprising a feature extractor filter unit, a filter controller, and a block generator).
• Transmitting feature extraction data from the second IC to the first IC programmable processing unit.
• On the first IC, executing the audio recognition algorithm on the feature extraction data to produce a first vector.
• Transmitting the first vector from the first IC to a vector processor on the second IC.
• Transmitting a second vector to the vector processor.
• Performing a vector operation on at least the first and second vectors, generating a result.
• Transmitting the result to the programmable processing unit on the first IC for use in the audio recognition algorithm.

Obviousness Argument:
This method claim describes the interaction between the two integrated circuits. Bahl et al. describe the initial steps of an acoustic processor receiving an audio waveform and transforming it into labels (feature extraction data). Smyth describes a processor performing vector calculations (e.g., distance calculations between feature vectors and acoustic model states) within a speech recognition context on an integrated circuit. The concept of loading algorithms and transmitting data between a main processor and a peripheral is fundamental to computer architecture.

A PHOSITA would have been motivated to implement this method to distribute the computational load of a speech recognition algorithm, a known problem in the art. Given Smyth's disclosure of a processor on an IC performing vector calculations for speech recognition and Bahl et al.'s disclosure of feature extraction, it would have been obvious to a PHOSITA to devise a method where the main processor (first IC) orchestrates the overall algorithm, offloading initial data processing (feature extraction) and specific intensive calculations (vector operations) to a specialized peripheral (second IC).

The specific steps of transmitting feature extraction data, generating a first vector from the algorithm, sending it back to the peripheral's vector processor, combining it with a second vector, performing the operation, and returning the result are all standard data flow and processing patterns in distributed computing and embedded systems. This combination of known processing steps, distributed across a general-purpose processor and a specialized accelerator (the peripheral), would lead to the predictable improvement of overall system performance and efficiency. The "first vector" and "second vector" and their use in a vector operation are directly tied to the vector processing capabilities inherent in Smyth's system for calculating distances between feature vectors.

Claim 50: Method of processing an audio signal on a single integrated circuit (Method Claim - Incomplete)

Claim 50 Elements (as provided, incomplete):

• On a single integrated circuit, a method of processing an audio signal for audio recognition comprising:
  • Receiving external control signals and interface information in an interface controller corresponding to the external execution of an audio recognition algorithm, and in accordance therewith, configuring a feature extractor (comprising a feature extractor filter unit coupled to receive the audio signals, a filter controller, and a block generator).
  • Receiving said audio signal in the feature extractor.
  • Extracting audio recognition features from the audio signal to produce feature extraction data.
  • Transmitting the feature extraction data external to the integrated circuit.

Obviousness Argument:
This claim describes the operation of the peripheral chip itself, without the vector processor interaction, and focuses on feature extraction and external communication. Bahl et al. disclose acoustic processors that extract features from audio signals. General knowledge in embedded systems design dictates that any dedicated hardware module (like a feature extractor) intended for use as a peripheral would be configurable via an interface controller receiving external control signals and interface information. The feature extractor's components (filter unit, filter controller, block generator) represent known ways to implement feature extraction.

A PHOSITA would have been motivated to design a single integrated circuit peripheral that performs feature extraction and then transmits that data to an external processor. The motivation would be to offload the initial computationally intensive task of feature extraction from a main processor, providing a flexible and efficient component for audio recognition systems. The configuration via control signals and interface information is a standard method for controlling peripheral hardware. Transmitting the extracted data externally is the logical step for the peripheral to interact with the main processor running the recognition algorithm. This combination of known elements and steps would yield predictable results in terms of modularity and performance partitioning.

Conclusion on Obviousness

The independent claims of US6832194 (1, 17, 20, 37, 43, and 50) appear to be obvious over combinations of prior art, particularly U.S. Patent No. 5,819,222 (Smyth) and U.S. Patent No. 4,718,094 (Bahl et al.), combined with the general knowledge of a PHOSITA in the field of audio/speech recognition and integrated circuit design around 2000.

The core contribution of US6832194 is the partitioning of audio recognition tasks (feature extraction and vector processing) between a general-purpose programmable processor and a specialized peripheral integrated circuit. However, the underlying functionalities (feature extraction and vector processing) were known in the prior art (Bahl et al. for feature extraction, Smyth for vector calculations on an IC in speech recognition). The motivation to combine these known elements and distribute them across two integrated circuits, or integrate them into a single peripheral chip for offloading, would have been clear to a PHOSITA seeking to improve the efficiency, cost-effectiveness, and flexibility of audio recognition systems. Such architectural decisions to optimize performance and resource utilization by leveraging specialized hardware are well-established design principles. The combination of these known elements according to their known functions would yield predictable results.