US 6775784

I'll search for authoritative information on US 6775784, including any litigation or CAFC docket activity.

Let me run additional targeted searches for litigation and CAFC docket activity.

Let me do a final check for any litigation involving this specific patent and confirm the USPTO record.

US Patent 6,775,784 — Analyst Summary

Docket / litigation check (negative finding)

I searched for CAFC 2026 docket activity and USPTO/PTAB proceedings tied specifically to 6,775,784. I found no CAFC 2026 docket entry, PTAB proceeding, or district-court litigation involving this patent number. The result sets returned Samsung-related 2026 appeals (e.g., Samsung v. Fendgo, CAFC 2026-1088, IPR2024-00114; Samsung v. Ouraring, CAFC 26-1413, PGR2024-00039; CogniPower v. Samsung, CAFC 26-1559), but none of these involve 6,775,784 — they concern unrelated patent numbers, so I am not attributing them to this patent. Treat the absence of litigation as "not found in this search," not as an affirmative confirmation that none exists.

Bibliographic data (from the authoritative Google Patents text and cross-checked search results)

Abstract (as issued)

"In a computer system having a plurality of power management states, a power management control circuit includes a power management controller which manages power in accordance with the Advanced Configuration and Power Interface (ACPI) power management scheme, and includes a switching circuit that supplies a main power or a standby power to a system memory for the computer system according to a control of the power management controller. When a system state of the computer system is converted into the soft off state of the ACPI power management scheme, the power management controller cuts off power supplied to the system memory for the computer system. Therefore, it is possible to prevent unnecessary power consumption and damage to the system memory and to peripheral circuits when the system memory is removed or mounted from or upon a main board for the computer system."

Plain-language overview of the independent claims

Claim 1 — Power supply control circuit (three-element circuit). A circuit for a computer with normal / sleep / power-off states, comprising:

• a power supply that supplies main power and standby power;

• a power management controller powered by the standby power, controlling the power supply and outputting multiple system state display signals corresponding to the states; and

• a switching circuit that:

  • supplies main power to a volatile system memory when the state display signals are at the normal-state level and a power good signal is received from the power supply;
  • supplies standby power to the volatile system memory when the signals are at the sleep-state level; and
  • cuts off standby power to the volatile system memory when the signals are at the power-off level.

  The key inventive concept: unlike conventional ACPI S5 designs that leave standby power on the DRAM, this claim affirmatively cuts standby power to the memory in the soft-off/power-off state. Note the conjunctive "and when a power good signal is received" limitation for the normal-state branch.

Claim 10 — Power supply control circuit (controller + switching circuit, no separate power-supply element recited). Substantively parallel to claim 1 but framed without the "power supply" element: a power management controller that controls the power supply and outputs the state display signals, plus a switching circuit that supplies main power (normal state + power good signal), supplies standby power (sleep state), and cuts off standby power (power-off state) to the volatile system memory.

Claim 17 — Method of controlling a power supply. A method with four steps:

1. selectively controlling the power supply via a power management controller that outputs the state display signals;
2. providing main power to the volatile system memory via a switching circuit when the signals are at the normal-state level and a power good signal is received;
3. supplying standby power to the volatile system memory when the signals are at the sleep-state level; and
4. cutting off standby power to the volatile system memory when the signals are at the power-off-state level.

Dependent-claim structure (context for claim scope)

• Claims 2–9 depend from claim 1: claim 2 (context stored/held in volatile memory during sleep); claim 3 (first switch for standby power, second switch for main power, and a switch driver responsive to the state signals and power good signal); claim 4 (regulator adjusting standby power level, between power supply and first switch); claims 5–9 (switch-driver sub-details, regulator placement alternatives).
• Claims 11–16 depend from claim 10 (same themes: sleep-context storage; first/second switches plus switch driver; regulator; split first/second switch drivers).
• Claim 18 depends from claim 17: adjusting the standby power level via a regulator.

Specification mechanics worth flagging

• State-signal truth table (TABLE 1) as reported in the description: Normal state → S3# = 0, S5# = 0; S3 state → S3# = 0, S5# = 1; S5 state → S3# = 0, S5# = 0. (Note the potential internal inconsistency in the description text: the prose for the normal state says "the system state display signals S3# and S5# each have a low level," and the same 0/0 combination is used for S5, with distinction resting on PW_OK and the drivers.) I am reporting the table literally rather than resolving it.
• Hardware: regulator 51 (5V standby → 3.3V standby, P3.3V_SB), first switch 53 / FET51, second switch 57 / FET54, first switch driver 55 (FET52, FET53, R51, R52), second switch driver 59 (NAND logic 58, R53–R55, NPN Q51), capacitors C51–C54. Output to memory is "3.3V dual power P3.3V_DUAL."
• Cited prior art (29 references) include US 4,365,290 (Nelms), US 5,167,024 (Smith), US 5,239,652 (Seibert), US 5,384,721 (Joto), US 5,396,635 (Fung), US 5,483,464 (Song), US 5,590,342 (Marisetty), US 5,737,616 (Watanabe), US 5,796,992 (Reif), US 5,919,264 (Reneris), US 5,987,613 (Busch), US 6,016,548 (Nakamura), US 6,128,744 (Wang), plus non-patent citation: "Power Reduction for Active FET Inverters," IBM Technical Disclosure Bulletin, Nov. 1984, vol. 27, pp. 3461–3462.
• The fetched Google Patents page displays both a "Cited By (57)" table and a later "Cited By (96)" table; these two counts do not match each other. I flag this as a page-level discrepancy rather than asserting a single forward-citation count.

Uncertainty notes

• No authoritative litigation record located for 6,775,784 in CAFC 2026 dockets or PTAB proceedings from this search; absence of evidence, not evidence of absence.
• The forward-citation count is internally inconsistent (57 vs. 96) on the fetched page.
• Bibliographic fields are taken from the authoritative patent text provided; secondary aggregation sites (e.g., uspto.report, FreePatentsOnline) corroborated the number/title/assignee but added nothing material.
• Legal status ("Expired – Lifetime," adjusted expiration 2022-05-25) is the status shown by the source and is explicitly labeled there as an assumption, not a legal conclusion.

I'll research litigation involving US patent 6775784. Let me run several targeted searches.

Initial searches didn't surface litigation for this patent. Let me run more targeted queries.

No litigation has surfaced yet. Let me check several litigation-specific databases and free docket sources.

Litigation Search Report — U.S. Patent No. 6,775,784

Bottom line

I found no record of any litigation (district court, CAFC, ITC, or PTAB proceeding) involving U.S. Patent No. 6,775,784.

What I searched

I ran multiple targeted queries against publicly accessible sources, including:

• General litigation/patent databases and the Unified Patents portal caselist (portal.unifiedpatents.com/litigation/caselist) for the number "6775784" and "6,775,784"
• Free docket/opinion aggregators (CourtListener/RECAP, Docket Alarm, Justia-style results)
• CAFC opinion/order feeds for the patent number
• PTAB (IPR/PGR/reexam) references
• Terms combining the patent with litigation, infringement, complaint, plaintiff, defendant, and the named assignee (Samsung Electronics)

None of these returned a case in which U.S. Patent No. 6,775,784 was asserted, challenged, or otherwise in suit.

Caveats on the search (please read)

1. No litigation ≠ never litigated, only that nothing indexed surfaced. The queries returned no docket entry, complaint, or PTAB filing tied to this exact number. Free web indexing is incomplete, particularly for older or short-lived cases, sealed filings, and cases that settled before any opinion issued; PACER and paid databases (e.g., Docket Navigator, LexisNexis IP Litigation) would be needed to make a fully negative assertion.
2. Ordering of search returns was poor, and I hit a tool/step limit before I could exhaust additional sources. I recommend confirming with a PACER docket search and the Unified Patents litigation caselist directly.
3. Do not confuse this with look‑alike numbers that did appear in results and are unrelated:
   • 6,755,784 — a pharmaceutical/biologic patent appearing in drug-patent litigation (Celgene/Jazz/UnitedHealth matters). Different patent.
   • 6,765,788 — InterVideo, Inc. v. Dell Inc. (C.D. Cal., reported Aug. 2005). Different patent.

Useful context for the patent itself (not litigation)

• Patent: US 6,775,784 B1, "Power supply control circuit and method for cutting off unnecessary power to system memory in the power-off state."
• Application: US 09/694,311; filed 2000-10-24; granted 2004-08-10.
• Priority: KR 10-1999-0046418, filed 1999-10-25 (KR 100603926B1).
• Assignee: Samsung Electronics Co., Ltd. (inventor Seong-Geun Park).
• Legal status: Expired – Lifetime; Google Patents lists an adjusted expiration of 2022-05-25. Because the patent has expired, it is unlikely to be newly asserted going forward.
• Family: CN1163813C, TW475107B, KR100603926B1.
• Citation/bibliographic activity: cited by numerous later publications (57 "cited by" listings) and itself cites 29 references, but citation activity is not litigation.

Recommendation

To close this out definitively, verify with:

• PACER (Case Locator) for the patent number across all districts; and
• Unified Patents Litigation Caselist (https://portal.unifiedpatents.com/litigation/caselist) filtered by the patent number; and
• USPTO PTAB (Patent Trial and Appeal Board) and USPTO reexamination records for any post-grant challenge.

If those confirm no hits, the correct answer is: no known litigation involving U.S. Patent No. 6,775,784.

I'll verify against live sources before reporting.

The searches surfaced only unrelated patents. Let me run a few more targeted checks.

Proceedings overview

Total AIA trial proceedings on file for US 6,775,784: 0 — 0 active, 0 with claims invalidated, 0 with claims sustained, 0 settled, 0 institution-denied. The USPTO Open Data Portal returns no IPR, PGR, or CBM proceeding naming this patent, and my live web checks surfaced no petition, institution decision, Final Written Decision, or Federal Circuit appeal involving it. The bottom-line defensive posture is therefore not "hardened by surviving IPRs" and not "claims canceled" — it is simply untested at the PTAB, and no longer in force: the patent's adjusted expiration is 2022-05-25, so an assertion today can only reach past damages (subject to the 35 U.S.C. § 286 six-year lookback), and the practical defense is expiry/limitations plus ordinary district-court invalidity, not PTAB estoppel.

Because there are zero proceedings, the per-proceeding template is not populated. What follows is the negative-search record and the strategic read.

Negative-search record (no proceeding numbers exist to report)

• Structured source (canonical): the "PTAB proceedings on file" block supplied with this task states the ODP API returns no AIA trial proceedings for this patent as of the most recent ingest. I have not overridden that default.
• Live web checks performed 2026-10-01: searches on the patent number, patent title, inventor/assignee, and PTAB E2E/CourtListener style queries returned no PTAB or CAFC matter for US 6,775,784. One query returned an empty result set.
• Near-miss disambiguation — the following hits are different patents and must not be confused with this one:
  • IPR2022-00311 and IPR2022-00312 (Samsung/Dell v. MYPAQ Holdings, later styled with Samsung) involve U.S. 8,477,514 and U.S. 7,675,759 — power-converter patents owned by a different patent owner, not US 6,775,784. (petition materials)
  • IPR2025-00543 (Samsung v. Mobile Data Technologies LLC) involves U.S. 9,619,578 — the "'578 patent" shorthand in that record is not this patent. (petitioner filing)
  • Various other Samsung IPRs (IPR2023-01183, IPR2025-00789, IPR2025-00481, IPR2026-00017, etc.) concern unrelated third-party patents.
• Caveat: absence of an indexed proceeding is a strong but not mathematically conclusive signal; the ODP ingest lags and some very recent filings may not yet appear. I found no evidence of an unindexed filing, and I will not invent a proceeding number to fill the gap.

Strategic summary

Claim status — all claims untested, none canceled, none affirmed. US 6,775,784 issued 2004-08-10 with 18 claims across the Google Patents text: independent claim 1 (power supply control circuit with power supply, power management controller, and switching circuit), independent claim 10 (circuit recited from the controller/switching-circuit side), independent claim 17 (method of controlling a power supply), and dependent claims 2–9, 11–16, and 18 adding the sleep-state context retention, first/second switches, switch drivers, and the standby-power regulator. No PTAB tribunal has ever construed, canceled, or sustained any of claims 1–18. There is accordingly no "surviving claims" list to assemble — every claim stands as issued, but that is because it was never challenged, not because it was defended.

Estoppel landscape. With no IPR/PGR/CBM ever instituted, § 315(e)(2) estoppel is not in play for any party. A defendant is not limited to art "not reasonably raiseable" before the Board, because no Board proceeding exists — the full universe of § 102/§ 103/§ 112 grounds remains available in district court, including printed publications, system art, and on-sale/public-use theories. The only binding constraints are ordinary ones (claim preclusion if a prior judgment exists on the same patent; § 282 defenses must be pleaded with particulars under the local rules).

Pattern signals. None of the classic PTAB patterns appear: no repeat petitioner stacking multiple IPRs against this patent, no patent-owner appeal activity, and no defensive aggregator (Unified Patents or similar) filing on it. That is consistent with the patent's age and its 2022-05-25 expiration — it simply never became a high-value assertion target in the post-AIA era. Note the patent's family (KR100603926B1, CN1163813C, TW475107B) is likewise expired or lapsed, so the assertion surface is US-only and time-barred going forward.

Recommended next steps

1. Lead with expiry, not PTAB. There is no FWD to cite. Confirm the term calculation yourself against the USPTO Patent Center record for 09/694,311 (filed 2000-10-24, priority 1999-10-25, adjusted expiration 2022-05-25). If a demand letter cites US 6,775,784 today, the primary defenses are (a) the patent has expired and post-expiration conduct is non-infringing, and (b) any damages theory is capped by § 286's six-year lookback plus § 287 marking.
2. If an IPR/PGR/CBM was in fact just filed (i.e., an ODP ingest lag), the clock to watch is the § 314(b) three-month institution-decision deadline from the petition's filing/accor-dation date, then the § 316(a)(11) one-year statutory FWD deadline from institution. Any such proceeding is not yet reflected in the sources I can access, so treat it as unverified until you see the notice of filing on PTAB E2E.
3. Verify directly before relying on this memo. Pull the patent's PTAB E2E page and the ODP "proceedings" endpoint for US 6,775,784 at the time you file anything, and re-check CourtListener/CAFC for any appeal styled against Samsung Electronics Co., Ltd. involving this patent number. I could not access those databases for a final confirmation within this session, so the "no PTAB activity" conclusion rests on the canonical structured block plus the negative web searches documented above.
4. Preserve invalidity proof anyway. Because no estoppel attaches and the claims were never tested, a district-court § 102/§ 103 challenge is live if the patent is somehow asserted within the damages window — the 29 references cited on the face of the patent (including Nelms US 4,365,290; Smith US 5,167,024; Fung US 5,396,635; Watanabe US 5,737,616; Reneris US 5,919,264; and the "Power Reduction for Active FET Inverters," IBM TDB, Nov. 1984) are the natural starting art set.

Bottom line: no PTAB activity on file for US 6,775,784, and none expected given its 2022-05-25 expiration. There is no FWD to link to and no disposition to quote. If you are a defendant, your leverage is the expired term and § 286 limitations, not an IPR record — and if someone hands you a docket showing a live PTAB case on this number, flag it immediately, because it would contradict every source checked here.

I'll research the assignment record for US 6775784 across the sources specified. Let me start with several targeted searches.

Let me dig deeper into assignment records, litigation history, and the Korean priority/family.

US 6775784 B1 — Ownership & Assignment Reconstruction

Patent: Power supply control circuit and method for cutting off unnecessary power to system memory in the power-off state
Patent no.: US 6,775,784 B1 · Appl. no.: US 09/694,311 · Filed: 2000-10-24 · Granted: 2004-08-10
Priority: KR 10-1999-0046418 (1999-10-25)

Source-access note: The USPTO Assignment Center / assignment.uspto.gov search interface did not return a machine-readable record set in this session, and no litigation docket surfaced for this patent. The assignment facts below are grounded in the Google Patents legal‑events ("Reassignment") block for US6775784B1, which is a mirror of the underlying USPTO assignment records. Where a reel/frame number or recorded correspondent was not exposed by that mirror, I say so explicitly rather than guess.

Inventors

• Only one inventor is named. No co‑inventor departures, no "all‑inventors‑left‑within‑12‑months" pattern is observable from the record.
• The application claims priority to a Korean filing (KR 10‑1999‑0046418) made by the same inventor while at Samsung — a standard corporate priority filing, not a signal of pending inventor exit.

Original assignee

• Samsung Electronics Co., Ltd. (Suwon‑city, KR) — named assignee on the grant and the original assignee of record.
• Line of business: Consumer/enterprise electronics and semiconductor manufacturing; the claimed subject matter (ATX/ACPI power‑rail switching for a system memory in the S5 soft‑off state) is a mainstream PC‑motherboard/power‑management feature that Samsung implemented in its own computer products. This is an operating company with shipped products embodying the technology class.
• Current status: Operating (publicly traded, no bankruptcy/insolvency event applicable to this chain). The record carries no assignment away from Samsung.
• Family: KR100603926B1, CN1163813C, TW475107B — all national counterparts of the same Samsung family, none showing a recorded divestiture to a non‑practicing entity in the material reviewed.

Assignment timeline

Chronological list of every recorded assignment that could be located:

• 2000-10-24 (executed) / recorded on/around 2000-10-24 — Reel/frame not exposed in the fetched record
  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS INTEREST)
  • Assignor: PARK, Seong‑Geun (sole inventor)
  • Assignee: SAMSUNG ELECTRONICS CO., LTD.
  • Correspondent: Not exposed in the fetched legal‑events mirror. (Samsung's in‑house/Korean prosecution practice — no recorded outside recording agent captured.)
  • Context: Original inventor‑to‑corporate assignment at filing; standard corporate ownership vesting. No funneling or reassignment follows.

No post‑issuance assignments are recorded for US6775784. The Google Patents legal‑events timeline shows exactly one reassignment event (the original grant of rights to Samsung) and no subsequent transfer, change of name, security interest, merger, or license record. There is no shell‑entity transfer, no cascade, and no defensive‑aggregator termination in the chain. Per the task framing, the absence of post‑issuance assignment records is itself the finding: Samsung Electronics still owned the patent at expiry.

Timeline diagram

timeline
    title Ownership of US 6775784
    1999 : Korean priority filed by Park
    2000 : US application filed
         : Assigned to Samsung Electronics
    2004 : Patent granted
    2022 : Patent expired

NPE / troll-pattern signals

1. Shell-entity transfer — not present. No assignment from Samsung to any "IP/Patents/Licensing/Holdings/Ventures" entity appears anywhere in the record. The only assignee is the operating company Samsung Electronics.

2. Known asserter in the chain — not present. No assignee in the chain matches Acacia, Marathon, IV, IPNav, Wi‑LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, or any other listed/sponsored asserter. The chain contains only Park → Samsung.

3. Repeat correspondent across the chain — not present / not assessable. Only one assignment exists, so there is no "across the chain" recurrence to evaluate; the recording correspondent was not exposed by the fetched record. No basis to flag.

4. Cascading transfers — not present. Zero consecutive transfers; none within 24 months or otherwise.

5. Pre-litigation transfer — not present. No assignment within 6 months before any infringement suit, because no infringement suit naming this patent was found in the searches performed, and no transfer exists to date.

6. Bankruptcy fire-sale — not present. Samsung Electronics has no Chapter 7/11 event divesting this patent; the record shows no sale in proceedings.

7. Privateering — not present. No operating‑company‑to‑NPE transfer; no SEC 8‑K/10‑K or third‑party coverage surfaced indicating assertion on Samsung's behalf through a proxy.

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at RPX, AST, LOT, Unified, or OIN; it never left Samsung.

Verdict

Insufficient data — specifically, only the original assignment exists.

Grounding: the sole recorded assignment is the 2000‑10‑24 inventor‑to‑corporate grant from Seong‑Geun Park to Samsung Electronics Co., Ltd. (the event listed in the Google Patents legal‑events block for US6775784B1), with no subsequent recorded transfer, correspondent recurrence, litigation, or fire‑sale in the material reviewed. Because the record never moved beyond the original operating‑company owner (and the patent expired 2022‑05‑25), there is no NPE activity to characterize — the chain is a clean single‑link corporate ownership record, not an assertion vehicle.

Verification link: https://assignmentcenter.uspto.gov/ — search patent number 6775784 (mirror: https://patents.google.com/patent/US6775784B1/en, "Reassignment"/legal‑events section).

Confidence caveats: (a) I could not pull a raw reel/frame or correspondents‑of‑record from the Assignment Center in this session, so if a late‑breaking assignment or a license record was filed after the source snapshot, it would not be reflected here; the mirror shows none. (b) "Not present" for litigation signals means no suit was surfaced in the searches run — it is not an affirmative clearance of all federal dockets.

I'll research US Patent 6775784 and its cited prior art. Let me start with searches to confirm the patent details and its citation record.

I've confirmed US 6775784 and its citation record. Let me now research the most relevant cited references to assess their §102 potential.

Prior-Art Analysis — US Patent 6775784 B1

1. Patent Under Review (confirmed)

Independent claims (the anticipation targets): claim 1 (power supply + power management controller + switching circuit that supplies main power in normal state, standby power in sleep state, and cuts off standby power to the volatile system memory in the power-off state); claim 10 (same, controller + switching circuit); claim 17 (method). Dependent claims 2–9, 11–16, 18 add: system context held in memory during sleep (2, 11), first/second switches + switch driver (3, 12), regulator for standby power (4, 7, 9, 13, 16), and separate first/second switch drivers (5, 8, 14, 15, 18).

2. §102 Framing and Method

• Anticipation under 35 U.S.C. §102 requires a single reference disclosing every element of a claim, arranged as claimed. References cited on the face of a patent are frequently "background" or §103 (obviousness) art, not anticipatory art.
• The critical date for the specification is the 1999-10-25 KR priority. Most cited references published well before 1999-10-25 qualify under §102(b); three references published only after the filing date qualify only as §102(e) art (based on their pre-1999-10-25 U.S. filing/priority): US 6389556 B1, US 6360327 B1, and US 6523128 B1.
• Caveat: I examined the full text of US 6775784 and the citation list, plus public summaries of the cited references. This is a preliminary §102 screen, not a claim-chart examination of every reference's full specification.

Overall §102 conclusion up front: No single cited reference appears to anticipate any of independent claims 1, 10, or 17. Each cited reference lacks at least one of the distinguishing elements — (a) the plurality of ACPI system-state display signals (S3#/S5#), (b) the dual-switch arrangement (first switch = regulated standby power path, second switch = main power path into the volatile memory), and (c) cutting off the standby power to the system memory specifically in the S5/soft-off state while retaining standby power in S3. The cited references are best characterized as §103 art or as art relevant only to narrower dependent claims. Details per reference follow.

3. Citation-by-Citation Analysis (all 29 U.S./foreign patent citations + 1 NPL)

Tier A — Closest art to the "standby power to memory in sleep/off" concept

US 6523128 B1 — Stapleton et al., "Controlling power for a sleeping state of a computer to prevent overloading of the stand-by power rails by selectively asserting a control signal," Intel Corporation.

• Priority 1999-08-31; published 2003-02-18. §102(e) art.
• Description: asserts a control signal to selectively manage the stand-by power rails during a sleeping state, avoiding rail overloads. Highly relevant to selective standby-power control in sleep.
• §102 potential: Closest reference to claims 1/10/17 on the "standby power in sleep" element, but it targets overloading of standby rails — it does not disclose cutting off standby power to the system memory in the power-off/soft-off (S5) state nor the dual main/standby switch into memory. Not a full anticipation; strongest §103 reference.

US 6266776 B1 — Sakai, "ACPI sleep control," Kabushiki Kaisha Toshiba.

• Priority 1997-11-28 (JP 9-329210); U.S. filing 1998-11-25; published 2001-07-24. §102(e)/§102(b)-era art.
• Description: ACPI S0–S5 framework; dynamically transitions between sleep states based on detected power-supply/battery changes while maintaining system memory power in S3.
• §102 potential: relevant to the S3 vs. S5 state definitions and to claim 2/11 (context held in memory during S3). It does not disclose the claimed switching circuit that cuts off memory standby power in S5. Not anticipatory of 1/10/17.

US 6128747 A — "System for delaying propagation of wake-up signal to processor through the sleep control means until the memory is awakened," Hewlett Packard Company.

• Priority 1997-01-28; published 2000-10-03. §102(b)-era.
• Description: sequences memory power-up before waking the processor during a sleep-state exit.
• §102 potential: relevant to memory power management across sleep states; not anticipatory (no S5 memory-power cutoff; no dual-path switch).

US 6389556 B1 — "Mechanism to prevent data loss in case of a power failure while a PC is in suspend to RAM state," Advanced Micro Devices, Inc.

• Priority 1999-01-21; published 2002-05-14. §102(e) art.
• Description: in suspend-to-RAM (S3), saves system state to system memory and an image to non-volatile memory; on wake, checks for memory corruption from power loss. Claims recite "system memory being supplied power in the reduced power state."
• §102 potential: relevant to claim 2/11 (state/context stored and held in system memory during sleep) and to the memory-power-in-sleep concept. Not anticipatory of 1/10/17 (no S5 cutoff, no claimed switching circuit/display signals).

US 5796992 A — "Circuit for switching between synchronous and asynchronous memory refresh cycles in low power mode," Compaq Computer Corporation.

• Priority 1995-12-20; published 1998-08-18. §102(b) art.
• Description: four power modes (RUN/SLEEP/IDLE/STANDBY) with memory refresh control to retain memory contents at low power.
• §102 potential: touches claim 2/11 (retaining memory context in a low-power state); not anticipatory of the independent claims.

US 6058039 A — "Memory package and hot-line insertion/removal method using time constant based on-off switching," Hitachi, Ltd.

• Priority 1995-01-11; published 2000-05-02. §102(b)-era.
• Description: enables hot-line insertion/removal of a memory package using time-constant-based on/off switching.
• §102 potential: directly relevant to the problem/motivation of the patent (removing/mounting system memory safely), and to the switch element; but it does not disclose the ACPI S3/S5 standby-power-cutoff control. Not anticipatory of 1/10/17; background/motivation art.

Tier B — Power-supply/switch control circuits (relevant to claim 3/12 switch elements)

US 5737616 A — Watanabe, "Power supply circuit with power saving capability," NEC Corporation.

• Priority 1995-05-15; published 1998-04-07. §102(b).
• Description: CPU status register signals a peripheral power-supply control block that changes power/clock statuses of a peripheral circuit/device in coordination with the CPU supply mode.
• §102 potential: closest to the coordinated controller + power-control-block architecture of claim 1, but no ACPI state signals and no memory standby-power cutoff in S5. §103 art; not anticipatory.

US 5414861 A — "Data protection system using different levels of reserve power to maintain data in volatile memories for any period of time," Fujitsu Limited.

• Priority 1991-09-11; published 1995-05-09. §102(b).
• Description: switch circuit selectively routes main/reserve power to a volatile memory array across power-loss sequences.
• §102 potential: relevant to claim 3/12's switch selectively routing main vs. reserve power to volatile memory; but the selection is driven by power-failure detection, not ACPI S3#/S5# display signals. Not anticipatory of 1/10/17.

US 6098174 A — "Power control circuitry for use in a computer system and systems using the same," Cirrus Logic, Inc.

• Priority 1998-08-03; published 2000-08-01. §102(b)-era.
• Description: power control circuitry for computer systems.
• §102 potential: general switch/control circuitry art; no teaching of the claimed S5 memory-standby cutoff. Not anticipatory.

US 6128744 A — "Computer starter and starting method for an ATX computer system," Winbond Electronics Corp.

• Priority 1998-10-29; published 2000-10-03. §102(b)-era.
• Description: ATX-system starter using standby voltage, smart-card interface, microcontroller, and a power control circuit.
• §102 potential: relevant to ATX standby-power handling (the patent's stated environment); not anticipatory of the memory-cutoff switching circuit.

US 5919264 A — "System and method for using data structures to share a plurality of power resources among a plurality of devices," Microsoft Corporation.

• Priority 1997-03-03; published 1999-07-06. §102(b)-era.
• Description: power-management data structures defining which power resources must be on/off for a device/system state (expressly incorporated by reference in US 6775784's background).
• §102 potential: relevant to the ACPI state/power-resource abstraction; it is software/data-structure art and does not disclose the claimed hardware switching circuit. Not anticipatory.

US 6260151 B1 — "Computer system capable of controlling the power supplied to specific modules," Kabushiki Kaisha Toshiba.

• Priority 1997-03-14; published 2001-07-10. §102(e)-era.
• Description: selective power control to specific modules.
• §102 potential: general selective-module-power art; not anticipatory.

Tier C — General power-management / sleep-state art (background; not anticipatory)

Non-Patent Citation

"Power Reduction for Active FET Inverters," IBM Technical Disclosure Bulletin, Nov. 1984, vol. 27, pp. 3461–3462.

• Dated Nov. 1984 (well before the 1999-10-25 priority). §102(b) art.
• Description: power-reduction techniques for active field-effect-transistor inverters.
• §102 potential: relevant only to the FET implementation of the first/second switches (claims 3, 12); not a circuit/system-level anticipation of claims 1/10/17.

4. Ranking — Most Relevant Cited Prior Art

1. US 6523128 B1 (Intel) — selective standby-rail power control in a sleeping state (§102(e)). Closest single reference to the "standby power in sleep" element.
2. US 6266776 B1 (Toshiba, "ACPI sleep control") — full ACPI S0–S5 sleep-state framework and transitions; strongest on the S3 vs. S5 distinction.
3. US 6389556 B1 (AMD) — suspend-to-RAM state retention with memory powered in the reduced-power state.
4. US 6128747 A (HP) — memory-power sequencing across sleep/wake.
5. US 5796992 A (Compaq) — low-power memory modes retaining contents.
6. US 6058039 A (Hitachi) — memory hot-line insertion/removal (matches the patent's stated motivation).
7. US 5737616 A (NEC) — coordinated controller + power-control-block architecture.

5. §102 Anticipation Conclusions

• Independent claims 1, 10, and 17: No cited reference anticipates. Each lacks the combination of (i) ACPI system-state display signals S3# and S5#, (ii) the dual-switch switching circuit coupling a regulated standby rail and a main rail into the volatile system memory, and (iii) cut-off of standby power to the system memory in the S5/soft-off state while retaining standby power in S3.
• Claims 2 / 11 (context held in memory during sleep): Potentially met in isolation by US 6389556 B1, US 6266776 B1, and/or US 5796992 A — but these cannot anticipate because they do not meet their independent claim, and (for 2/11) a dependent claim is anticipated only if the reference also shows the parent claim's elements.
• Claims 4/7/9/13/16 (regulator for the standby level): Only general support in US 5737616 A / US 5414861 A; not anticipatory.
• Claims 3/12/5/8/14/15/18 (first/second switches and switch drivers): Only partial support (US 5414861 A switch routing; US 6058039 A switching; IBM TDB for FETs); not anticipatory.
• Net effect: The cited set is §103 (obviousness) / background art, consistent with the patent having issued with 18 claims. On the record I can see, the claimed S5-specific memory standby-power cutoff was not shown in a single cited reference.

6. Explicit Uncertainties

• I did not retrieve the complete specification and claim sets for every one of the 29 cited references; my descriptions for the Tier C references rely on titles/summaries, so per-reference §102 characterizations there are provisional.
• Publication/filing dates above are taken from the US 6775784 citation listing (Google Patents), which labels the earliest date as "Priority date"; where a reference's actual U.S. filing date differs from its priority date, the §102(e)/§102(b) category could shift.
• A full anticipation opinion would require element-by-element claim charts against the primary references (US 6523128 B1, US 6266776 B1, US 6389556 B1), which I have flagged as the references to obtain in full.

I'll verify the key prior-art references before building the § 103 analysis.

Let me verify a few more of the cited references that are closest in time and subject matter.

Obviousness Analysis — U.S. Pat. No. 6,775,784 B1

Patent: U.S. 6,775,784 B1, "Power supply control circuit and method for cutting off unnecessary power to system memory in the power-off state"
Inventor: Seong-Geun Park · Assignee: Samsung Electronics Co., Ltd.
Priority: Oct. 25, 1999 (KR 99-46418) · Filed: Oct. 24, 2000 · Granted: Aug. 10, 2004 · Adjusted expiration: May 25, 2022 (Expired – Lifetime)

Framing notes

• Because the application was filed before March 16, 2013, the governing provision is pre‑AIA 35 U.S.C. § 103(a). References qualify as prior art under § 102(a)/(b)/(e) as of their own dates, and any reference with an effective date after Oct. 25, 1999 must be screened for § 102(e) availability.
• The patent has expired, so this is a retrospective/hypothetical validity analysis of historical and technical interest, not a live invalidity contention. It is not legal advice.
• Per the operating rules I have not auto-corrected any number. Where I could not verify a reference's content directly I say so explicitly.

1. The claim set in outline

The acknowledged point of novelty is narrow: the prior art already taught (i) ACPI S0–S5 management, (ii) switchable power gating of subsystems, (iii) ATX main/standby rails, and (iv) standby-powered DRAM in suspend-to-RAM. The asserted contribution is the additional cut-off of the standby rail to system memory specifically in S5/soft-off, gated by the ACPI state-display signals and PW_OK.

2. Reference inventory (from the "Prior Art" section of the page) and element mapping

Caveat: I was cut off before verifying US 6,389,556, US 5,737,616, and US 6,098,174 live; the characterizations above for those three rest on the page's own abstracts/descriptions plus my training knowledge, and I have flagged them accordingly. I did not auto-correct any identifiers.

3. Element-by-element coverage of independent claim 1

No single reference on this page appears to disclose all of claim 1. Reneris is software/OS-level and does not show the hardware switch array; Sakai lacks the explicit main-vs-standby rail arbitration to memory; Wang has the rails but not the state-gated memory cut-off. Obviousness, not anticipation, is therefore the realistic invalidity theory — which is what the examiner's allowance suggests.

4. Principal § 103 combination

Combination A — Reneris '264 + Sakai '776 + Wang '744 + Smith '024 (optionally + Intel '528)

Claim 1 / 10 / 17. Reneris supplies the ACPI multi-state control paradigm and the express concept that a given system state dictates which power resources must be OFF. Sakai supplies an embedded controller that, on state transitions, "stops power supply to unnecessary portions" — i.e., a controller that actively removes power from units as the system descends toward S5. Wang supplies the ATX environment with a main rail and a 5VSB standby rail that persists when the machine is off, plus an always-on power control circuit. Smith supplies the concrete mechanism — transistor switches under the power manager's control that gate power to individual units — which is exactly the "switching circuit" of claim 3 (first switch = standby, second switch = main, driver). Gating on the ATX PW_OK signal is a documented ATX handshake.

Motivation to combine (KSR/art-recognized rationales):

1. Same field, same problem: all four address reducing PC power consumption across operational states.
2. Art-recognized technique: gating the supply to a subsystem according to a state signal was routine (Smith; Fung; Watanabe).
3. Design need / predictable result: because the ATX supply already maintains 5VSB in the off state (Wang), and the ACPI S5 state is defined as consuming minimal power with no context saved (ACPI spec in the patent), a skilled artisan had a clear reason to stop feeding memory in S5 — there is nothing to preserve, so the draw is pure waste. This is a "finite number of identified, predictable solutions" situation (KSR Int'l v. Teleflex).
4. Additional design need unique to this art: the specification itself recites that in S5 "a user cannot replace the system memory … because the standby power is still supplied," creating a safety/serviceability rationale to kill the rail. Hitachi '039 (hot-line insertion/removal) supplies the art's recognition that live rails complicate memory removal — supporting a motivation to de-energize memory in what is functionally a power-off state.

Combination B — Fung '635 + Wang '744 + Watanabe '616 + Intel '528

Fung supplies the ON/DOZE/SLEEP/OFF state machine and "activity monitor … generating control signals for selecting one of the states," Wang the ATX main/standby rails and standby-powered control logic, Watanabe the status-signal→power-supply-control-block architecture, and Intel '528 the specific idea of selectively asserting a control signal to manage the stand-by rail during a sleeping state. Adding a memory-side gate that is on in SLEEP and off in OFF follows directly from Fung's own four-state hierarchy, where OFF is expressly the lowest-power state.

Combination C — Reneris '264 + Smith '024 + Wang '744 + ATX spec (claims 3, 5, 8)

For the dependent switch architecture (claim 3, 5, 8), Smith's "transistor switches controlled by the power manager control the distribution of power" supplies the first/second switches and switch driver; providing two separate drivers (claim 5/8) is a routine partitioning choice with no unexpected result — the two switches are controlled by different enable conditions (main in normal + PW_OK; standby in sleep), so a skilled artisan would naturally give each its own driver to avoid cross-coupling, and indeed the patent's own drivers are independent.

Combination D — any of A/B/C + a regulator reference (claims 4, 6, 7, 9, 13, 16, 18)

Claims 4/6/7/9/13/16/18 add only a regulator between the standby rail and the first switch to adjust the standby level (5VSB → 3.3V). This is the patent's own express design and is dictated by the ATX/industry rails (Wang: 5VSB), where stepping 5V down to a memory rail voltage is elementary. If a reference is desired beyond the ATX/industry knowledge, US 5,737,616 and US 5,796,992 both operate in this voltage/state-conversion environment. No non-obvious weight attaches to this limitation.

Combination E — Watanabe '616 or Nelms '290 as an alternative "status signal → switch" primary

Watanabe is arguably the closest single teaching for the control concept of independent claims 1/10: a status register/status signal causes a power supply control block to change power supply statuses of a downstream block. Combined with the ACPI-state framework of Reneris/Sakai and the ATX rails of Wang, it yields the claimed signal-driven rail arbitration without the OS-level abstraction of Reneris.

5. Dependent claims 2 and 11 (context held in memory during sleep)

These add nothing patentably distinct. Retaining context in DRAM during a low-latency sleeping state is the definition of the ACPI S3/"suspend-to-RAM" state, which is described in the patent's own background as known art and appears in the cited ACPI Specification Rev. 1.0 (Dec. 22, 1996) and in AMD '556 (protecting DRAM contents during suspend-to-RAM). A limitation that merely describes the pre-existing premise of the environment (why memory needs power in S3) cannot confer patentability.

6. Motivation-to-combine summary (for an obviousness narrative)

• Common problem / common field: every reference cited is in computer power management (see the page's own section headings and CPC class G06F1/26, G06F1/32).
• Reasonable expectation of success: combining a state-signal decoder (Reneris/Watanabe), a standby rail (Wang), and transistor power gating (Smith) is a mechanical aggregation of known circuit blocks with predictable results; the assignee's own patent reduces it to two FET switches, two drivers, and a regulator.
• "Finite number of identified, predictable solutions": given ACPI expressly defines S5 as soft-off with no saved context, the option space for handling the memory rail in S5 reduces to "leave it powered (known, wasteful, and blocks memory service)" or "cut it." The patent chooses the latter.
• Teaching away absent: none of the references teaches that memory must remain on standby in the off state; on the contrary, Intel '528 and Sakai '776 move in the direction of selectively removing standby power.
• Design-incentive/other-motivation: safety and serviceability of the memory when removed/mounted from the main board (the patent's own stated objects), reinforced by the hot-insertion art (Hitachi '039).

7. Considerations cutting the other way (diligence for a complete opinion)

1. The examiner allowed the claims, which is some evidence the combination was not viewed as reasonably clear at the time, and the cited art was fully of record (29 references, including Intel '528 and AMD '556).
2. Timing of the closest references: Intel '528 (priority 1999‑08‑31) and AMD '556 (1999‑01‑21) are close to, but before, the Oct. 25, 1999 priority date. Their precise § 102(e) availability and disclosure scope would need claim-chart verification of their full texts (which I flagged as unverified).
3. Claim construction matters: the phrases "each system state display signal … at a level corresponding to the normal/sleep/power-off state" and "when a power good signal is received" are written in the alternative/negative, which can narrow the effective combination to those references that gate on all state signals and PW_OK. Whether the prior art meets these is a fact question per reference.
4. Secondary considerations: the patent is expired; I found no objective evidence of unexpected results, long-felt need, industry praise, or copying in the record available here. Absent such evidence, the prima facie combination is unrebutted.

8. Bottom line

• Likely obvious under § 103(a) over Reneris '264 + Sakai '776 + Wang '744 + Smith '024 (optionally reinforced by Intel '528), with dependent claims 4/6/7/9/13/16/18 rendered obvious by the routine use of a regulator on the 5VSB rail, claims 5/8/14/15 by routine driver partitioning, and claims 2/11 by the definition of ACPI S3/suspend-to-RAM.
• Alternative viable combinations: (B) Fung '635 + Wang '744 + Watanabe '616 + Intel '528, and (C) Watanabe '616 + Reneris '264 + Wang '744.
• The patent's asserted advance — cutting the standby rail to volatile system memory in S5 while keeping it in S3 — reads as an incremental, predictable application of known state-signal-controlled power gating in the ATX/ACPI environment, which is the classic KSR fact pattern.

Caveats: This analysis relies on the "Prior Art" listing and text of the provided page plus the searches I could complete; I could not independently verify the full disclosures of US 6,389,556, US 5,737,616, and US 6,098,174 before my tool budget ended, and I have flagged those characterizations. Verify each reference's full text and effective prior-art date before relying on this analysis.