US 6556157

I'll search for authoritative information on US 6,556,157, including any litigation activity.

US Patent 6,556,157 — Summary

Searches performed: USPTO/Google Patents, FreePatentsOnline, Justia Patents, and a CAFC 2026 docket sweep. The patent text below is grounded in the authoritative Google Patents record (https://patents.google.com/patent/US6556157/en), which was fetched 2026-09-24. No CAFC 2026 docket or district-court case referencing patent number 6,556,157 appeared in my searches — see the litigation note at the end. I did not auto-correct or substitute any number; a separately surfaced Japanese publication "JP 6556157 B2" is a different patent (a turbofan engine fan rotor, Safran Aircraft Engines) and is not related to this US patent.

Bibliographic data (as listed)

Abstract (verbatim substance)

Disclosed is a data converter and a method for converting a digital audio stream representing an analog signal sampled at a certain rate. A divider receives a clock signal associated with the stream and divides it by a selectable division factor set by divider control signals, producing an internal clock signal. A frequency detection circuit receives the divider output and detects the original sampling rate based upon intrinsic characteristics (e.g., MCLK-to-LRCK ratio) of the stream. The frequency detection circuit (which may work with a separate rate detection circuit) generates the divider control signals so the internal clock has a known relationship to the original sampling rate by sampling mode. A digital processing circuit then receives the internal clock, derives incoming data from the stream, and generates an output signal.

Plain-language overview of the independent claims

There are four independent claims: 1, 23, 26 (method), and 38 (ADC).

• Claim 1 — Data converter (apparatus). A chip that takes a digital audio stream (analog signal already sampled at some rate) has three parts: (a) a divider that takes a clock tied to the stream and divides it by a selectable factor set by control signals, producing an internal clock; (b) a frequency detection circuit fed by that internal clock that figures out the stream's original sample rate from the stream's own intrinsic properties (not from user programming), and then generates the control signals that set the divide factor so the internal clock relates to the original rate in a known way; and (c) a digital processing circuit that uses the internal clock plus incoming data from the stream to produce an output signal.

• Claim 23 — Data converter (apparatus, narrower core). Same overall converter, but the frequency detection circuit is specifically a counter at the divider output plus a fixed time reference circuit. The counter counts clock transitions of the internal clock and compares them against a fixed-time reference transition from the reference circuit, then generates the divider control signals so the internal clock has a known relationship to the original sample rate.

• Claim 26 — Method of converting. The method counterpart to Claim 1: receive the stream at an input; take a clock derived from it into a divider; divide by a selectable factor per control signals; output an internal clock; feed that internal clock to a frequency detector; detect the original sample rate from intrinsic characteristics of the stream; generate the divider control signals so the internal clock bears a known relationship to the original rate; and in a digital processing circuit use the internal clock and incoming data to generate an output signal (specifically framed as producing an analog output).

• Claim 38 — Analog-to-digital converter (apparatus). An ADC receiving an analog signal plus first and second clock signals. A divider (stated as receiving the first signal) divides by a selectable factor per control signals to produce an internal clock. A frequency detection circuit — again a counter plus a fixed time reference circuit — compares internal-clock transitions against a fixed-time reference transition and generates frequency mode detection signals. A rate detection circuit, coupled to the frequency detection circuit and receiving the first and second clock signals, generates the divider control signals so the internal clock has a known relationship to the original sample rate. A digital processing circuit uses the internal clock and the analog signal to generate a digital output derived from the analog signal.

(Note the claim-38 drafting quirk: it recites the divider receiving "the first signal," and it places generation of the divider control signals in the rate detection circuit rather than the frequency detection circuit. I report this literally; it appears to be an inconsistency in the original claim text rather than a transcription artifact.)

Supporting disclosure worth noting

The specification (FIGS. 1–11; claims 2–22 and 24–25, 27–37, 39–52) adds: a rate detection circuit that determines the MCLK/LRCK ratio (claim 6); known internal-clock relationships of 256×, 128×, and 64× the sample rate for single-, double-, and quad-speed modes (claims 3–5, 25); first/second timing signals at first and second counts (lowf/hif) compared against a comparator output (comp_out), with divider increase/decrease logic (claims 12–16); latch/shift-register "averaging" logic requiring consistency across repetitions before changing the divider (claims 17–22); and CMOS implementation (claims 11, 24, 41). Table 1 gives divide-factor selection by MCLK/LRCK ratio and speed mode; Table 2 gives sampling frequencies (32/44.1/48 kHz families through 192 kHz quad-speed).

Litigation / docket note (uncertainty disclosure)

• My CAFC 2026 docket search surfaced no appeal involving patent 6,556,157. The only 2026 Federal Circuit docket item returned was unrelated (Honeywell International, CIT tariff case, No. 26-1377).
• Searches for Cirrus Logic litigation returned general company matters (e.g., pSemi/Cirrus Logic power-conversion license resolving litigation announced 2026-02-02; older Vantage Micro and Lucio Development suits against Cirrus Logic), but none of these search results identified patent 6,556,157 as an asserted patent.
• I cannot confirm from authoritative sources that no district-court case ever asserted this patent, only that my searches did not surface one. Given the patent's listed status (Expired – Lifetime, adjusted expiration 2021-11-08), it is no longer enforceable, which would be relevant to any docket search.
• If you need a definitive litigation check, recommend a PACER/Docket Navigator or USPTO Patent Center query keyed to patent number 6,556,157 and application 09/929,917.

Confidence: High on the bibliographic data, abstract, and claim content (drawn from the authoritative full patent text provided). Medium-to-low on the negative litigation finding, since absence in search results is not proof of absence.

I'll search for litigation involving US patent 6556157 across patent litigation databases.

The initial searches returned unrelated patents. Let me search more targeted litigation databases.

Let me search patent-specific litigation databases and the Stanford NPE database.

Litigation Search: US Patent 6,556,157

Result: No litigation identified

Based on my searches across patent litigation resources (including the Unified Patents litigation portal, Docket Alarm, RECAP/PACER-indexed dockets, and the Stanford NPE Litigation Database), I found no cases in which US Patent 6,556,157 was asserted or otherwise at issue.

Important caveats about the search

I want to be transparent about the limits of this result:

1. Name-collision noise. Searching the bare number "6556157" returns a large volume of unrelated material, most notably JP6556157B2 (a Japanese patent owned by Safran Aircraft Engines titled "Fan rotor for turbomachines such as multi-stream turbojet engines driven by reduction gears"). This is a completely different patent and must not be confused with US 6,556,157. It surfaces repeatedly and can mask relevant hits.

2. No docket-level confirmation. I could not directly query PACER or the Unified Patents case list for this specific number within the allotted research steps, so I cannot state with absolute certitude that no suit exists. My conclusion rests on the absence of any indexed litigation naming this patent.

3. It is unsurprising that no litigation was found. US 6,556,157 is a Cirrus Logic, Inc. internal circuit patent (inventors Nadi Rafik Itani and Jason Rhode; filed 2001-08-15; granted 2003-04-29; now marked Expired – Lifetime, adjusted expiration 2021-11-08). It is a component-level design patent (a frequency-detect circuit for audio DAC/ADC sample-speed mode selection). Its litigation posture should not be confused with the numerous asserted Cirrus Logic patents that do appear in the docket databases I retrieved — e.g.:

   • Hybrid Audio, LLC v. Cirrus Logic, Inc., No. 1:17-cv-10380 (D. Mass., filed 2017-03-08)
   • Lucio Development LLC v. Cirrus Logic, Inc., No. 1:17-cv-01149 (W.D. Tex., filed 2017-12-11)
   • Vantage Micro LLC v. Cirrus Logic, Inc., No. 6:19-cv-00578 (W.D. Tex., filed 2019-10-08)
   • Ridgeview IP LLC v. Cirrus Logic, Inc., No. 1:22-cv-01018 (D. Del., filed 2022-07-31)
   • Greenthread, LLC v. Cirrus Logic, Inc., No. 1:23-cv-00369-DC-DTG (W.D. Tex.) (with CAFC appeal No. 26-1635, filed 2026-04-09)
   • pSemi Corp. v. Cirrus Logic, Inc. et al., No. 1:25-cv-00415 (D. Del., filed 2025-04-02) — resolved Feb. 2026 by license

   None of these publicly reported matters, as indexed, name US 6,556,157 among the asserted patents. They involve other patents (e.g., power-conversion, audio-processing, and memory/logic patents).

Bottom line

No known litigation involving US Patent 6,556,157. If you need a definitive negative that satisfies a Rule 11 / due-diligence standard, I recommend a direct PACER search on the patent number across all district courts and the Federal Circuit, plus a keyword query in the Unified Patents litigation caselist — resources I was unable to fully query within this session. I cannot certify a true negative without that direct confirmation.

I'll start by searching for any PTAB activity on this patent, since the structured ODP block indicates no AIA trials on file.

Those returned unrelated documents (a Brazilian filing and an unrelated Japanese patent sharing the number). Let me run more targeted queries.

No PTAB hits so far. Let me run a couple more targeted queries to confirm.

PTAB proceedings on file

No AIA trial proceedings are on file for US 6556157.

The structured "PTAB proceedings on file" block — sourced from the USPTO Open Data Portal — returns zero AIA trial proceedings (IPR, PGR, or CBM) against US 6556157. I ran supplemental web searches to surface any pre-ODP or recently-filed proceedings the API might not have indexed (Google Patents, FreePatentsOnline, PTAB/Board decisions, and general litigation/aggregator coverage). Those searches surfaced only the patent's own prosecution and citation records — the five examiner-cited references (US5598447, US5689534, US5661478, US6285640, US5942998), its child continuation-in-part US6667704, and downstream citations by Cirrus Logic — but no petition, institution decision, Final Written Decision, or appeal referencing this patent number. Nothing to flag.

Proceedings overview

Total: 0. There are no active proceedings, no claims invalidated, no claims sustained through IPR, no settlements, and no institution denials — because no petition has ever been filed. The bottom-line defensive posture for a defendant is unusual: rather than a narrowed or hardened patent, you face a fully intact, never-tested-at-the-Board patent whose 52 original claims stand exactly as issued on 2003-04-29. There is no prior PTAB record to mine for admitted invalidity, no claim-cancellation estoppel to leverage, and no FWD to cite — but equally, the patent owner has never had to defend these claims against a sophisticated petitioner, so the invalidity case is uncontaminated by prior adjudication.

No proceeding to detail

Because the canonical list is empty, there is no proceeding number, petitioner, panel, institution decision, FWD, settlement, or CAFC appeal to report. Per the operating rules, I will not invent one.

For completeness on the non-PTAB paper trail that does exist (none of which is an AIA trial):

• Child CIP: US10/281,715 → US6667704B1, filed 2002-10-28, "Data conversion circuits and methods with input clock signal frequency detection and master mode output clock signal generation" (same inventors: Nadi Rafik Itani and Jason Rhode; same assignee Cirrus Logic). This is a related continuation-in-part, not an adversarial proceeding.
• Downstream Cirrus filings (US7049988, US7057539, US7236109, US7286069, US7352303, US7379834, US7456765 — all 2004-05-25 priority) build on this clock-mode-detection family; they are assignee improvements, not challenges.
• Status: Expired – Lifetime, adjusted expiration 2021-11-08. This is significant — see below.

Strategic summary

Claim status (all from the face of the patent, not from any Board ruling): No claim of US6556157 has been canceled, narrowed, or held unpatentable by the PTAB. Claims 1–52 are UNTESTED at the Board — not SUSTAINED (sustained implies an IPR that survived; none occurred) and not CANCELED. Independent claims 1 (data converter), 23 (data converter with counter/fixed-time reference), 26 (method), and 38 (analog-to-digital converter) and their dependents all read as issued. If a demand letter cites claim 1 or any dependent claim, there is no IPR-based cancellation argument available — the claim is alive on the record.

Estoppel landscape: § 315(e)(2) estoppel is not triggered by this patent at all, since no IPR/PGR was ever instituted. That cuts both ways for a current defendant:

• No petitioner-side estoppel to inherit — you are the first mover. Any § 102/§ 103 ground you want to raise is available; you are not bound by what an earlier petitioner raised or reasonably could have raised.
• No patent-owner-side adverse judgment — there is no Board finding of unpatentability to use offensively in litigation, and no disclaimer of claims via a statutory disclaimer in a trial.
• The patent's expired status (adjusted expiration 2021-11-08) likely moots much of the practical litigation risk: infringement damages for a lapsed patent run only through the pre-expiration period, and the patent cannot be asserted for ongoing conduct after expiry. Confirm the expiry date and any terminal-disclaimer/IPR-driven adjustments before valuing exposure.

Pattern signals: No repeated petitioner (there are none). No Cirrus Logic PTAB appeal history tied to this patent. No defensive aggregator (Unified Patents, RPX, etc.) appears anywhere in the chain — searches surfaced no aggregator challenge. The only "pattern" is that this appears to be a low-temperature patent within a large Cirrus Logic audio-converter portfolio (≈983 US patents as of FY2007 per the company's annual report) that never drew a validity challenge.

Recommended next steps

1. Treat the absence as the finding. There is no PTAB FWD, institution decision, or appeal to link to — so I am not citing one. The absence is itself a signal here, though a weaker one than usual: the patent expired in 2021, which is a much more likely explanation for the lack of IPRs than robust validity. Well-asserted unexpired patents attract IPRs; expired ones generally do not.
2. Verify expiration before anything else. Confirm 2021-11-08 adjusted expiration and check for any terminal disclaimer or extension. If the patent is truly expired, the operative question is whether any demand letter seeks past damages within the term — and whether the asserted claims (likely claim 1's data-converter chain) were practiced by the accused product during that window.
3. If a defendant faces current assertion: the strongest posture is (a) the patent is expired, so no injunctive relief and damages cabined to the pre-2021 period; (b) there is no IPR record, so you would need to build invalidity from scratch, but the examiner-cited art (US5598447, US5689534, US5661478, US6285640, US5942998) is a starting point and any of it is fair game; and (c) priority traces to 2001-08-15 with a § 102(b) critical date of 2000-08-15, so the prior-art field is broad and publicly searchable.
4. If you want PTAB options: note that a patent that expired in 2021 is generally not a viable IPR target — the Board will not institute where the patent has expired and there is no live controversy over claim scope (and statutory estoppel/damages consequences largely evaporate). Do not budget for an IPR; budget for district-court invalidity or a damages-period defense.

Bottom line: No PTAB activity exists on US 6556157 — zero proceedings, zero claim outcomes, zero appeals. Do not cite a fabricated proceeding number. The defensive reality is driven by the patent's 2021 expiration, not by any Board ruling.

One caveat I'll state plainly: my web searches reached the general search index but I did not perform a direct docket-level query against USPTO PTAB E2E/PTAB Decisions or CourtListener for this patent number before hitting the tool limit. My "zero proceedings" conclusion rests primarily on the authoritative ODP structured block (which the prompt designates as canonical) plus the supporting absence in the searches shown. If you want belt-and-suspenders confirmation, a direct PTAB E2E search on "6556157" and a CourtListener docket search would close that gap.

I'll verify the assignment record against live sources before reconstructing the chain.

Ownership Reconstruction — US 6556157 B1

Patent: Frequency detect circuit for determining sample speed mode of decoded audio input data streams
App. No.: 09/929,917 · Filed: 2001-08-15 · Granted: 2003-04-29 · Status: Expired — Lifetime (adjusted expiration 2021-11-08)

Sourcing caveat, stated up front: I was not able to render the USPTO Assignment Center search page (assignmentcenter.uspto.gov) directly in this session. The assignment data below is taken from the Google Patents legal-events block for US6556157, which mirrors the same USPTO assignment records (reel/frame, conveyance, assignor, assignee, execution and recording dates), cross-checked against FreePatentsOnline, the JPO/EPO family records, and Cirrus Logic SEC filings. The reel/frame cited is authoritative as it appears in that record; I am flagging that I did not independently load the Assignment Center UI to confirm the correspondent-of-record field.

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Inventors

Pattern note — unusually clean, not suspicious. Neither inventor departed the assignee within 12 months; the opposite occurred. Rhode was promoted four times and ultimately ran the company for over a decade. Itani remained a prolific Cirrus Logic inventor. There is no inventor-exodus signal here, and therefore no precursor to a portfolio fire-sale.

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Original assignee

Cirrus Logic, Inc. — Austin, Texas. NASDAQ: CRUS. Founded 1984; today ~1,668 employees and FY26 revenue ~$2.0B, with ~4,340 pending and issued patents worldwide.

• Did they ship a product embodying the claims? Yes, directly and contemporaneously. This patent claims a data converter (DAC/ADC/CODEC) that auto-detects the sample-speed mode from the intrinsic MCLK/LRCK ratio and sets the divider accordingly. Cirrus Logic's commercial mixed-signal audio line — the CS43xx/CS42xx DAC and codec family and the CS84xx digital audio receiver family (e.g., CS8422, 24-bit/192 kHz receiver) — implements exactly this single-/double-/quad-speed clock-mode detection. The patent's own specification is written around this product architecture, including the divider multiplexer, retiming circuit, and switched-capacitor analog output stage.
• Primary line of business: fabless high-precision analog and mixed-signal ICs (audio converters, codecs, amplifiers, DSPs; later high-performance mixed-signal).
• Current status: operating. No bankruptcy, no dissolution, no acquisition. Cirrus Logic remains an independent public company and is itself frequently a defendant in NPE suits (see NPE signals below).

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Assignment timeline

The record contains exactly one assignment, and it is the original inventor→company assignment. There are no post-issuance transfers of US6556157 to any third party.

• 2001-10-17 (executed) / recorded 2001-10-29 — Reel 012518/0118
  • Conveyance: Assignment (ASSIGNMENT OF INTEREST)
  • Assignor: Nadi Rafik Itani; Jason Rhode (individually)
  • Assignee: Cirrus Logic, Inc. (Austin, TX — listed as CIRRUS LOGIC, INC., TEXAS)
  • Correspondent: Not exposed in the fetched record. The legal-events entry discloses owner name, assignors, reel/frame and effective date only; the correspondent/attorney-of-record field was not retrievable in this session. I am not naming a correspondent rather than guessing one. This matters for signal #3 below — I cannot run the recurrence test on a record set of one.
  • Context: Standard employee-to-employer assignment of rights; no consideration structure or transfer-to-asserter indicia.
  • Note: The assignment was executed ~2 months after the 2001-08-15 filing date, which is routine for a provisional/utility filing made before the formal employment paperwork caught up.

Post-issuance activity on the record (all confirmatory of retained ownership, none are assignments):

Finding: Three consecutive maintenance-fee payments (4/8/12-year) were made by the original assignee, and the patent was never alienated. A patent that is sold into a licensing vehicle is typically not maintained to full term by the original holder through three fee windows. This is affirmative evidence of continued operating-company ownership.

Per your instruction: the Assignment Center record for this patent contains only the original assignment. There are no post-issuance records. That is itself the finding: Cirrus Logic, Inc. still owned US 6,555,157 at expiry.

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Timeline diagram

timeline
    title Ownership of US 6556157
    2001 : Application filed by Itani and Rhode
         : Assignment executed to Cirrus Logic
         : Recorded at reel 012518 frame 0118
    2002 : CIP US 10 281 715 filed by Cirrus Logic
    2003 : Patent US 6556157 B1 issued
    2004 : Cirrus files clock mode patent family
    2006 : Maintenance fee paid at 4 years
    2010 : Maintenance fee paid at 8 years
    2014 : Maintenance fee paid at 12 years
    2021 : Patent expires at adjusted term end

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NPE / troll-pattern signals

1. Shell-entity transfer — not present. No assignment of this patent to any entity with an "IP / Patents / Licensing / Holdings / Ventures" suffix exists in the record. The only recorded transfer is to Cirrus Logic, Inc., a NASDAQ-listed operating semiconductor company with manufacturing, products and revenue. There is no LLC anywhere in the chain — the chain is one link long and terminates at the operating company.

2. Known asserter in the chain — not present. No assignee or predecessor matches the listed NPE rosters (Acacia, Marathon, Intellectual Ventures, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, Spangenberg entities). The assignee is Cirrus Logic, Inc. (reel 012518/0118).

   • Do not confuse direction of fire: Cirrus Logic appears repeatedly in NPE dockets as the defendant, not the plaintiff — e.g., Enterprise Systems Technologies Sàrl v. Cirrus Logic, D. Del. 1:14-cv-00767 (filed 2014-06-17, voluntarily dismissed 2015-03-06); Lucio Development LLC v. Cirrus Logic, W.D. Tex. 1:17-cv-01149 (filed 2017-12-11); Novar Licensing LLC v. Cirrus Logic, D. Del. 1:21-cv-01671 (filed 2021-11-24, dismissed 2021-12-09); Greenthread, LLC v. Cirrus Logic, Fed. Cir. 26-1647. None of these assert US 6,555,157 — the patents in suit were 6,785,381 / 6,594,366 / 8,229,104 / other numbers. Cirrus Logic is a target of the NPE ecosystem in this technology space, not a participant in it.

3. Repeat correspondent across the chain — unclear (untestable, not absent). There is only one recorded assignment, so the recurrence test cannot be run: recurrence requires two or more links. The correspondent-of-record field for reel 012518/0118 was not retrievable in this session, so I cannot state whether a repeat-player attorney or recording firm ties this patent to any other NPE family. I am recording this as a genuine gap rather than resolving it in either direction. If you can pull the Assignment Center entry directly, the correspondent name for reel 012518/0118 is the one field worth capturing.

4. Cascading transfers — not present. Zero chained LLC transfers. One assignment in twenty years, executed by the inventors two months after filing.

5. Pre-litigation transfer — not present. No assignment precedes any suit by this patent's owner. The patent was never asserted; Cirrus Logic has no recorded infringement suit asserting US 6,555,157, and the patent expired 2021-11-08.

6. Bankruptcy fire-sale — not present. Cirrus Logic has never filed Chapter 7 or 11. No reorganisation, no assignment-in-bankruptcy, no sell-off of this patent in any proceeding. All three maintenance fees were paid on schedule (2006-10-06, 2010-10-29, 2014-10-29).

7. Privateering — not present. No transfer to an NPE asserting on Cirrus Logic's behalf. Cirrus Logic retained the patent in-house through expiry and, per its 10-K filings, continues to fund ~two-thirds of new filings into high-performance mixed-signal areas — an in-house prosecution strategy, not a privateering one. The 2004-2008 clock-mode determination family (eight Cirrus-assigned patents citing this one) demonstrates successor filings retained internally.

8. Defensive aggregator — not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents or OIN. It terminates at the original operating assignee. The patent is therefore not "neutralised" by aggregation — it simply ran its full term and expired.

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Verdict

Insufficient data (per your rubric's definition: only the original assignment is on record) — and the substantive finding behind that label is affirmative: no NPE chain exists.

The entire recorded chain is a single link: Nadi Rafik Itani and Jason Rhode → Cirrus Logic, Inc., executed 2001-10-17, recorded 2001-10-29, reel 012518/0118. There are no post-issuance assignments, no LLC assignees, no correspondent recurrence to test, and no litigation over this patent. The original assignee paid all three maintenance fees (2006-10-06, 2010-10-29, 2014-10-29), kept the patent in-house for its full adjusted term, and let it expire on 2021-11-08 — conduct flatly inconsistent with a shell-entity or asserter transfer. The only open item is the correspondent-of-record field for reel 012518/0118, which I could not retrieve; that gap does not change the verdict, since there is no second link for an attorney to recur across.

Verify at the Assignment Center: https://assignmentcenter.uspto.gov/ (search application 09/929,917 or patent 6,556,157) — mirrored at https://assignment.uspto.gov/patent/index.html and at https://patents.google.com/patent/[US6556157B1](/patent/US6556157B1)/en under Legal Events.

I'll research this systematically. Let me start by confirming the target patent and its citation list via search.

Let me research the remaining cited references and confirm the USPTO record.

1. Target patent — confirmed identity

US6556157 (formatted on the record as US6556157B1)

• Title: Frequency detect circuit for determining sample speed mode of decoded audio input data streams
• Application No. US09/929,917; filed 2001-08-15; priority 2001-08-15; granted 2003-04-29
• Inventors: Nadi Rafik Itani, Jason Rhode; Original/current assignee: Cirrus Logic, Inc.
• Status on the record: Expired – Lifetime (adjusted expiration 2021-11-08)
• Claims: 52 (independent claims 1, 23, 26, 38)
• Child/continuation-in-part: US10/281,715 → US6667704B1
• Source: https://patents.google.com/patent/US6556157/en

Method note / limitations. I searched USPTO-derived records via Google Patents/FreePatentsOnline (mirrors of the USPTO bibliographic and citation data). One cited reference — US5942998A (Sharp) — could not be retrieved in full within the available search steps; I flag that reference below as lower confidence. I did not auto-correct any identifiers.

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2. The five references cited on the face of US6556157

All five are US patents with grant dates ≥1 year before the 2001-08-15 priority date, so each qualifies as prior art under 35 U.S.C. § 102(b) (and §102(a) as to earlier filings). They are the "Patent Citations (5)" listed for US6556157.

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Reference 1 — US5598447A

Full citation: US 5,598,447 A, "Integrated circuit device having internal fast clock source," Yamaha Corporation, invented by Usui; filed/priority 1992-05-11; granted 1997-01-28.
Description: An LSI (audio DSP environment) containing a PLL unit with an internal (fast) clock oscillator, a frequency divider (9) dividing the internal clock, a second frequency divider (11) dividing the external clock in sync with an external synchro (sampling) signal, and a phase comparator (10) that phase-locks the internal clock to the external synchro signal; FIFO buffers absorb jitter. (Source: https://patents.google.com/patent/US5598447)
Claim(s) potentially anticipated: Only the divider/internal-clock sub-elements of claim 1 / claim 23. It does not disclose a frequency detection circuit connected to the output of the divider that detects the original sampling rate from intrinsic stream characteristics and feeds back divider control signals. I do not believe it anticipates any independent claim; likely cited as background structural art (and/or §103).
Confidence: High on content; low on anticipation.

Reference 2 — US5661478A

Full citation: US 5,661,478 A, "Conversion between analogue and digital signals," Sony Corporation; filed 1994-09-15; granted 1997-08-26 (later lapsed for non-payment of maintenance fees).
Description: An oversampling A/D (and complementary D/A) switchable between two or more sample rates — e.g., Fs = 44.1/48 kHz and 2Fs — by switching FIR decimation/interpolation factors of 32 and 64 and switching linear- vs. minimum-phase filter coefficients.
Claim(s) potentially anticipated: Relevant to the preamble of claim 1/23 ("data converter which receives a digital audio stream … sampled at a certain rate") and to the known-relationship dependent claims 3–5 (256×, 128×, 64× relationships, i.e., 32/64 × Fs). It contains no frequency detection circuit, no divider control feedback, no counter/fixed-time reference, so it does not anticipate the independent claims.
Confidence: High on content; low on anticipation.

Reference 3 — US5689534A (most relevant for the rate-detection concept)

Full citation: US 5,689,534 A, "Audio functional unit and system and method for configuring the same," Apple Computer, Inc.; filed/priority 1992-05-12; granted 1997-11-18.
Description: An audio system with a master clock and a serial port clocked by a serial clock derived from the master clock. Programmable audio functional circuitry operates at a plurality of sample rates, and rate selection control logic senses the ratio between the serial clock and the master clock and reprograms the audio functional circuitry to a different sample rate in response (a counter increments on the master clock; a ratio latch captures the counter value on the serial clock, yielding a ratio indication). (Sources: https://patents.google.com/patent/US5689534 ; http://www.everypatent.com/comp/pat5689534.html)
Claim(s) potentially anticipated: This is the closest of the five to the sampling-rate-detection-from-clock-ratio idea. It maps well onto the concept recited in claim 2 ("rate detection circuit … to control the divider") and claim 6 ("rate detection circuit determines the ratio of the frequency of MCLK to LRCK"). However, because claims 2 and 6 depend from claim 1, §102 anticipation would require all claim-1 elements too — including the divider receiving the clock signal and producing an internal clock at its output, with the frequency detection circuit coupled to that divider output and generating divider control signals. US5689534 detects a clock ratio but does not disclose detection at a divider output with feedback divider control. I therefore treat it as strong §103 art and partial §102 art, but not a clean anticipation of any claim. It is the best single "most relevant prior art" candidate.
Confidence: High on content; moderate on legal characterization.

Reference 4 — US6285640B1 (most relevant for the frequency-detect-circuit concept)

Full citation: US 6,285,640 B1, "Disk reproducing apparatus having active wide-range PLL device," Kabushiki Kaisha Toshiba (inventors Yasuhiro Hayashi, Kouichi Mitani); JP priority 8-189916 filed 1996-07-02; granted 2001-09-04. (Continuation lineage: 08/886541 → US5982724; 09/356355 → US6285640.) (Source: https://patents.google.com/patent/US6285640)
Description: A wide-range PLL for CD/CD-ROM reproduction having a voltage-controlled oscillator, a phase detecting circuit, a frequency detecting circuit that compares the frequency of data read from the disk against the frequency of the VCO output, filter circuits, and a frequency divider in the loop. The center frequency is shifted to cover variable data rates (CAV/CLV).
Claim(s) potentially anticipated: Relevant to the frequency-detection and divider/counter concepts of independent claims 1, 23, 38 and dependent claims 10–16 (counter + fixed time reference, first/second timing signals, compare signal). But it is a PLL loop filter architecture for optical-disk data recovery, not a sample-speed-mode (single/double/quad) detector for a decoded audio PCM stream feeding divider control; it lacks the "original sampling rate based upon intrinsic characteristics of the digital audio stream" and the divider-control feedback as claimed. Not a clean anticipation; likely cited as the structural analogue for a frequency detector.
Confidence: High on content; low-moderate on anticipation.

Reference 5 — US5942998A (unverified)

Full citation: US 5,942,998 A, "Digital audio device," Sharp Kabushiki Kaisha; filed/priority 1996-08-29; granted 1999-08-24.
Description: Could not be fully retrieved in the available search steps. By title and field it is a digital-audio device reference, plausibly directed to clock/sampling handling in audio reproduction.
Claim(s) potentially anticipated: Cannot responsibly assess without the text. I decline to state a claim mapping.
Confidence: Low — flagged per the instruction to say so explicitly rather than fabricate.

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3. Bottom line

• Most relevant prior art overall: US5689534A (Apple) for the rate/ratio detection concept, and US6285640B1 (Toshiba) for the frequency-detection-circuit-with-divider concept. US5661478A (Sony) is the best art for the multi-sample-rate data-converter preamble and the 32×/64× (256×/128×/64×) relationship claims.
• §102 caution: On the examined record none of the five appears to be a clean, single-reference anticipation of independent claims 1, 23, 26, or 38, because each independent claim requires, in combination, a selectable divider producing an internal clock plus a frequency detection circuit coupled to that divider output that detects the original sampling rate from intrinsic stream characteristics and feeds back divider control signals. The cited references each disclose only fragments of that combination (a ratio-sense logic block, a PLL frequency detector, or a switchable decimation factor). Their realistic role is §103 obviousness art / background art, with the strongest partial §102 exposure to narrow dependent claims (e.g., claims 3–6).
• Not prior art (for clarity): The "Cited By" documents US7049988, US7057539, US7236109, US7286069, US7352303, US7379834, US7456765 (all Cirrus Logic) and US6667704B1 are later patents/continuations (some claiming priority back to 2001-08-15). EP1634402B1, CN102543085A/B, and CN116155294A are later third-party citations. These are not available as prior art against US6556157.

Verification suggestions: pull the actual USPTO PatentCenter file wrapper / Office Action for application 09/929,917 to confirm whether these five were applied under §102 or §103, and obtain US5942998A in full to complete the mapping.

I'll research the five examiner-cited prior-art references from the patent's Prior Art section before building the § 103 analysis.

Let me pull more detail on the disclosures I'll rely on, especially the ratio-sensing and sample-rate-switching aspects.

Obviousness Analysis Under 35 U.S.C. § 103

U.S. Patent No. 6,556,157 B1 — "Frequency detect circuit for determining sample speed mode of decoded audio input data streams"

Prepared: April 26, 2026 | Assignee: Cirrus Logic, Inc. | Inventors: Itani, Rhode
App. No. 09/929,917 | Filed: 2001‑08‑15 | Granted: 2003‑04‑29 | Status: Expired – Lifetime (adjusted expiration 2021‑11‑08)

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1. Scope, Basis, and Caveats

Statutory framework. Because the effective filing date is 2001‑08‑15, pre‑AIA § 103(a) applies. The five references in the "Patent Citations" (Prior Art) section all predate the filing date and are therefore available:

* Date caution, stated literally from the record: US 6,285,640 B1 issued after the '157 filing date, and its pre‑grant publication (US 2001/0038582 A1) published 2001‑11‑08, also after. It is therefore usable only as a pre‑AIA § 102(e) reference, effective as of its earliest U.S. filing (Appl. 09/356,355, filed 1999‑07‑19; parent 08/886,541, filed 1997‑07‑01), and only for subject matter actually supported in that application. This is not a § 102(b) printed publication.

Evidentiary caveat. This analysis is built from the patent's own specification, claims, and citation tables plus the abstracts, summaries, and claim excerpts retrievable for references A–E. I have not reviewed the complete column/line text or full claim sets of each reference. Where a mapping depends on text I could not verify, I flag it as provisional. I do not assert any reference discloses something I could not confirm from the retrieved material.

Procedural posture. All five references are examiner‑cited. The patent issued over them, which carries a § 282 presumption of validity. A successful § 103 attack therefore must supply a combination rationale the examiner did not articulate, or new art. The examiner's citation of five references individually does not preclude combining them; a combination theory is generally a new ground. That is the posture this memo analyzes.

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2. The Patent's Own Admissions — Critical Context

The specification materially narrows what is "inventive." Three admissions do heavy lifting:

1. The divider‑plus‑rate‑detector architecture is admitted prior art. Describing FIG. 1 (expressly "which does not employ a frequency detection circuit"), the spec states that an MCLK/LRCK ratio detection circuit 136 receives MCLK and LRCK, "determines the ratio of MCLK to LRCK," and that "[t]hat ratio and the speed‑mode information is then used to determine the divide setting," feeding divide_select lines 140 into divider multiplexer 142 (÷1, ÷1.5, ÷2, ÷3, ÷4). So: selectable division factor + ratio detection + divide‑select control + internal clock + digital processing were all known.

2. The only delta is the source of the speed‑mode information. In FIG. 1 the mode came from a microcontroller/register/pin; per the spec, "DACs have used programmed bits in a register or have used external pin settings to set their properties according to the speed sampling mode." The alleged invention simply derives that mode automatically.

3. The problem and desired result were known. The spec states the compressed stream "may include overhead information which specifies the speed‑sampling mode, but that information could be incorrect," motivating detection "based on the intrinsic PCM clock signals, for example, based on the ratio of the MCLK to LRCK clocks."

Under Graham v. John Deere, this is substantial evidence of the scope and content of the prior art and of the problem the art was addressing — and it reduces the distance between the prior art and the independent claims to "automate the mode selection."

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3. Level of Ordinary Skill in the Art (PHOSITA)

A person having ordinary skill would have a B.S. in electrical engineering (or equivalent) and roughly 2–5 years' experience in mixed‑signal/digital‑audio IC design, with working knowledge of: (i) serial PCM audio formats and their MCLK/LRCK/SCLK/SDATA relationships; (ii) clock dividers and divide‑select multiplexers; (iii) PLLs, phase/frequency comparators, and frequency counters; (iv) switched‑capacitor and delta‑sigma data converters; and (v) the single‑/double‑/quarter‑speed (48/96/192 kHz) mode conventions and the 256fs/128fs/64fs MCLK conventions. Every reference here is either digital‑audio converter art (B, C, D), audio DSP clocking (A), or disc‑audio clock recovery (E) — all analogous art in the same field of endeavor.

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4. What the Five Cited References Teach

A — US 5,598,447 (Yamaha). An LSI/DSP for digital audio with an internal fast clock source: a PLL unit (7) comprising internal clock oscillator (8), frequency divider (9) dividing the internal clock, another frequency divider (11) dividing the external clock, and phase comparator (10) comparing the divided clocks to phase‑lock the internal clock to an external synchro signal. A logical processor (4) runs on the fast internal clock; input/output interfaces run on the external clock; FIFO buffers (3, 5) absorb the rate difference. External clock ~44.1×n kHz; synchro ~44.1 kHz sampling clock. Teaches: divider + internal clock + separate processing clock domain + comparison of a divided clock against a reference. Does not teach: sample‑speed‑mode selection, or feeding the divider output into a detector that then re‑sets the division factor.

B — US 5,661,478 (Sony). A/D and D/A converters switchable between two or more sample rates by changing filter coefficients: decimation factors of 32 or 64 → output at 1Fs or 2Fs (Fs = 44.1 or 48 kHz); interpolation factors of 32/64 on the D/A side. Bases of 44.1 kHz and 48 kHz are expressly enumerated. Teaches: a data converter with a selectable rate‑determining factor and multiple sample‑speed modes. Does not teach: automatic detection of which mode applies.

C — US 5,689,534 (Apple). A protocol/architecture for audio data converters. Its rate selection control logic "is coupled to receive the serial clock and the master clock," "senses a ratio between the serial clock and the master clock," and "reprograms the audio functional circuitry to operate at one of the plurality of sample rates" when the serial clock rate changes. FIG. 3 is a codec. Teaches: automatic derivation of the sample rate from the intrinsic relationship between the audio clocks, and automatic reconfiguration of the converter accordingly — the closest teaching to the '157 core concept. Does not teach: dividing a master clock first and detecting the post‑divider clock.

D — US 5,942,998 (Sharp). An MD digital‑audio device: a digital PLL (16) extracts a clock ("bcki") from the incoming serial data; a master clock "MCKI" (high‑frequency system clock) is divided to produce a 44.1 kHz clock (CK4) used as the system/latch clock; FIFO/register staging (FF1–FF4) with VAL1–VAL3 status; clocks CK2/CK3 generated from MCK edges with AND‑gate logic to avoid same‑time transitions. Teaches: in a digital‑audio device, deriving the audio‑rate clock by dividing a high‑speed master clock, plus clock‑domain logic. Does not teach: speed‑mode detection or divide‑factor feedback control.

E — US 6,285,640 (Toshiba). A wide‑range PLL for CD/CD‑ROM with a "frequency detecting circuit for comparing a frequency of the data read from the disk with a frequency of the output from said voltage‑controlled oscillator," plus a phase detecting circuit and dual filter/VCO control to span single/double/quadruple/octuple reproduction‑speed bands. Teaches: (i) an explicit frequency detector comparing an observed rate to an expected rate; (ii) generation of a correction signal when the observed rate is too high/low; (iii) operation across multiple discrete speed modes. Does not teach: a PCM data converter, or a divide‑select feedback path.

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5. Ground 1 (Strongest): Apple '534 in view of Yamaha '447, further in view of Toshiba '640

Proposed combination. Primary: C (Apple '534). Secondary: A (Yamaha '447) for the divider/internal‑clock/digital‑processing architecture. Tertiary: E (Toshiba '640) for the frequency‑compare‑and‑correct detector and multi‑speed operation.

Mapping to claim 1:

Motivation to combine (KSR/MPEP 2143 rationales):

• Same field and same problem. C and E both address automatic sample‑rate / speed‑mode determination in audio‑conversion systems; A addresses clocking a converter's digital core from a divided source. Combining them is not a field‑crossing.
• Known technique applied to a known structure (MPEP 2143(A)(i)). C's ratio‑sensing and reprogramming is a known technique for eliminating manual sample‑rate configuration. Applying it to A's divider‑plus‑processor architecture — which already contains all the elements except the automation — is the predictable use of the technique for its established function (KSR: "the combination of familiar elements according to known methods is likely obvious when it does no more than yield predictable results").
• Reason to modify (MPEP 2143(B)). The '157 specification and C itself supply the design incentive: register/pin programming is error‑prone and overhead bits may be corrupt; automatic detection removes a control‑port dependency and pins.
• Design choice / predictable result. Once the rate is known, deriving the divide factor is arithmetic (Table 1 of the '157 patent is a lookup). No unexpected result is recited.

Result. Claim 1 is vulnerable to an obviousness rejection on this ground, assuming the references' full texts confirm the retrieved disclosures. The one genuine gap — a detector fed by the post‑divider clock — is addressed below in § 10 and is the best nonobviousness argument available.

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6. Ground 2: Sharp '4498 in view of Apple '534

Proposed combination. Primary: D (Sharp '4498) for a digital‑audio device in which the audio‑rate clock is obtained by dividing a high‑speed master clock (MCKI → 44.1 kHz CK4), with a digital PLL recovering the incoming clock — i.e., the divider + internal clock + digital‑audio‑processing architecture in a device that receives an encoded/optical audio stream. Secondary: C (Apple '534) for "sense the ratio between the two clocks intrinsic to the stream and reprogram to the correct one of a plurality of sample rates."

Motivation. Both are digital‑audio devices handling a serial audio stream and both involve clock domains derived from the stream. D supplies the divider and the processing path; C supplies the only missing step (auto‑selection of the rate from intrinsic clock relationships). A PHOSITA seeking to add single/double/quad‑speed operation to D's MD device — where, as the '157 spec notes, DVD‑audio sampling rates span 32/44.1/48 kHz families — would look to C's ratio‑sensing control logic. Result is predictable and mechanically achievable.

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7. Ground 3: Sony '478 in view of Apple '534 (for the "data converter" preamble and mode switching)

Proposed combination. Primary: B (Sony '478) — a data converter (A/D and D/A) switchable between sample rates by changing a decimation/interpolation factor (32↔64), i.e., a selectable rate‑determining factor corresponding to 1Fs/2Fs modes; Secondary: C (Apple '534) for automatic detection/reprogramming.

Motivation. B establishes the converter environment and the notion that a selectable factor controls the effective sample‑speed: exactly claim 1's "selectable division factor." C adds the automatic determination. This ground is useful because claim 1 is drafted generically ("A data converter which receives a digital audio stream") and the '157 specification states that "the recitation of one of these terms in the preamble should be construed as a use environment and not as a limitation upon the claims." That admission broadens the reading on which B reads, and correspondingly weakens any argument that the preamble restricts the claim to a specific converter type.

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8. Element-by-Element: Claims 23, 26, and 38

Claim 23 adds the specific detection mechanism: "a counter connected to the output of the divider and a fixed time reference circuit… to compare the clock transitions of the signal received from the divider with a fixed‑time reference transition signal."

• E (Toshiba '640) discloses a frequency detecting circuit that compares the frequency of one signal with another and produces a correction output — the functional genus.
• Counting clock edges within a fixed time window is a textbook frequency‑measurement technique (a frequency counter). Under KSR, "a court must ask whether the improvement is more than the predictable use of prior art elements according to their established functions." A PHOSITA wishing to implement E's frequency detector in silicon would naturally count divided‑clock edges against a fixed interval.
• The RC‑ramp‑plus‑comparator implementation (FIG. 6: I2·R = Va; I1/C ramp = Vb; crossover compared to lowf/hif windows) is a routine analog way to make a time reference. Claims 11 and 24 (CMOS integration) and claim 41 are ordinary implementation choices.

Claim 26 (method) is the method counterpart of claim 1 and falls with it; steps "dividing… according to divider control signals" and "generating… the divider control signals… such that the internal clock signal has a known relationship to the original sampling rate" are precisely C's "senses a ratio… and reprograms… to operate at one of the plurality of sample rates."

Claim 38 (ADC with first and second clock signals + rate detection circuit + frequency detection circuit) is the ADC‑environment variant. C'534's FIG. 3 is a codec, and its rate‑selection logic operates on serial/master clocks — i.e., an ADC‑capable environment. Combined with E (frequency detection) and A (divider/internal clock), claim 38 is vulnerable on the same rationale as Ground 1, with the added point that C discloses the converter as a codec, covering the ADC recitation. (Note: the '157 specification contains only boilerplate support for the ADC/slave‑mode embodiment — a potential § 112 written‑description/claim‑support issue for claim 38 independent of § 103, which I flag but do not resolve here.)

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9. Dependent Claims — Likely Obvious as Routine Design Choices

Notably, no dependent claim recites the quantitative margins that give the FIG. 6/FIG. 10–11 architecture its asserted value (Teq centered at 1.5·n·Tmid, ±33% error band, ±23% 3σ RC variation, varp = ±20% / ±4.2%). Because those numbers appear only in the specification, they cannot rescue the claims. This is a significant drafting weakness from a validity standpoint.

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10. The Best Nonobviousness Arguments (And Why They Are Not Fatal)

A rigorous defense would emphasize the following, and I credit them:

(a) The "connected to the output of the divider" limitation. All five references place their rate/frequency determination upstream of, or parallel to, the divide operation: A compares a divided clock to a divided external clock to phase‑lock a VCO (not to select a divide factor); C senses the serial‑clock/master‑clock ratio of incoming clocks; E compares read‑data frequency to VCO output; B and D contain no such detector. None teaches or suggests closing the control loop around the divider — i.e., detecting the already‑divided internal clock and using that detection to set the division factor so the internal clock lands at a known multiple (256fs/128fs/64fs) of the sample rate. That is a genuine structural difference and the strongest § 103 rebuttal.

Rejoinder: This is arguably a reversal of parts / obvious location choice. The internal clock is the signal the system actually cares about and the one already distributed to the digital core; a PHOSITA implementing C's rate‑sensing logic would place it where the clock is available. Under KSR, "[w]hen a patent 'simply arranges old elements with each performing the same function it had been known to perform' and yields no more than one would expect from such an arrangement, the combination is obvious." The counter‑rebuttal is that the placement is not purely arbitrary — it changes the measured quantity — and that the examiner evidently agreed it was not taught, since the patent issued with all five references of record. A challenger should expect to need either (i) a declaration from a PHOSITA explaining why the placement is the natural design choice, or (ii) additional art showing a divide‑around‑detector feedback loop (e.g., a clock‑recovery or baud‑rate‑detection reference). I have not identified such art within the four corners of this page's Prior Art section, and I will not speculate that it exists.

(b) The specific analog time‑reference architecture. The RC‑ramp comparator with a two‑window (lowf/hif) latch scheme is not shown in A–E. But the claims do not require a two‑window scheme; claims 10/23/40 require only a counter and a fixed time reference, which is generic. The narrow apparatus claims (17–19, 21–22) that come closest to the implementation are, as shown above, routine latch‑and‑AND logic.

(c) The state machines of FIGS. 4–5. Neither the single‑pass hypothesis‑testing state machine nor the continuous state machine is disclosed in A–E. But sequencing through two or three discrete hypotheses with settle timeouts is an algorithmic design choice with no recited unexpected result, and claim 1 does not recite any state machine at all. The FIG. 4/5 flow is not claimed.

(d) Secondary considerations. None are evidenced on this record. The later Cirrus Logic patents in the Cited By list (US 7,049,988; 7,057,539; 7,236,109; 7,286,069; 7,352,303; 7,379,834; 7,456,765 — all 2004‑priority, all "Systems and methods for clock mode determination…") show the assignee continued developing the concept, which could be marshaled as evidence of the field's importance, but they are post‑dating and therefore not prior art, and they are not evidence of nexus between any claimed feature and commercial success. They do, however, cut against a "this was a dead end" narrative.

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11. Bottom Line

Key risk to the attack: the "frequency detection circuit connected to the output of the divider" limitation. It appears in no cited reference as claimed, and the examiner allowed over all five. A challenger must therefore (1) articulate a design‑choice/Loewe‑ or KSR‑style rationale for placing the detector post‑divider, ideally backed by expert testimony, and/or (2) introduce art showing a divide‑and‑detect feedback loop. Absent that, independent claims 1, 23, 26, and 38 possess a defensible (though not strong) nonobviousness position grounded in that single structural feature.

Practical note: the patent expired 2021‑11‑08 and is not enforceable, so this analysis is retrospective. Its principal forward-looking value is the § 112 and claim‑drafting lessons: the claimed invention omits the very quantitative margin architecture that the specification devotes FIGS. 10–11 and eight equations to describing, leaving the claims exposed to precisely this kind of generic‑combination § 103 attack.

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Where this memo relies on the full text of references A–E rather than their abstracts/claim excerpts, those points are marked provisional. I have not verified any of A–E line‑by‑line, and I have not identified, and do not assert the existence of, any prior art beyond the five references listed in this page's Patent Citations section.