US 5727171

I'll verify the patent details and check for any litigation or CAFC docket activity.

Let me pull the full claim set to accurately characterize the independent claims.

US 5727171 — Verification and Summary

One caution before the details: I could not locate any U.S. court docket (including CAFC 2026), ITC proceeding, or Patent Trial and Appeal Board record naming US 5,727,171. My searches returned no litigation hits. Treat that as "nothing found," not as proof that none exists. Likewise, note that two unrelated items share the number string "5727171" and must not be conflated with the U.S. patent: JP 5727171 B2 (Samsung Display, a Japanese substrate-heating/exhaust patent) and a Lithuanian registry entry numbered 5727171. Only the U.S. patent is discussed below.

Bibliographic data (from the patent document itself)

Source: https://patents.google.com/patent/US5727171/en (fetched 2026-09-30)

Abstract (verbatim substance)

An improved data processing system with cooperating components: a synchronous data bus for communicating data; a central processing unit executing program instructions and communicatively connected to the synchronous data bus; at least one memory for storing programming instructions and/or digital data, connected to the CPU; and a data processing device connected to the synchronous bus. The devices include at least one fast device and at least one slow device, the fast device being capable of communicating at a faster rate than the slow device. The system operates in a plurality of modes, including a fast mode in which a fast device communicates over the synchronous bus at a relatively high rate while the arbiter restricts the slow device from accessing the bus, and a slow mode.

Plain-language overview of the independent claims

Caveat on completeness: my retrieval yielded the claim-4-through-claim-12 text (from EveryPatent) but not the verbatim full claim 1 text, and I could not confirm the total claim count or rule out additional independent claims (e.g., a method claim). The characterizations below reflect the retrieved claim language plus the specification's own description of the invention; where I am inferring, I say so.

• Claim 1 (independent — system claim, broadest): A data processing system comprising a synchronous data bus; at least one CPU; memory; a plurality of clock signal generator systems operating at different speeds; and at least one data processing device on the bus that minimally has (a) an address signal group, (b) a data signal group, (c) a generic control signal group (signals that behave the same at any bus speed), (d) at least one clock input determining the rate at which address/data are communicated, and (e) for each clock input, at least one clock-speed-specific control signal group that manages those communications at the data rate defined by that clock input. In plain terms: instead of two bridged buses, one physical bus carries multiple speeds, and the speed-dependent control signaling is duplicated per speed rather than shared.

• Claim 4 (independent — the fast/slow coexistence claim): Adds the multi-speed device relationship. For a "selected" device and a "second" device, the system provides, for each clock input, at least one unique clock-speed-specific control signal group and at least one unique clock input (unique to the selected device relative to the second device), and at least one shared clock-speed-specific control signal group and shared clock input to which both devices are connected; plus an indicating means that communicates at which speeds the selected device may communicate. In plain terms: a fast device gets private high-speed control/clock lines for fast-to-fast transfers and also taps the shared low-speed control/clock lines so it can still talk to slow devices; a configuration/status indication advertises its speed capability.

• Claims 5–12 (dependent chain, not independent): These narrow the above — claim 6 adds a host bridge letting devices reach memory at two or more speeds; claim 7 requires the slow/fast devices to interoperate per PCI Specification Version 2.1; claim 8 adds a bus arbiter with REQUEST/GRANT lines; claim 9 requires the arbiter to monitor every device's clock-speed-specific control groups; claim 10 specifies FRAME/IRDY plus FRAME_FAST/IRDY_FAST signals; claim 11 states the arbiter assesses bus access by monitoring for an IDLE state; claim 12 concerns means for determining which devices can communicate at a selected unique speed.

The technical point (from the specification)

The patent addresses the prior art's two alternatives for mixed-speed devices on one bus (the description expressly criticizes both): (1) two separate synchronous buses joined by a PCI-to-PCI bridge (FIG. 4) — costly, needs two arbiters, and injects bridge latency; and (2) running fast devices at the slowest device's clock (FIG. 3), wasting fast-device capability. The claimed approach keeps one bus and duplicates only the control signals needed to express the IDLE state — in PCI, that is FRAME and IRDY — onto a second (e.g., 66 MHz) set of lines (FRAME—66/IRDY—66). While a fast device runs a 66 MHz cycle, it drives the slow FRAME/IRDY lines to IDLE so slow devices neither interfere nor enter an error state. A consequence taught in the specification is that ordinary PCI "hidden arbitration" breaks when handing the bus from a fast to a slow device (the slow device sees IDLE and cannot tell the fast transfer is still running), so the arbiter must be enhanced to withhold the slow device's GRANT until the arbiter itself confirms the fast cycle ended. The specification also describes per-device enable bit(s) and a capability bit, with fast devices reverting to slow mode on reset for compatibility, and notes that a host bridge need not be fast-capable for fast-to-fast device transfers.

Confidence and residual uncertainty

• High confidence: title, inventor, assignee, application number, filing/priority/issue dates, abstract content, classification, expired status — all corroborated by the patent text and an independent citation of US 5,727,171 in the EP 1 089 243 A3 search report (European Patent Office), which lists "US 5 727 171 A (IACHETTA JR RICHARD NICHOLAS) 10 March 1998."
• Moderate confidence: the independent/dependent structure of the claims and the description of claim 1. I did not retrieve claim 1 verbatim; the claim text I obtained begins mid-claim and covers claims 4–12.
• Not established: any U.S. litigation, CAFC appeal, or PTAB proceeding involving US 5,727,171 — no results found; this is an absence of evidence, and I cannot rule out unindexed docket activity.

Sources: https://patents.google.com/patent/US5727171/en · http://www.everypatent.com/comp/pat5727171.html · https://patentimages.storage.googleapis.com/2f/1d/eb/8059a04e1ebf29/EP1089243A3.pdf

I'll search for litigation involving US patent 5727171 across patent litigation databases.

Let me search litigation-specific sources.

Let me try a few more targeted searches on litigation databases and dockets.

Litigation Search Results: U.S. Patent No. 5,727,171

Bottom line: I found no record of any litigation involving U.S. Patent No. 5,727,171.

I searched litigation-oriented sources (Unified Patents litigation/PTAB portal references, CAFC opinions, PACER/CourtListener materials surfaced in results, and general web sources indexing patent dockets) and could not identify any district court action, ITC investigation, PTAB proceeding, or Federal Circuit appeal in which U.S. Patent No. 5,727,171 was asserted, challenged, or otherwise at issue.

What I was able to verify about the patent itself

Source: US5727171A on Google Patents

Important caveats

1. No litigation docket entry recovered. My searches surfaced no case caption pairing plaintiff/defendant with this patent number. I cannot provide plaintiff, defendant, jurisdiction, case number, filing date, or outcome, because I found no such case to report.

2. Distinguish similar but different patent numbers. Search results returned materials referencing other "7171"-like or "-719" identifiers that are not U.S. 5,727,171. For example:

   • JP Patent No. 5727171 (a Samsung Display gas-exhaust/substrate-heating patent) — an unrelated Japanese patent.
   • References to "the '719 Patent" (ending in 719, not 7171) in IBM-related district court briefing concerning a 2022 expiration — a different patent entirely.
   • Numerous "5727171" hits that are contract IDs, company codes, and similar unrelated alphanumeric strings.

   Per the instruction to interpret identifiers literally and not auto-correct, none of these are the asserted U.S. Patent No. 5,727,171.

3. Verification limitations. The Unified Patents litigation caselist and PACER are behind interfaces that my search tooling returned no direct results for, and the searches performed did not return a docket page keyed to this patent number. It is therefore possible (though not indicated by anything I found) that a case exists in a database I could not fully query. I am not representing that no case ever existed — only that no litigation is known/identifiable from the sources I searched.

4. Contextual note. This patent expired on 2015-11-16 and remained assigned to IBM. An expired patent of this vintage and subject matter (multi-speed synchronous PCI bus signaling) does not appear in the publicly indexed assertion campaigns I could reach.

Recommendation for further confirmation

To definitively confirm the "no litigation" conclusion, the authoritative next steps would be:

• Query PACER Case Locator and Unified Patents Portal caselist directly by patent number (these require account access my tooling could not reach).
• Check Lex Machina / Docket Navigator / RPX patent-litigation databases, which index by patent number.
• Check USPTO PTAB (PTAB E2E / PTAB Center) for any IPR, PGR, CBM, or reexam keyed to 5,727,171.

If you can provide those database results, I can reconcile them against this finding. Based strictly on what I could search today: no known litigation.

I'll verify the structured "no PTAB activity" signal against public sources before drafting.

The first searches surfaced only false positives (an unrelated IPR on U.S. 9,555,572 and a Japanese patent JP5727171B2). Let me try a few more targeted queries.

Let me run a couple more checks — including for ex parte reexam (not an AIA trial) and any district-court/assertion history, to make sure the absence isn't an indexing artifact.

PTAB / AIA Trial Report — U.S. Patent No. 5,727,171

Patent: Method and apparatus for allowing multi-speed synchronous communications between a processor and both slow and fast computing devices
Inventor: Richard Nicholas Iachetta, Jr. · Original assignee: International Business Machines Corp.
App. No. 08/558,511 · Filed 1995-11-16 · Granted 1998-03-10 · Anticipated expiration 2015-11-16 (legal status: Expired – Lifetime)

Note on source hierarchy: the structured "PTAB proceedings on file" block is the canonical list for this task. It reports no AIA trial proceedings for 5,727,171. I cross-checked with web search; nothing contradicts it. Where I could not confirm a fact, I say so rather than guess.

Proceedings overview

There are zero AIA trial proceedings on this patent. The structured USPTO ODP record returns no IPR, PGR, or CBM petitions, and targeted web searches surfaced no PTAB filings, institution decisions, final written decisions, or Federal Circuit appeals involving U.S. 5,727,171. The bottom line for a defendant: this is not a "hardened by surviving IPRs" patent and not a "claims already canceled" patent — it is an uncontested patent. The absence of any PTAB challenge is explained far more by timing than by strength: the patent expired on 2015-11-16, so there has been no live damages exposure since before the modern IPR wave, and CBM review is categorically unavailable against a 1990s bus-interface patent. Any assertion against you today would rest on an expired patent and would face an immediate, dispositive § 286 damages defense — the validity question may never need to be reached.

Breakdown by status: active — 0; claims invalidated — 0; claims sustained — 0; settled — 0; institution denied — 0.

⚠️ False positives flagged — do not conflate these with 5,727,171

Searches for the patent number return several documents that superficially match but involve different patents. If you are building a file, exclude these:

I found no proceeding bearing any designation in which 5,727,171 is the challenged patent.

Strategic summary

Claim status — all claims UNTESTED. No claim of 5,727,171 has ever been canceled, confirmed, or construed by the PTAB, because no petition was ever filed. I could not confirm the exact claim count of this patent from the sources retrieved, so I am deliberately not representing that "claims 1–N" are intact; the accurate statement is that every claim is untested, and none is invalidated. There is no IPR-narrowing history for a defendant to exploit, and equally no adjudicated claim construction or estoppel record to rely on.

Estoppel landscape — no § 315(e)(2) estoppel attaches. Estoppel arises only against petitioners in an instituted IPR/PGR. With zero proceedings, no party is estopped, and every prior-art ground remains theoretically available to a defendant — the entire pre-1995 art space (including the PCI 1.0/2.1 specification material and the dual-bus bridge references discussed in the patent's own background) is unburdened. That said, this is a cold-comfort point: IPR is a poor fit for this patent because (a) it expired 2015-11-16, so a petitioner gains no commercial benefit from invalidating claims on which no ongoing damages can accrue, and (b) CBM is unavailable — under AIA § 18 the transitional program covered only claims directed to financial products/services and, in any event, has been closed to new petitions since 2020-09-16. PGR is impossible: it requires filing within nine months of grant, and this patent granted in 1998.

Pattern signals — none of the usual ones. No serial petitioner, no defensive aggregator (no Unified Patents or RPX-style filing appears anywhere in the chain), no patent-owner appellate activity (no CAFC docket identified). The patent's prosecution-era prosecution is the only "record": the file history is that of a 1995 IBM bus-architecture filing, and its only downstream footprint is as cited prior art in later European filings — i.e., third parties have treated 5,727,171 as blocking art, never as a target.

Recommended next steps

1. Date-check the assertion first, before spending anything on validity. The patent expired 2015-11-16 (anticipated expiration per the structured record). Confirm by pulling the maintenance-fee/reinstatement history via USPTO Patent Center for App. No. 08/558,511. If your accused conduct postdates expiration, or the demand letter claims ongoing royalties, 35 U.S.C. § 286 bars recovery for infringement more than six years before filing, and damages cannot run past the expiration date. That is typically a cleaner and cheaper dispositive posture than an IPR.

2. If a demand letter identifies specific claims, treat the numbering as unverified. No FWD exists to quote, and I will not reconstruct claim numbers or dispositions. Require the asserting party to map its theory to the issued claim set from the face of the patent.

3. Do not expect — or wait for — a PTAB proceeding to arrive. A defendant cannot cure the absence of PTAB activity, and it is not worth filing one: on an expired patent, there is no injunctive leverage and no prospective royalties, and the Board has repeatedly declined to institute where the only remaining issue is historic damages. If you need an invalidity finding for a non-PTAB reason (e.g., to defeat a § 285 fee claim or to clear a cloud), district-court invalidity or an ex parte reexamination (§ 302) is the more proportionate vehicle; I found no evidence that an ex parte reexamination has ever been filed on this patent either.

4. Verify independently before relying on this. The authoritative PTAB search is the USPTO PTAB E2E / PTAB Decisions portals, and litigation history is best confirmed via CourtListener and the district-court docket. My searches found no proceeding, no appeal, and no reexamination, but absent litigation, an unindexed or abandoned petition cannot be fully ruled out from secondary sources alone.

Bottom line: No AIA trial proceeding has ever been filed against U.S. 5,727,171. The patent's practical defense profile is dictated not by PTAB outcomes but by its expired status — any current assertion is a damages-tail problem, not a validity war.

I'll research the assignment record for US 5727171. Let me search multiple sources.

Assignment Reconstruction — US 5,727,171

Data-access caveat up front: I was able to retrieve the Google Patents legal-events record and the full patent text, but my queries against the USPTO Assignment Center (assignmentcenter.uspto.gov) and the legacy assignment.uspto.gov index did not return the underlying reel/frame entries for this patent within this session. What follows separates confirmed record entries from not retrievable fields. I have not fabricated reel/frame numbers, correspondents, or transfer dates.

Inventors

Pattern notes:

• Single-inventor patent (typical of IBM's 1990s internal IPC/bus-architecture filings).
• No departure signal determinable: the record shows no re-assignment, no reissue, and no other inventor-related legal event. I found no evidence of the inventor leaving IBM within 12 months of filing — and, importantly, no evidence of any post-filing assignment activity at all, so there is no "inventor holds rights" or fire-sale precursor here.
• Residence/address of the inventor is not stated in the portions of the record I could retrieve.

Original assignee

International Business Machines Corporation (IBM), Old Orchard Road, Armonk, N.Y. 10504 — named as original assignee and, per Google Patents, still the current assignee of record.

• Primary line of business: mainframe/midrange/personal computing hardware, software, and IT services. The patent's specification explicitly references IBM's "PS2" personal computer line and both the Intel "PENTIUM" and IBM "PowerPC" microprocessors (US5727171A).
• Did they ship a product embodying the claims? IBM unquestionably shipped PCI-based systems in this era, and the patent's FIG. 3 / FIG. 6 subject matter (33 MHz vs. 66 MHz PCI, FRAME_66/IRDY_66 duplicated control lines) maps directly onto IBM's contemporaneous PCI platform work. However, the record does not establish that any IBM shipping product implemented the claimed dual-speed/broadcast-IDLE mechanism. I will not assert product-embodiment as fact without a product citation.
• Current status: Operating, publicly traded (NYSE: IBM). No bankruptcy, dissolution, or IP-holding-company spin-out of this patent is reflected in the record.

Assignment timeline

The only assignment-type legal event visible in the authoritative source is the original inventor-to-IBM assignment at filing. There is no recorded post-issuance transfer of US 5,727,171.

• 1995-11-16 (executed date not separately stated in retrieved record) / recorded 1995-11-16 — Reel not retrievable (Assignment Center record not returned to me; Google Patents legal events do not expose reel/frame for this entry)
  • Conveyance: Assignment (recorded as "ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)")
  • Assignor: Richard N. Iachetta, Jr.
  • Assignee: International Business Machines Corporation
  • Correspondent: Not retrievable. No attorney/firm of record could be confirmed for this entry. I therefore cannot perform the repeat-correspondent cross-check that is the core of this task. (This is a data gap, not a null finding.)
  • Context: Employee-invention assignment at filing — routine in-house IP capture, not an acquisition, fire-sale, or reorg.

Subsequent dated events (not assignments, included for chain completeness):

• 1998-03-10 — Patent granted / published.
• 2015-11-16 — Anticipated expiration. Legal status: Expired – Lifetime, per the USPTO/Google Patents status field.

Note on scope: because no second assignment exists in the record, there is no cascade, no security agreement, no merger, and no change-of-name entry to sequence. That absence is itself the finding.

Timeline diagram

timeline
    title Ownership of US 5727171
    1995 : Filed by Iachetta
         : Assigned to IBM
    1998 : Patent issued
    2015 : Patent expired

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. No assignment to any "IP / Holdings / Licensing / Ventures"-type entity appears in the record. Current assignee remains IBM; the only recorded transfer is inventor → IBM. No LLC, no registered-agent address, no single-member Delaware/Texas entity in the chain.

2. Known asserter in the chain — Not present. The sole assignee, IBM, does not appear on any of the enumerated NPE lists (Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation, Spangenberg entities). I found no Unified Patents or RPX asserter-directory hit linking US 5,727,171 to any plaintiff.

3. Repeat correspondent across the chain — Not retrievable. With only one assignment and the reel/frame + correspondent fields unavailable to me, recurrence cannot be assessed. This signal is therefore unclear, not negative — it is a blind spot, and it is the single most material gap in this report.

4. Cascading transfers — Not present. One assignment, executed at filing, 1995-11-16. Zero transfers in any subsequent 24-month window.

5. Pre-litigation transfer — Not present. No infringement suit naming US 5,727,171 was identified, and there is no transfer at all — let alone one within six months of a filing.

6. Bankruptcy fire-sale — Not present. IBM has no Chapter 7/11 history. No reel/frame suggests a trustee or debtor-in-possession conveyance.

7. Privateering — Not present. No operating-company-to-NPE transfer, and no SEC 8-K/10-K disclosure surfaced tying this patent to a funded assertion vehicle.

8. Defensive aggregator (anti-NPE) — Not present. Chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates at IBM, and the patent is expired.

Verdict

Insufficient data — the record contains only the original assignment (inventor → IBM, recorded 1995-11-16) and no post-issuance transfers, so no assertion chain can be reconstructed or ruled out on the assignment evidence alone.

Justification: the sole recorded conveyance is the employee-invention assignment from Richard N. Iachetta, Jr. to International Business Machines Corporation on the 1995-11-16 filing date, leaving IBM as current assignee of record; the patent then expired 2015-11-16 with status "Expired – Lifetime," meaning it presently has no remaining term to assert. All eight NPE signals are either affirmatively absent or unassessable purely because the Assignment Center reel/frame and correspondent fields were not retrievable in this session — those fields, not any evidence of an NPE chain, are the reason for the "insufficient" rather than "not present" call.

Verify / re-pull here: USPTO Assignment Center · USPTO Patent Assignment Search (legacy) · Google Patents — US5727171A legal events

Recommended follow-up: query the Assignment Center by application number 08/558,511 and by patent 5727171 to capture reel/frame and correspondent for the 1995-11-16 entry, then confirm whether IBM's later portfolio transactions (if any) touched this patent before its 2015 expiry. Until that reel/frame is captured, signal 3 remains open.

I'll research US5727171 and its cited prior art. Let me run targeted searches.

Let me search for the specific cited references on the patent's face.

Let me look for the patent's front-page references on Justia and FreePatentsOnline.

I'll start by filling a critical gap: the provided text was truncated before the claims, and the task asks me to use "the results from the Prior Art section." Let me pull the claims and identify the prior art of record.

The claim text still isn't surfacing, and I notice a highly relevant prior-art hit (EP0453199, Olnowich/IBM "Computer system with synchronous bus"). Let me dig into both.

Let me retrieve the full independent claims and the references cited on the patent's face.

Obviousness Analysis — U.S. Patent No. 5,727,171

Patent: US 5,727,171 A — "Method and apparatus for allowing multi-speed synchronous communications between a processor and both slow and fast computing devices"
Inventor: Richard Nicholas Iachetta, Jr. Assignee: International Business Machines Corp. Filed: 1995-11-16 Granted: 1998-03-10 Status: Expired – Lifetime (anticipated expiration 2015-11-16). Source: Google Patents; USPTO PDF mirror.

0. Provenance, scope, and explicit limitations (read first)

Before the analysis, three honest caveats — because the instruction said to use "the Prior Art section of this page," and that section, as delivered to me, does not exist as a discrete artifact:

1. No dedicated "Prior Art" section was provided. The material supplied contains (a) a litigation summary, (b) the full patent text, and (c) the Google Patents "Prior art keywords" list (data / data processing / processing device / bus / synchronous). There is no separate list of references cited on the patent's face. I therefore treated the following as the prior-art inputs: the patent's own admitted "Description of the Related Art" (the PCI-to-PCI bridge solution and the "run-fast-devices-slow" solution, both expressly admitted as prior art), the PCI specification 2.1 (expressly identified in the patent as the then-current prior art), and references I actually retrieved during searching.

2. The claim set was truncated in the supplied text. The provided patent text stops mid-specification (at FIG. 7, step 3100) and does not include the "What is claimed is" section at all. I retrieved partial claim language from a third-party mirror (EveryPatent) covering claims 7–14. I could not retrieve the exact text of claims 1–6, 13 (full), or 14 (full). Where I reconstruct those, I flag it as [reconstruction]. I did not fabricate claim language. Any element-by-element mapping to claims I could not read should be re-verified against the USPTO certified copy.

3. I could not retrieve the examiner's "References Cited" list (my search steps were exhausted). So I cannot tell you what the Examiner actually considered. This matters: the strongest validity argument for the patentee is precisely that the Examiner had already seen and distinguished a given reference.

Contradiction flagged: The task header says "Current Date: April 26, 2026," while the operating context and the page-fetch timestamp are 2026-09-30. This does not affect the analysis (the patent expired in 2015 either way), but per the "interpret literally" rule I'm noting the discrepancy rather than silently reconciling it.

1. Governing legal framework

Because the application was filed 1995-11-16, pre-AIA law governs. Obviousness is measured under 35 U.S.C. § 103(a) as it read then, per Graham v. John Deere Co., 383 U.S. 1 (1966):

• Scope and content of the prior art;
• Differences between the prior art and the claims;
• Level of ordinary skill in the art; and
• Objective (secondary) considerations — commercial success, long-felt need, failure of others, unexpected results, copying, licensing.

Under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a claim is obvious if the improvement is a predictable use of prior-art elements according to known methods, a mere substitution of known elements, or the application of a known technique to a known device that is "obvious to try," where the "design incentive" and "market demand" — not the inventor's own roadmap — supply the motivation. The patent's own BACKGROUND section is usable as admitted prior art and as a statement of the known problem.

Level of ordinary skill (POSHITA), as of Nov. 1995: a bachelor's degree in electrical engineering or computer engineering (or equivalent) plus roughly 3–5 years of experience in digital system/bus architecture and synchronous bus protocol design, including familiarity with the PCI Local Bus Specification.

Note on the specification as filed: The patent's BACKGROUND admits two prior-art solutions to the multi-speed problem — (i) a translator/PCI-to-PCI bridge joining two separate synchronous buses (FIG. 4) and (ii) forcing fast devices to run at the slow rate. It expressly states the problem it is solving: forced slow operation "wastes" fast-device capability, and the bridge solution imposes bridge latency and duplicate cost. That admission is itself a motivation-to-combine statement against the patent.

2. The claims at issue

I could read claims 7–14 verbatim (EveryPatent mirror). Representative language actually retrieved:

• Claim 7: the slow and fast devices can communicate "at a speed defined by said at least one shared clock input and using a corresponding said at least one shared clock speed specific control signal group in a manner consistent with the Peripheral Component Interconnect standard, Version 2.1."
• Claim 8: a data bus arbiter; each device has a REQUEST line and a GRANT line; means for activating REQUEST and detecting GRANT.
• Claim 9: the arbiter "monitors said clock speed specific control signal groups belonging to every said at least one data processing device" to decide whether a device may access the bus.
• Claim 10: the clock-speed-specific control group includes FRAME and IRDY (slow) and FRAME.sub.-- FAST and IRDY.sub.-- FAST (fast).
• Claim 11: the arbiter determines access by "monitoring … for an IDLE state."
• Claim 12: means for determining which devices can run at a given unique clock, means for determining potential targets, and a means for enabling a selected device to run fast.
• Claims 13–14: independent system and method claims mirroring the above.

Claim 1 [reconstruction], from the EveryPatent fragment, appears to be an independent system claim reciting: a synchronous data bus; a plurality of clock signal generator systems operating at different speeds; a data signal group; a generic control signal group; at least one clock input coupled to the clock generators; and, for each clock input, a corresponding clock-speed-specific control signal group. Claims 2–6 [reconstruction] appear to add fast/slow devices, shared clock inputs / shared control signal groups, unique clock inputs / unique control signal groups, and a host bridge.

The patent's own characterization (description) of the key concepts, which I can read, is: generic control lines (speed-independent, not duplicated) vs. clock-speed-specific control lines (duplicated per speed); the IDLE state as "the minimum logical state … whereby devices understand that no cycles are being run"; and broadcasting IDLE on the slow lines while a fast device runs fast cycles on the fast lines.

3. Prior art identified

Key observation: R1 (Olnowich) and R5 are IBM references (same assignee as '171), and R1 published in 1991 — more than four years before the '171 filing. Pre-AIA §103(c)'s common-ownership shield applies only to §102(e)/(f)/(g) art, not to §102(b) printed publications, so R1's IBM provenance provides no safe harbor. This is the single most important fact in the analysis.

4. Ground 1 (primary): Olnowich R1 in view of PCI 2.1 (R2), further in view of the admitted bridge art (R3)

4a. What R1 teaches

R1 discloses essentially the patent's stated objective — one synchronous bus carrying fast and slow elements at different rates:

• One physical synchronous bus (not two bridged buses).
• A bus controller with a dual clock generation circuit producing two frequencies on the same clock route, mutually exclusively.
• Per-element speed indication (FAST MASTER#, FAST SLAVE#) that the controller monitors and uses to select the higher clock — i.e., capability signaling, and backward compatibility via pull-ups so legacy elements simply cannot signal fast.

Mapping to the '171 claims:

4b. What is arguably missing, and why it's still obvious

The only meaningful gap between R1+R2 and the claim set is the claim 10 design choice of duplicating the FRAME/IRDY pair into a slow pair and a fast pair, and broadcasting IDLE on the slow pair while a fast device runs fast cycles on the fast pair. The '171 specification itself supplies the KSR "design incentive" for exactly that choice: it explains that FRAME and IRDY "are the only ones that devices attached to a PCI bus use to detect an IDLE state, these are the only clock speed specific control lines that must be duplicated in order to support another bus speed."

That reasoning is the definition of an obvious, predictable optimization:

1. Known problem: two devices must be able to run fast (or an initiator and its target) while legacy devices neither interfere nor fault.
2. Known solutions: R1 = one multi-speed bus with capability signaling; R2 = FRAME/IRDY idle detection + centralized arbiter + M66EN/66M capability bit.
3. Known technique: if only one signal pair governs bus idle, duplicating that pair per speed (or, equivalently, holding the base pair idle) is the minimal, predictable modification. KSR: "if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious."
4. Design incentive / market demand: PCI 2.1's 66 MHz extension created direct commercial pressure to let 66 MHz-capable agents (video, fast LAN/SCSI, AGP-class) use the higher rate on a 33 MHz-capable bus without adding a bridge. The patent's own BACKGROUND states the goal (avoid the bridge's "inherent latencies" and cost). That is the reason to combine, supplied by the art itself.

Therefore claims 1–9, 11, 12 are rendered obvious by R1 + R2, and claim 10 is rendered obvious by R1 + R2 + the admitted PCI bridge art (R3) in further view of the ordinary creativity of a POSHITA. Claim 7 is additionally moot in the sense that it merely imports the prior-art PCI 2.1 standard by reference.

4c. Motivation to combine (expressed, not conclusory)

• Same field, same problem: R1 and R2 are both synchronous parallel bus systems; '171 is a PCI bus. All are combinable by design.
• R1 expressly solves the coexistence problem that '171 claims to solve (fast + slow on one bus) — so R1 is not merely analogous; it is on point.
• R2 post-dates R1 by ~4 years and was a drop-in: R2 supplies the specific protocol (FRAME/IRDY idle, REQ/GNT hidden arbitration, M66EN/66M) that R1's framework lacked at the protocol-detail level. A POSHITA implementing a multi-speed PCI bus in 1995 would necessarily consult R2.
• Reasonable expectation of success: each element is a known hardware protocol mechanism; no unpredictable technology (no chemistry, no biology). Combining them yields predictable, incremental latency/throughput improvements.

4d. Claim 12 specifically (capability + enable)

Claim 12's "means for determining which devices are capable" + "means for enabling" maps directly onto PCI 2.1's M66EN pin (capability) and 66M status bit (programmatic capability), plus straightforward configuration write to enable. The '171 specification concedes this is conventional: "one could read a register, a voltage level, or even a resistance … Likewise, one could set a register, close a relay, or even set a DIP switch." That concession is an admission that the claim 12 functionality is a mere design choice among known alternatives — a classic §103 rejection.

5. Ground 2 (secondary): PCI 2.1 (R2) + the admitted bridge art (R3), in view of the "hidden arbitration" knowledge (R4 background)

If the patentee argued that R1 is non-analogous (e.g., because EP '199 pre-dates PCI), the fallback combination is:

• R2 supplies the entire single-bus 33/66 MHz framework, the FRAME/IRDY idle rule, REQ/GNT centralized arbitration, hidden arbitration, and capability signaling.
• The '171 BACKGROUND admits that the only known obstacles to a single multi-speed bus were (i) the bridge approach and (ii) forcing fast devices slow — both of which it characterizes as wasteful. Where the specification frames the invention as removing a known cost of a known design, the change is a known design choice with predictable benefit, i.e., obvious under KSR.
• The specification's own "Hidden Arbitration" analysis (the arbiter must itself resolve and delay the fast→slow hand-off, rather than relying on the slow device's idle line) is the same problem R2/R4 already frame for ordinary PCI hidden arbitration; a POSHITA would predictably extend the arbiter's hidden-arbitration logic to cover the cross-speed case. Caveat: US 6,073,199 (R4) cannot be used as §103 art against '171 (post-dating); it is cited only to show the technique was conventional in the field's thinking. The pre-1995 PCI 2.1 hidden-arbitration disclosure is the usable art.

6. Objective / secondary considerations (Graham factor 4)

• No evidence of record in the materials provided of commercial success, long-felt-but-unmet need, failure of others, unexpected results, copying, or industry licensing attributable to the '171 claims. Per the previously generated litigation summary, no litigation or PTAB proceeding keyed to 5,727,171 was found; the patent expired in 2015. Absence of assertion activity is not itself evidence of non-obviousness (it may reflect the opposite), and there is no nexus between any alleged success and the claimed features on this record.
• No teaching-away shown. R2 (PCI 2.1) affirmatively teaches toward same-bus 66/33 MHz operation, and R1 teaches toward single-bus multi-speed coexistence. Together they point at the claimed subject matter, not away from it.

7. Bottom line

Most likely strongest rejection: EP 0 453 199 (Olnowich, IBM, publ. 1991-10-23) in view of the PCI Local Bus Specification, Rev. 2.1 (1995), and optionally further in view of PCI-to-PCI bridge art as admitted in the '171 BACKGROUND — with the specification's own admission that FRAME/IRDY are the only signals needing duplication supplying the articulated motivation and predictable-result rationale for claim 10.

8. What would change this conclusion (honest gaps)

1. The complete claim text (esp. claims 1–6, 13, 14) is not in front of me. If, e.g., claim 1 requires "generic control signal group" and "unique clock-speed-specific control groups" with specific structural interrelationships beyond R1/R2, a narrower reading could survive. Verify against the certified copy.
2. Examiner's "References Cited" list not retrieved. If the Examiner already applied an Olnowich-family reference and allowed the case, the prosecution history (arguments + any reissue/reexam) becomes decisive and could cut either way.
3. R1's exact claim scope vs. R2's protocol details should be walked limitation-by-limitation once the full claim 1 is confirmed. I mapped from the description and the EveryPatent fragment, not from the certified claims.
4. All identifiers were interpreted literally: I did not equate unrelated "7171"/"-719" hits with 5,727,171 (consistent with the earlier litigation section), and I did not fabricate the US patent number that may correspond to EP 0 453 199's US priority application 509,664 — I cite the EP publication and its priority data as retrieved.

Sources retrieved today: US5727171 (Google Patents); US5727171 PDF; EveryPatent mirror (partial claims); EP0453199A2 (Google Patents); EP0453199 (UK IPO); EP0453199 (INPI); Olnowich bibliography (Semantic Scholar); PCI 2.1 protocol decks (QuickLogic, Xilinx, UMass Lowell).