Invalidity dossier

US 5630086

Apparatus systems and methods for controlling electronic memories

Current assignee: Hewlett Packard Development Co LP

Added 9/24/2026, 1:39:45 AM

At a glanceNo PTAB challengesNo litigation on file

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Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

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Patent Overview: US 5,630,086

Title: Apparatus, systems and methods for controlling electronic memories

Patent number: US 5,630,086 A
Application number: US 08/161,937
Inventors: Bryan D. Marietta; Douglas A. Oppedahl
Original assignee: Hewlett Packard Co (application filed 1993-12-03; assignment to Convex Computer Corporation recorded same date; later assignments to Hewlett-Packard and Hewlett-Packard Development Company, L.P., per the source)
Priority/filing date: 1993-12-03
Publication (grant) date: 1997-05-13
Status as listed: Expired – Lifetime; anticipated expiration 2014-05-13

Purpose. The patent addresses control of DRAM memory systems, where adjusting for differences in device signal-to-signal timing to maximize performance was a major problem. Prior timing was varied using control-signal-generator signals with discrete gates and delay lines; changing timing required new hardware, and the number of control signals through connectors became excessive, causing electrical noise, added complexity and cost, and board-space consumption.

Plain-language scope. Memory control circuitry generates a timed sequence of Gray code values and controls how long each value is asserted. The sequence is transmitted through a connector to decoder circuitry, which decodes each value and produces at least one memory control signal. Because Gray code states change one bit at a time, fewer switching signals cross the connector, reducing ground voltage drift and noise. Embodiments cover reducing signals through a connector between first and second circuits, a memory system with control circuitry and memory circuitry (including a memory operation type control signal and a timed sequence of memory control signals), and a corresponding method. A stored program can be replaced or modified to vary control-signal timing, allowing memory devices with differing performance parameters to be designed in. The excerpt describes a processing system with parallel CPUs, a crossbar, parallel memory units, and a service processor.

Source: https://patents.google.com/patent/US5630086/en

What the excerpt does not establish. The supplied text is an excerpt: claim language, the full written description, drawing details, and the complete field are not reproduced, so specific claim scope cannot be quoted. It does not establish validity, enforceability, litigation, prior-art comparisons, or the accuracy of listed assignees and legal status (the source itself labels status/assignees as assumptions).

Generated 10/1/2026, 9:31:15 PM

Cases on file (0)

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Litigation summary

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Proceedings on file (0)

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AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.

No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.

PTAB challenges

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Assignment history

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Prior art

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Obviousness

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Extensions

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Derivative works

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