Invalidity dossier
US 5557209
Identification of pin-open faults by capacitive coupling through the integrated circuit package
Current assignee: Agilent Technologies Inc
Added 9/23/2026, 7:31:00 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 5,557,209
Title: Identification of pin-open faults by capacitive coupling through the integrated circuit package
Patent number: US 5,557,209 A
Application number: US 08/400,787
Inventor(s): David T. Crook; Kevin W. Keirn; Ugur Cilingiroglu
Original assignee: Hewlett-Packard Co. (current assignee listed as Agilent Technologies Inc.)
Priority date: 1990-12-20
Filing date: 1995-03-07
Publication/grant date: 1996-09-17
Legal status (as listed): Expired – Lifetime; anticipated expiration 2013-09-17
Purpose. The invention generally relates to measuring and testing devices, particularly in-circuit testing of connections between integrated circuits (or other components) and a circuit assembly, such as a printed circuit board. A primary object is to provide improved apparatus and methods for testing the integrity of a connection between a pin of an electrical component and a printed circuit board or circuit assembly. The background notes that functional testing, in-circuit testing using a "bed of nails" fixture, and manufacturing defect analyzers each have limitations, and that the invention is predominantly directed to in-circuit testing of component-to-board connections.
Plain-language scope. The disclosed system measures the integrity of an electrical contact between a component connection pin and a circuit assembly. It includes: means for supplying an electrical signal; measuring means for measuring a parameter indicative of a capacitance associated with the pin-to-board connection; a conductive electrode connected to the measuring means and having a surface placed in proximity to a surface of the connection pin; an electrical connection from the signal-supplying means output to the pin under test; and an electrical connection between at least one other node of the circuit assembly and the common signal return. Preferred embodiments include error-indicating means when the measured parameter is outside predetermined limits; a measurement below a low limit indicates an open pin, while measurements exceeding a high limit indicate other faults such as an open ground or power pin. The measuring means may measure current or voltage between the electrode and common signal return, and the signal-supplying and measuring connections may be interchanged. Current-measuring embodiments may hold the measurement connection to a virtual ground, implemented with conventional operational amplifier circuitry.
Source: https://patents.google.com/patent/US5557209/en
What the excerpt does not establish. The supplied text is excerpted and omits the full claims, detailed description, and drawings. It does not establish the complete claim scope, the full list of cited prior art, prosecution history, or the accuracy of the listed assignees, legal status, or priority assumptions (which the source itself labels as assumptions, not legal conclusions).
Generated 10/1/2026, 9:41:59 PM
Cases on file (0)
Specific litigation cases in our database that name US patent 5557209. The free-form analysis below may also discuss cases beyond this list.
No cases on file mention this patent. Upload a CSV or add a case manually in Admin → Manage litigation cases.
Litigation summary
Past and pending lawsuits — plaintiffs, defendants, jurisdictions, outcomes, and notable rulings.
Proceedings on file (0)
All PTAB activity →AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.
No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.