Invalidity dossier
US 5479645
Portable computer capable of switching CPU clocks
Current assignee: Toshiba Corp
Added 9/23/2026, 9:20:39 PM
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Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 5,479,645 A
Title: Portable computer capable of switching CPU clocks
Assignee: Toshiba Corp (original assignee; assignment recorded to Kabushiki Kaisha Toshiba, assignors Makoto Sakai and Makoto Arai)
Key dates: Priority date 1991‑10‑11; application US07/958,030 filed 1992‑10‑07; granted/publication date 1995‑12‑26. Legal status listed as "Expired – Fee Related," with anticipated expiration 2012‑12‑26 (status presented as an assumption, not a legal conclusion).
Purpose: To provide a mechanism letting a user arbitrarily switch clock frequencies generated inside a one‑chip microprocessor that generates operation clocks by internally frequency‑dividing an externally supplied fundamental clock (EFI). The specification identifies a commercially available example, the Intel 386SL, and notes that prior arrangements (e.g., CPU clock register, de‑Turbo pin/register) did not let the user switch clock frequencies as needed. A further object is a portable computer using this mechanism.
Plain‑language scope: The portable computer includes a one‑chip microprocessor with a clock‑generating section incorporating a clock frequency setting register; a clock is produced by frequency‑dividing EFI according to the register value. Input means (keyboard) supplies data designating a frequency switching operation; detecting means detects that data and changes the register value, thereby changing the operation clock frequency. Embodiments read a setup menu (high‑speed, normal, low‑speed mode sets combining EFI, EFI/2, EFI/4, EFI/8), store selections in a battery‑backed backup RAM, use BIOS‑ROM defaults, and detect switching keystrokes (Fn + PgUp / Fn + PgDn) via a keyboard controller, D flip‑flops, NOR/AND gates, an I/O register, and a system management interrupt (SMI) routine. Values are also set in slow CPU clock and idle MCP clock registers, the latter governing a math coprocessor clock; the de‑Turbo pin is held at a level selecting the CPU clock register.
Source: https://patents.google.com/patent/US5479645/en
What the excerpt does not establish: It does not state the number or exact wording of claims, the full claim scope, complete figure content, or omitted text; it does not address validity, enforceability, litigation, or prior‑art comparisons, and the listed legal status and assignee data are expressly assumptions per the source.
Generated 10/1/2026, 9:34:21 PM
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Litigation summary
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PTAB challenges
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Assignment history
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Prior art
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Obviousness
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Extensions
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Derivative works
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