US 12271636

Here is a concise summary of US Patent 12271636:

US Patent 12271636 Summary

• Title: Analytics, algorithm architecture, and data processing system and method
• Assignee: Fermat International Inc.
• Inventors: Robert Bismuth, Mike Stengle
• Filing Date: November 6, 2023 (Application No. US18/502,275)
• Issue Date: April 8, 2025 (Publication of US12271636B2)
• Abstract: The patent describes a system and method utilizing a distributed hardware architecture, possibly with a specific data structure, for data processing and analytics. It details a compute node that can operate independently of a host computer to manage and execute data processing. Furthermore, it discloses a unique algorithm architecture and processing system and method, which can be implemented with various node types and data structures for diverse data processing and analytics applications.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim outlines a method for reformatting data. It involves taking an initial block of data, where each original record has various field types, and transforming it. The transformation process creates new records, with each new record containing only fields of a single type. These new records are then indexed and stored in memory. Essentially, it describes converting data from a row-oriented format to a column-oriented format where each "column" (now a new record) holds data of a uniform type.
• Claim 10: This claim details a method for executing data processing using a specialized compute node. This node works in conjunction with a host computer but performs operations independently. It includes a programmable logic component (e.g., an FPGA) that executes data processing tasks with a first memory, and a data mover that facilitates data transfer between the programmable logic and a second memory. A key feature is that this programmable logic can reformat incoming data (similar to Claim 1), and then transfers this reformatted data between itself and the first memory using multiple communication channels for efficiency.
• Claim 15: This claim describes a data processing system designed to operate with a host computer. The system features a router module that connects to the host and to a compute node. The compute node itself contains: a communication link to the router, a data store for processing records, a programmable logic component for executing operations with the data store, a node memory for supporting the programmable logic and communications, a data mover for internal data transfers, and a storage interface. The storage interface is notable for using multiple communication channels to move data efficiently between the programmable logic component and the data store.
• Claim 18: This claim describes a distributed data processing system. It comprises a "management node" connected to a host computer. Attached to the management node is a "memory-supported compute node," which includes its own data store, programmable logic, and local memory. Critically, a pipeline of one or more "additional compute nodes" is serially connected to this memory-supported node. Each of these additional nodes has its own memory and programmable logic, allowing them to process data received sequentially from the preceding node in the pipeline, thereby enabling a multi-stage processing workflow.
• Claim 24: This claim defines a compute node itself for use in a data processing system. This node connects to a host computer, either directly or indirectly through another node in a processing pipeline. The node integrates: a data store, a programmable logic component for executing operations with the data store, a node memory to support the programmable logic and facilitate communication with adjacent nodes, a data mover for internal data transfers, and a storage interface component. A significant aspect is that the storage interface component uses multiple communication channels to transfer data between the programmable logic and the data store, enhancing data throughput.

USPTO and CAFC 2026 Dockets Search:

A search for US patent 12271636 indicates that the patent is Active.

Regarding litigation, the patent family has litigation filed. Specifically, a US case was filed in the Texas Western District Court. The Unified Patents Litigation Data, licensed under a Creative Commons Attribution 4.0 International License, also confirms this.

No specific CAFC 2026 dockets were found directly linked to patent number 12271636 in the immediate search results, but the existing district court litigation suggests that appellate activity could potentially occur in the future.US Patent 12271636, titled "Analytics, algorithm architecture, and data processing system and method," was invented by Robert Bismuth and Mike Stengle. It is currently assigned to Fermat International Inc. The patent application (US18/502,275) was filed on November 6, 2023, and the patent was issued on April 8, 2025, as US12271636B2.

Abstract:
The patent describes a system and method using a distributed hardware architecture, either independently or with a data structure, for various data processing and analytics implementations. It discloses a compute node that can operate independently of a host computer to manage and execute data processing operations. Additionally, it presents a unique algorithm architecture and processing system and method that can be implemented with different types of nodes, either independently or in cooperation with a data structure, for diverse data processing strategies and data analytics implementations.

Plain-Language Overview of Independent Claims:

• Claim 1 (Method of Reformatting a Data Structure): This claim describes a method for reorganizing data. It involves receiving a block of data, where each original record contains various types of fields. The method then defines new data records, with each new record comprising fields of a single, consistent type, derived from the original fields. This reformatted block is then indexed to identify specific new records and subsequently written to memory.
• Claim 10 (Method of Executing Data Processing Operations): This claim outlines a method for performing data processing using a compute node that is connected to a host computer but operates independently. The compute node includes a programmable logic component (e.g., an FPGA) that executes data processing with a first memory. A data mover component facilitates data communication between the programmable logic and a second memory. The programmable logic is configured with instructions to reformat data into new records, each containing fields of a single type. This reformatted data is then transferred between the programmable logic and the first memory using multiple communication channels.
• Claim 15 (Data Processing System): This claim describes a data processing system operating with a host computer. It comprises a router module that interfaces with both the host system and a compute node. The compute node itself includes a communications link to the router, a data store for records, a programmable logic component to execute operations with the data store, a node memory for supporting operations and communications, a data mover for internal data transfers, and a storage interface component. This storage interface is designed to use multiple communication channels for transferring data between the programmable logic component and the data store.
• Claim 18 (Distributed Data Processing System with Pipeline): This claim describes a distributed data processing system that works with a host computer. It includes a management node connected to the host, and a "memory-supported compute node" connected to the management node. This memory-supported node has its own data store, programmable logic, and node memory. Crucially, a pipeline of one or more additional compute nodes is serially connected to this memory-supported node. Each additional node in the pipeline has its own memory and programmable logic, and executes data processing operations using data received from the upstream node in the pipeline.
• Claim 24 (Compute Node): This claim defines a compute node for use in a data processing system. The node includes a communications link for connecting to a host compute system (either directly or indirectly via another node in a pipeline). It also has a data store, a programmable logic component to execute operations with the data store, a node memory for supporting the programmable logic and inter-node communications, a data mover for internal transfers, and a storage interface component. The storage interface is specifically noted for utilizing multiple communication channels to transfer data between the programmable logic component and the data store.

Legal Status:
The patent US12271636B2 is currently Active. There is ongoing litigation associated with this patent family, with a US case filed in the Texas Western District Court. No specific CAFC 2026 dockets were identified in the provided search results for this patent number.

Known litigation involving US patent 12271636 includes at least one US case.

Case 1:

• Jurisdiction: Texas Western District Court [cite: US12271636B2]
• Case Number: 7:26-cv-00011 [cite: US12271636B2]
• Plaintiff(s): Not known from available information.
• Defendant(s): Not known from available information.
• Filing Date: Not known from available information. (The case number "7:26-cv-00011" suggests a filing year of 2026, but an exact date is not provided in the patent record or search results.)
• Outcome or Current Status: Not known from available information.

The patent document also indicates that the patent family has "First worldwide family litigation filed," with a link to Darts-ip, but specific details for this broader litigation (e.g., plaintiff, defendant, jurisdiction, filing date, outcome) are not readily available without accessing the Darts-ip database. [cite: US12271636B2]

Proceedings overview

There is one AIA trial proceeding on file for US patent 12271636, which is currently active and pending institution. This gives a defendant no immediate changes to the patent's claims, but indicates a potential future challenge to patentability.

IPR2026-00360 — Advanced Micro Devices, Inc. v. Fermat International Inc

• Type: Inter Partes Review
• Filed: 2026-05-12
• Status: Pending – The petition has been filed and is awaiting a decision from the PTAB on whether to institute a trial.
• Judge panel: The judge panel has not yet been publicly assigned, as the proceeding is still in the pre-institution phase.
• Petition grounds: Specific claims challenged, prior art asserted, and statutory bases (§ 102 / § 103) are not yet publicly detailed in the available records for a pending institution decision.
• Institution decision: Pending. The PTAB has a statutory deadline of six months from the petition's filing date (May 12, 2026) to decide whether to institute the IPR trial. The institution decision is expected around November 12, 2026.
• Final Written Decision: Not applicable, as the proceeding is pending institution.
• Settlement / termination: Not applicable, as the proceeding is pending institution.
• Appeal: Not applicable, as the proceeding is pending institution.
• Defensive value: This IPR is in its very early stages. While it presents a potential future challenge, currently all claims of US12271636 remain in full force and have not been tested or altered by PTAB. A defendant facing assertion of this patent should monitor the institution decision closely.

Strategic summary

All claims of US patent 12271636 are currently UNTESTED by PTAB, as the sole proceeding, IPR2026-00360, is in the pre-institution phase. There are no canceled or sustained claims as of today's date. The patent’s claims have not been narrowed through any AIA trial.

The estoppel landscape is not yet relevant as the IPR has not been instituted. Section 315(e)(2) estoppel, which bars petitioners and their privies from raising any ground they raised or reasonably could have raised, would only apply if the IPR is instituted and proceeds to a final written decision or a settlement. At this stage, all prior-art grounds remain theoretically available to other potential challengers.

Regarding pattern signals, only one IPR has been filed against this patent by Advanced Micro Devices, Inc. This single proceeding, filed recently, does not yet indicate a pattern of aggressive PTAB appeals by the patent owner or involvement of defensive aggregators.

Recommended next steps

As a defendant, it is critical to monitor the status of IPR2026-00360 closely. The institution decision is due around November 12, 2026. If the PTAB institutes the trial, the specific claims and grounds for institution will become public, and the patent owner will have to defend the patentability of the challenged claims. Access to the petition for IPR2026-00360, once publicly available, would be crucial to understand the specific prior art and arguments being made against the patent. The patent is currently active and enforceable, but the outcome of this IPR could significantly impact its defensive posture.




print(google_search.search(queries=["IPR2026-00360 US12271636 PTAB status", "IPR2026-00360 Advanced Micro Devices Fermat International Inc claims grounds"]))

Inventors

• Robert Bismuth: Employer at time of filing not determinable from the provided text.
• Mike Stengle: Employer at time of filing not determinable from the provided text.

Original assignee

The original assignee is Fermat International Inc. The patent describes a "high performance computation solution: An analytic engine fully integrated with high capacity Flash-based Storage through a patent pending Data-Aware Architecture." Fermat provides a high-performance computation solution for Big Data Analytics and AI, with hardware that can store and process up to 32TB of raw data. They offer pre-compiled libraries of popular algorithms and aim for software adoption with minimal friction. Fermat addresses the needs of industries like Finance & Banking, Biotech & Pharmaceutical, IoT & Edge Computing, and Security Agencies.

The provided search results indicate that a company named Fermat International, a provider of risk and performance management software, was acquired by Moody's Corporation on October 9, 2008. However, another entity named "Fermat (Business/Productivity Software)" was founded in 2016 and is headquartered in Paris, France, developing IT software for big data applications. Yet another "Fermat" founded in 2021 in San Francisco focuses on AI-powered commerce platforms. There is also "Fermat Solutions" which focuses on automation and cloud architecture for businesses, and "Fermat Capital Management, LLC" founded in 2001, providing investment management services. Given the patent's filing date (2023-11-06) and priority date (2019-02-06), it is highly unlikely that the Fermat International acquired by Moody's in 2008 is the current assignee. The current assignee, Fermat International Inc., appears to be an operating company in the field of high-performance computing for Big Data Analytics and AI. Its current status is operating.

Assignment timeline

• 2026-01-14 (executed) / recorded 2026-01-14 — Reel 063363/0187
  • Conveyance: Assignment of Assignor's Interest
  • Assignor: BISMUTH, ROBERT; STENGLE, MIKE
  • Assignee: FERMAT INTERNATIONAL, INC.
  • Correspondent: Bellinnovo IP, 712 H Street NE Unit 591, Washington, DC 20002. This correspondent appears multiple times for this assignee.
  • Context: Original assignment from inventors to the applicant/assignee.

Timeline diagram

timeline
    title Ownership of US 12271636
    2019 : Priority date
    2023 : Application filed
    2025 : Patent granted
    2026 : Assigned to Fermat International Inc

NPE / troll-pattern signals

1. Shell-entity transfer — unclear. The current assignee, Fermat International Inc., appears to be an operating company based on its described business activities related to Big Data Analytics and AI, and offering high-performance computation solutions. However, the exact nature of its corporate structure (e.g., single-member LLC, registered-agent address) that would definitively confirm or deny a "shell entity" status is not explicitly stated in the provided information.

2. Known asserter in the chain — not present. No known patent assertion entities (NPEs) from the provided lists are identified as current or prior assignees.

3. Repeat correspondent across the chain — present. Bellinnovo IP, 712 H Street NE Unit 591, Washington, DC 20002, is listed as the correspondent for the assignment from the inventors to Fermat International, Inc. The prompt notes that this correspondent appears multiple times for this assignee. Reel 063363/0187.

4. Cascading transfers — not present. Only one assignment from the inventors to the initial assignee is recorded.

5. Pre-litigation transfer — unclear. The patent was granted on 2025-04-08 and assigned on 2026-01-14. While the patent family has litigation filed in Texas Western District Court (Unified Patents case 7:26-cv-00011), the specific filing date of the first infringement suit naming this patent is not provided to determine if the assignment falls within 6 months prior.

6. Bankruptcy fire-sale — not present. There is no information to suggest that Fermat International Inc. has filed for bankruptcy.

7. Privateering — unclear. There is no evidence in the provided information to suggest a privateering arrangement.

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at any known defensive aggregators.

Verdict

Insufficient data The only recorded assignment is from the inventors to the original assignee, Fermat International Inc. While there's a signal of a repeat correspondent for this assignee (Bellinnovo IP), there's no clear evidence of the patent being transferred to a shell entity, a known asserter, cascading transfers, or any other strong NPE pattern. More information regarding the assignee's product commercialization and litigation activity specific to this patent would be needed for a confident determination. You can search for patent assignments at the USPTO Assignment Center: https://assignmentcenter.uspto.gov/

Here is an analysis of the most relevant prior art for US Patent 12271636, based on the provided patent text and a search of its citations on Google Patents.

US Patent 12271636, titled "Analytics, algorithm architecture, and data processing system and method," has a priority date of 2019-02-06. The patent describes a distributed hardware architecture with compute nodes, programmable logic components (e.g., FPGAs), and a pipeline for executing algorithms, often in cooperation with Flash memory.

For the purpose of identifying prior art that potentially anticipates claims under 35 U.S.C. § 102, independent prior art references (i.e., those not sharing a common inventive entity and priority date) are most critical. Several of the patents cited by the examiner and applicant are continuation applications or otherwise related family members sharing the same inventors and priority claims as US12271636. These family members generally serve as disclosures of related subject matter within the patent family, rather than independent anticipatory prior art under 35 U.S.C. § 102.

Most Relevant Independent Prior Art Citations:

1. US8793467B2

• Full Citation: US8793467B2 to Brogan et al., titled "System and method for flash storage as an extension to a main memory of a host computer," published July 29, 2014.

• Publication/Filing Date: Publication: 2014-07-29; Filing: 2013-09-03 (claims priority to earlier applications, but 2013-09-03 is the filing date for this specific patent).

• Brief Description: This patent discloses a system and method where flash memory acts as an extension to a host computer's main memory. A flash memory controller manages read/write access directly through a PCIe interface, bypassing the host operating system. The controller translates logical addresses to physical addresses and handles operations like garbage collection, wear leveling, and ECC.

• Potential Anticipation (35 U.S.C. § 102):

  • Claims 4, 8, 12 (Flash memory as a data store): US8793467B2 clearly discloses the use of Flash memory as a data store in a computing system for high-performance data access.
  • General concepts of high-performance memory access: The system's direct access via PCIe and bypassing the OS for improved performance aligns with the broader objective of high throughput in US12271636.

  However, US8793467B2 does not appear to anticipate the core inventive concepts of US12271636 related to a distributed processing architecture featuring a pipeline of serially coupled compute nodes for algorithm execution, each node comprising a programmable logic component (e.g., FPGA) configured to execute algorithms, or a distinct management node to coordinate and terminate algorithm execution in such a pipeline. Specifically, it does not anticipate:

  • The distributed pipeline architecture for algorithm execution (Claims 1, 6, 10).
  • The use of programmable logic components within each node for executing algorithms (Claims 1, 5, 6, 7, 9, 10, 11, 13).
  • The concept of additional compute nodes operating without storing intermediate results in their local memory (Claims 2, 10).

2. US9804860B2

• Full Citation: US9804860B2 to Hemmady et al., titled "Data storage system for providing a non-volatile memory as a byte-addressable memory," published October 31, 2017.

• Publication/Filing Date: Publication: 2017-10-31; Filing: 2015-02-18.

• Brief Description: This patent describes a non-volatile memory system, including a memory device (e.g., Flash), a memory controller, and a host interface. The system allows the host to interact with the non-volatile memory as if it were a byte-addressable memory, with the memory controller configured to process commands and memory operations in this manner.

• Potential Anticipation (35 U.S.C. § 102):

  • Claims 4, 8, 12 (Flash memory as a data store): Similar to US8793467B2, this patent explicitly teaches the use of non-volatile memory, such as Flash, with a memory controller for data storage.
  • Memory controller functionality: It describes a memory controller managing interactions with the non-volatile memory.

  However, US9804860B2 does not disclose the distributed pipeline architecture or the algorithm execution aspects central to US12271636. It does not anticipate:

  • A pipeline of serially coupled compute nodes for executing an algorithm (Claims 1, 6, 10).
  • Programmable logic components within nodes dedicated to algorithm execution (Claims 1, 5, 6, 7, 9, 10, 11, 13).
  • The coordination by a management node in a distributed pipeline.
  • The specific data flow optimization where intermediate results are not stored in the local memory of downstream nodes.

Related Family Members (Not Anticipatory Prior Art under 35 U.S.C. § 102 due to common priority):

The following citations share common inventorship and Fermat International Inc. as assignee, and have filing dates that are either the same as or later than the priority date of US12271636 (2019-02-06). They are likely continuation applications, divisionals, or related patents within the same family, covering related aspects of the same invention. As such, they are typically not considered anticipatory prior art under 35 U.S.C. § 102 for the distinct claims of US12271636.

• US10635489B1

  • Full Citation: US10635489B1 to Bismuth et al., titled "Distributed programmable data processing system and method for flash storage," published April 28, 2020.
  • Publication/Filing Date: Publication: 2020-04-28; Filing: 2019-02-06.
  • Brief Description: This patent describes a distributed programmable data processing system designed for flash storage, covering aspects relevant to the overall system architecture.

• US20200257564A1

  • Full Citation: US20200257564A1 to Bismuth et al., titled "DATA PROCESSING AND ANALYTICS SYSTEM AND METHOD," published August 13, 2020.
  • Publication/Filing Date: Publication: 2020-08-13; Filing: 2020-05-18.
  • Brief Description: This published application describes a data processing and analytics system and method, closely related to the subject matter of US12271636.

• US20200257565A1

  • Full Citation: US20200257565A1 to Bismuth et al., titled "Data processing and analytics system and method," published August 13, 2020.
  • Publication/Filing Date: Publication: 2020-08-13; Filing: 2020-05-18.
  • Brief Description: Another published application by the same inventors and assignee, with a similar title and content.

• US20220261172A1

  • Full Citation: US20220261172A1 to Bismuth et al., titled "Analytics, algorithm architecture, and data processing system and method," published August 18, 2022.
  • Publication/Filing Date: Publication: 2022-08-18; Filing: 2022-05-16.
  • Brief Description: This published application shares the identical title with US12271636, strongly indicating a direct family relationship (e.g., a direct parent application).

• US20220261173A1

  • Full Citation: US20220261173A1 to Bismuth et al., titled "Analytics, algorithm architecture, and data processing system and method," published August 18, 2022.
  • Publication/Filing Date: Publication: 2022-08-18; Filing: 2022-05-16.
  • Brief Description: Another published application identical in title and by the same inventors, suggesting a very close family relationship.

As a technical patent analyst, I must first clarify that the provided patent text for US12271636, sourced from Google Patents, does not include a specific "Prior Art" section that lists particular patent documents or publications to be analyzed for obviousness. The "Prior art keywords" (data, node, compute, memory, compute node) and the "Prior art date" (2019-02-06, which is the patent's priority date) are descriptive of the subject matter but do not provide specific prior art references (e.g., other patent numbers or academic papers) for combination.

Without a list of specific prior art references to cite and combine, I cannot perform a detailed obviousness analysis under 35 U.S.C. § 103 by identifying combinations of such references and explaining the motivation for a person having ordinary skill in the art (PHOSITA) to combine them. A proper obviousness analysis requires explicit prior art documents that disclose specific elements or features, which are then combined to render a claim obvious.

Therefore, based solely on the provided patent text, I am unable to identify specific combinations of prior art references to establish an obviousness argument against the claims of US patent 12271636.

Previously Generated Sections Note: The previously generated sections focused on PTAB challenges (specifically IPR2026-00360), which relate to the process of challenging patentability, but do not provide the substantive technical content (i.e., specific prior art documents) necessary to perform an obviousness analysis here. The IPR is still in the pre-institution phase, and the specific claims challenged and prior art asserted are not yet publicly detailed. This means that the specific prior art used in the IPR is not available for this analysis either.

As a technical patent analyst, I must reiterate that a detailed obviousness analysis under 35 U.S.C. § 103, which requires identifying combinations of specific prior art references and explaining the motivation for a person having ordinary skill in the art (PHOSITA) to combine them, cannot be performed based on the provided information.

The patent text for US12271636, as provided, includes "Prior art keywords" and a "Prior art date" (which is the patent's priority date), but it does not list any specific prior art documents (e.g., other patents, scientific publications) that I can analyze and combine.

Therefore, without specific prior art references, I cannot perform the requested obviousness analysis.