US 12271636

Here is a concise summary of US Patent 12271636:

US Patent 12271636 Summary

• Title: Analytics, algorithm architecture, and data processing system and method
• Assignee: Fermat International Inc.
• Inventors: Robert Bismuth, Mike Stengle
• Filing Date: November 6, 2023 (Application No. US18/502,275)
• Issue Date: April 8, 2025 (Publication of US12271636B2)
• Abstract: The patent describes a system and method utilizing a distributed hardware architecture, possibly with a specific data structure, for data processing and analytics. It details a compute node that can operate independently of a host computer to manage and execute data processing. Furthermore, it discloses a unique algorithm architecture and processing system and method, which can be implemented with various node types and data structures for diverse data processing and analytics applications.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim outlines a method for reformatting data. It involves taking an initial block of data, where each original record has various field types, and transforming it. The transformation process creates new records, with each new record containing only fields of a single type. These new records are then indexed and stored in memory. Essentially, it describes converting data from a row-oriented format to a column-oriented format where each "column" (now a new record) holds data of a uniform type.
• Claim 10: This claim details a method for executing data processing using a specialized compute node. This node works in conjunction with a host computer but performs operations independently. It includes a programmable logic component (e.g., an FPGA) that executes data processing tasks with a first memory, and a data mover that facilitates data transfer between the programmable logic and a second memory. A key feature is that this programmable logic can reformat incoming data (similar to Claim 1), and then transfers this reformatted data between itself and the first memory using multiple communication channels for efficiency.
• Claim 15: This claim describes a data processing system designed to operate with a host computer. The system features a router module that connects to the host and to a compute node. The compute node itself contains: a communication link to the router, a data store for processing records, a programmable logic component for executing operations with the data store, a node memory for supporting the programmable logic and communications, a data mover for internal data transfers, and a storage interface. The storage interface is notable for using multiple communication channels to move data efficiently between the programmable logic component and the data store.
• Claim 18: This claim describes a distributed data processing system. It comprises a "management node" connected to a host computer. Attached to the management node is a "memory-supported compute node," which includes its own data store, programmable logic, and local memory. Critically, a pipeline of one or more "additional compute nodes" is serially connected to this memory-supported node. Each of these additional nodes has its own memory and programmable logic, allowing them to process data received sequentially from the preceding node in the pipeline, thereby enabling a multi-stage processing workflow.
• Claim 24: This claim defines a compute node itself for use in a data processing system. This node connects to a host computer, either directly or indirectly through another node in a processing pipeline. The node integrates: a data store, a programmable logic component for executing operations with the data store, a node memory to support the programmable logic and facilitate communication with adjacent nodes, a data mover for internal data transfers, and a storage interface component. A significant aspect is that the storage interface component uses multiple communication channels to transfer data between the programmable logic and the data store, enhancing data throughput.

USPTO and CAFC 2026 Dockets Search:

A search for US patent 12271636 indicates that the patent is Active.

Regarding litigation, the patent family has litigation filed. Specifically, a US case was filed in the Texas Western District Court. The Unified Patents Litigation Data, licensed under a Creative Commons Attribution 4.0 International License, also confirms this.

No specific CAFC 2026 dockets were found directly linked to patent number 12271636 in the immediate search results, but the existing district court litigation suggests that appellate activity could potentially occur in the future.US Patent 12271636, titled "Analytics, algorithm architecture, and data processing system and method," was invented by Robert Bismuth and Mike Stengle. It is currently assigned to Fermat International Inc. The patent application (US18/502,275) was filed on November 6, 2023, and the patent was issued on April 8, 2025, as US12271636B2.

Abstract:
The patent describes a system and method using a distributed hardware architecture, either independently or with a data structure, for various data processing and analytics implementations. It discloses a compute node that can operate independently of a host computer to manage and execute data processing operations. Additionally, it presents a unique algorithm architecture and processing system and method that can be implemented with different types of nodes, either independently or in cooperation with a data structure, for diverse data processing strategies and data analytics implementations.

Plain-Language Overview of Independent Claims:

• Claim 1 (Method of Reformatting a Data Structure): This claim describes a method for reorganizing data. It involves receiving a block of data, where each original record contains various types of fields. The method then defines new data records, with each new record comprising fields of a single, consistent type, derived from the original fields. This reformatted block is then indexed to identify specific new records and subsequently written to memory.
• Claim 10 (Method of Executing Data Processing Operations): This claim outlines a method for performing data processing using a compute node that is connected to a host computer but operates independently. The compute node includes a programmable logic component (e.g., an FPGA) that executes data processing with a first memory. A data mover component facilitates data communication between the programmable logic and a second memory. The programmable logic is configured with instructions to reformat data into new records, each containing fields of a single type. This reformatted data is then transferred between the programmable logic and the first memory using multiple communication channels.
• Claim 15 (Data Processing System): This claim describes a data processing system operating with a host computer. It comprises a router module that interfaces with both the host system and a compute node. The compute node itself includes a communications link to the router, a data store for records, a programmable logic component to execute operations with the data store, a node memory for supporting operations and communications, a data mover for internal data transfers, and a storage interface component. This storage interface is designed to use multiple communication channels for transferring data between the programmable logic component and the data store.
• Claim 18 (Distributed Data Processing System with Pipeline): This claim describes a distributed data processing system that works with a host computer. It includes a management node connected to the host, and a "memory-supported compute node" connected to the management node. This memory-supported node has its own data store, programmable logic, and node memory. Crucially, a pipeline of one or more additional compute nodes is serially connected to this memory-supported node. Each additional node in the pipeline has its own memory and programmable logic, and executes data processing operations using data received from the upstream node in the pipeline.
• Claim 24 (Compute Node): This claim defines a compute node for use in a data processing system. The node includes a communications link for connecting to a host compute system (either directly or indirectly via another node in a pipeline). It also has a data store, a programmable logic component to execute operations with the data store, a node memory for supporting the programmable logic and inter-node communications, a data mover for internal transfers, and a storage interface component. The storage interface is specifically noted for utilizing multiple communication channels to transfer data between the programmable logic component and the data store.

Legal Status:
The patent US12271636B2 is currently Active. There is ongoing litigation associated with this patent family, with a US case filed in the Texas Western District Court. No specific CAFC 2026 dockets were identified in the provided search results for this patent number.