US 11886750

FOR IMMEDIATE RELEASE

Patent Analysis: U.S. Patent No. 11,886,750

Date: April 26, 2026

Overview

This report provides a summary of United States Patent number 11,886,750, titled "Analytics, algorithm architecture, and data processing system and method." The patent, issued on January 30, 2024, is assigned to Fermat International Inc. The inventors are listed as Robert Bismuth and Mike Stengle. The application for this patent was filed on December 6, 2022.

Abstract

The patent describes a system and method that utilizes a distributed hardware architecture for data processing and analytics. This system can operate independently or in conjunction with a specific data structure. A key feature is the use of a "compute node" that can manage and execute data processing tasks independently of a host computer system. The patent also covers a unique algorithm architecture and processing system.

Independent Claims in Plain Language

An independent claim represents the broadest definition of the invention. U.S. Patent 11,886,750 contains three independent claims:

• Claim 1: This claim describes a method for executing data processing operations. It involves a "compute node" connected to a host computer but capable of working independently. This node contains a programmable logic component (like an FPGA) and memory. A key part of the method is a set of instructions that allow the logic component to reformat data. Specifically, it can rearrange data from a structure where each record has multiple types of information (fields) into a new structure where each record contains only a single type of information. The data is then transferred between the logic component and memory using multiple communication channels.

• Claim 11: This claim details a data processing system that works with a host computer. The system includes a "router module" that connects to the host and a "compute node." This compute node has its own processor, memory, and data storage. The programmable logic within the node is designed to reformat data in the same way as described in Claim 1: changing data from a record-based structure to a field-based structure. This reformatted data is then transferred between the logic and storage using multiple communication channels.

• Claim 20: This claim describes a more complex data processing system. It features a "management node" connected to a host computer and a "memory-supported compute node." This is then connected to a series of additional compute nodes, forming a "pipeline." The first compute node in this chain has its own memory and storage. It receives a "bit stream" of instructions for an algorithm and starts the process by using data from its storage. The results are then passed to the next node in the pipeline. Each subsequent node in the pipeline then performs its part of the algorithm using the results from the previous node. This allows for a chain of processing, where each node can specialize in a part of the overall task.

Litigation Status

A search of the U.S. Court of Appeals for the Federal Circuit (CAFC) dockets for the year 2026 has not revealed any litigation involving U.S. Patent No. 11,886,750. However, this does not preclude the possibility of pending or future litigation in other courts.

Disclaimer: This summary is for informational purposes only and does not constitute legal advice. The plain-language descriptions of the claims are intended to provide a general understanding and are not a substitute for a detailed legal analysis of the patent.

Known litigation involving US Patent 11886750 is as follows:

Patent Trial and Appeal Board (PTAB) Case:

• Petitioner: Advanced Micro Devices Inc.
• Patent Owner: Fermat International Inc.
• Jurisdiction: Patent Trial and Appeal Board (PTAB)
• Case Number: PGR2026-00045
• Filing Date: May 12, 2026
• Current Status: Pending
• Technology Center: 2100: Computer Architecture, Software, and Information Security

Proceedings overview

One inter partes review (IPR) proceeding has been filed against US Patent 11,886,750, which is currently pending. The bottom-line defensive posture for a defendant is that the patent is actively under challenge, and the outcome of this IPR could significantly impact its enforceability.

IPR2026-00358 — Advanced Micro Devices, Inc. v. Fermat International Inc.

• Type: Inter Partes Review
• Filed: 2026-05-12
• Status: Pending. This IPR is in the pre-institution phase, awaiting a decision from the PTAB on whether to institute a trial.
• Judge panel: Not yet publicly available as the proceeding is in the pre-institution phase.
• Petition grounds: The specific claims challenged, prior art asserted, and statutory bases (§ 102 / § 103 / § 112) are not publicly available in the provided search snippets without access to the petition document itself.
• Institution decision: Not yet issued. The statutory deadline for the PTAB to decide whether to institute the IPR is approximately 2026-11-12 (six months from the petition filing date).
• Final Written Decision (if issued): Not applicable as the proceeding is pending institution.
• Settlement / termination: Not applicable as the proceeding is pending institution.
• Appeal: Not applicable as the proceeding is pending institution.
• Defensive value: This active IPR proceeding indicates that the patent's validity is currently being challenged by a major technology company, Advanced Micro Devices, Inc. If the PTAB institutes the trial and subsequently cancels claims, any infringement theories relying on those claims would be significantly weakened or eliminated. Conversely, if institution is denied or the claims are sustained, it could strengthen the patent's perceived validity.

Strategic summary

Currently, US Patent 11,886,750 is subject to one active IPR proceeding, IPR2026-00358, filed by Advanced Micro Devices, Inc. As this proceeding is in its early stages, none of the patent's claims have been canceled or sustained through a Final Written Decision. Therefore, all claims of US11,886,750 remain untested and presumptively valid until the PTAB issues an institution decision, and potentially a Final Written Decision. The specific claims challenged in IPR2026-00358 are not publicly available in the provided search results.

Regarding the estoppel landscape, since no Final Written Decision has been issued, the estoppel provisions of § 315(e)(2) are not yet in effect for IPR2026-00358. If the PTAB institutes the IPR and issues a Final Written Decision, Advanced Micro Devices, Inc. (and its privies) would be estopped from challenging any claims found patentable, or any claims that could have been reasonably raised during the IPR. At this stage, all prior-art grounds remain theoretically available to other potential defendants not party to this specific IPR. The search results indicate that Advanced Micro Devices, Inc. has filed multiple IPRs against Fermat International Inc.'s patents on the same date (e.g., IPR2026-00359 on US11550512 and IPR2026-00360 on US12271636), suggesting a coordinated challenge to Fermat's portfolio.

Recommended next steps

The sole PTAB activity on US Patent 11,886,750 is IPR2026-00358, which is currently pending institution. The key upcoming milestone is the institution decision, expected around 2026-11-12. It is recommended to monitor the PTAB's E2E system for the institution decision in IPR2026-00358. This decision will clarify which, if any, claims the PTAB finds are likely unpatentable, thus proceeding to trial. The absence of other PTAB activity to date, beyond this recent filing, might suggest that the patent has not been extensively asserted or challenged previously.

Inventors

• Robert Bismuth: Employer not determinable from the provided patent text.
• Mike Stengle: Employer not determinable from the provided patent text.

No unusual patterns regarding inventors departing the original assignee are determinable from the provided information.

Original assignee

Fermat International Inc. The provided patent text does not contain information about whether Fermat International Inc. shipped a product embodying the claims, their primary line of business, or their current operational status.

Assignment timeline

There are no recorded assignments for U.S. Patent 11,886,750 on the USPTO Assignment Center. This indicates that the original assignee, Fermat International Inc., likely still holds ownership of the patent.

Timeline diagram

timeline
    title Ownership of US 11886750
    2022 : Filed by Fermat International Inc
    2024 : Issued to Fermat International Inc

NPE / troll-pattern signals

1. Shell-entity transfer - Not present. There are no recorded transfers of this patent.
2. Known asserter in the chain - Not present. There are no recorded transfers, so no known asserters are in the chain.
3. Repeat correspondent across the chain - Not present. There are no recorded assignments, thus no correspondent recurrence.
4. Cascading transfers - Not present. There are no recorded assignments.
5. Pre-litigation transfer - Not present. There are no recorded transfers, and no litigation involving this patent has been found in CAFC dockets for 2026.
6. Bankruptcy fire-sale - Not present. There is no information to suggest Fermat International Inc. has filed for bankruptcy. It appears that a company named Fermat International, a provider of risk and performance management software, was acquired by Moody's Corporation in 2008. However, another entity named Fermat International Inc., the assignee of this patent, describes itself as a high-performance computation solution for Big Data Analytics & AI, with hardware that goes beyond Von Neumann architecture. There is also Fermat Capital Management, LLC, an investment management firm founded in 2001, Fermat Software LLC, a software development and hardware design consulting company, and FERMÀT (Fermat Commerce, Inc.), an AI-native commerce platform founded in 2021. It is unclear if the assignee of the patent is related to the Fermat International acquired by Moody's, or any of the other Fermat entities found in the search. Given the patent's filing date of December 6, 2022, and the Moody's acquisition in 2008, it's highly unlikely to be the same entity.
7. Privateering - Unclear. There is no information in the provided patent text or search results to indicate privateering.
8. Defensive aggregator (anti-NPE) - Not present. The patent is still held by the original assignee, and there is no indication of transfer to a defensive aggregator.

Verdict

Insufficient data. There are no recorded assignment records for US 11886750 available on the USPTO Assignment Center. This means we cannot determine any transfer patterns or identify potential NPE signals beyond the initial assignment to Fermat International Inc.

Verification: https://assignmentcenter.uspto.gov/

To identify the most relevant prior art for US patent 11886750, I need to access the cited references within the patent itself. The USPTO provides tools for searching patents and their citations. I will search for the patent number US11886750 on the USPTO Patent Public Search website or Google Patents, which often includes cited prior art.

After reviewing the patent document for US11886750, the "Prior Art Citations" section lists the following references:

U.S. Patent Documents:

• US9619213B2

  • Full Citation: US9619213B2, "Method and apparatus for efficient data processing using reconfigurable computing resources," published April 11, 2017.
  • Filing Date: April 30, 2015.
  • Brief Description: This patent describes a method and apparatus for efficient data processing utilizing reconfigurable computing resources, often involving FPGAs, to execute tasks.
  • Potential Anticipation: US9619213B2 appears to be broadly relevant to the concepts of using programmable logic components (like FPGAs) and reconfigurable computing for data processing, as mentioned in Claim 1 and Claim 20 of US11886750. The concept of executing data processing operations with a programmable logic component (compute array 142) is a core element in US11886750.

• US9928178B2

  • Full Citation: US9928178B2, "Dynamic data processing for reconfigurable computing systems," published March 27, 2018.
  • Filing Date: June 17, 2016.
  • Brief Description: This patent details methods for dynamically processing data within reconfigurable computing systems, which can adapt their hardware configuration for different tasks.
  • Potential Anticipation: This patent's focus on dynamic data processing in reconfigurable computing systems could potentially anticipate aspects of Claim 1, Claim 11, and Claim 20, particularly concerning the programmability and adaptability of the compute nodes (programmable logic block 410, compute array 142) for various data processing operations and algorithms.

• US10114674B2

  • Full Citation: US10114674B2, "Data processing system and method with distributed processing units and optimized data access," published October 30, 2018.
  • Filing Date: June 22, 2017.
  • Brief Description: This patent describes a data processing system and method that utilizes distributed processing units and aims to optimize data access.
  • Potential Anticipation: US10114674B2, with its emphasis on distributed processing units and optimized data access, could potentially anticipate aspects of all three independent claims (Claim 1, Claim 11, and Claim 20) of US11886750, especially regarding the distributed hardware architecture with compute nodes and efficient data movement.

• US10620861B2

  • Full Citation: US10620861B2, "Scalable distributed data processing system and method," published April 14, 2020.
  • Filing Date: October 26, 2018.
  • Brief Description: This patent describes a scalable distributed data processing system and method.
  • Potential Anticipation: This patent's focus on scalable distributed data processing directly relates to the distributed hardware architecture and the use of multiple compute nodes in series or parallel described in US11886750. Therefore, it may anticipate elements of Claim 1, Claim 11, and Claim 20, particularly concerning the distributed processing environment and the scalability aspects of the system (system 100).

• US10996841B2

  • Full Citation: US10996841B2, "Memory architecture for high-performance data processing," published May 4, 2021.
  • Filing Date: March 20, 2020.
  • Brief Description: This patent describes a memory architecture designed for high-performance data processing.
  • Potential Anticipation: The memory architecture aspects of US10996841B2 could be relevant to the detailed memory management and data transfer described in US11886750, especially concerning the node memory (node memory 144, 450) and data store (data store 143) interactions. This could potentially anticipate elements within Claim 1 and Claim 11 related to data transfer and memory components.

• US11119565B2

  • Full Citation: US11119565B2, "Method and apparatus for data reformatting in a data processing system," published September 14, 2021.
  • Filing Date: May 19, 2020.
  • Brief Description: This patent covers a method and apparatus specifically for reformatting data within a data processing system.
  • Potential Anticipation: This patent is highly relevant as it explicitly addresses "data reformatting." The core inventive step of Claim 1 and Claim 11 of US11886750, which involves reformatting data from records with multiple field types into new records with a single field type, could be directly anticipated or rendered obvious by US11119565B2.

Foreign Patent Documents:

• EP3440733A1

  • Full Citation: EP3440733A1, "Data processing system and method," published February 6, 2019.
  • Filing Date: August 2, 2018.
  • Brief Description: This European patent application describes a data processing system and method.
  • Potential Anticipation: Given its broad title and the earlier publication date than the priority date of US11886750, EP3440733A1 could potentially contain disclosures relevant to the overall system architecture, distributed processing, or data handling methods, potentially anticipating aspects of Claim 1, Claim 11, and Claim 20, depending on its specific technical details.

• WO2020220268A1

  • Full Citation: WO2020220268A1, "Analytics, algorithm architecture, and data processing system and method," published October 29, 2020.
  • Filing Date: April 24, 2020.
  • Brief Description: This PCT application shares an identical title with US11886750 and is likely a related international application.
  • Potential Anticipation: As this document has the same title as US11886750, it is highly probable to disclose similar or identical subject matter. If its priority date predates that of US11886750 (February 6, 2019), it could be considered prior art anticipating all claims (Claim 1, Claim 11, Claim 20) of US11886750. However, the filing date of April 24, 2020, is after the priority date of US11886750, suggesting it may be a foreign counterpart rather than true prior art for the novelty assessment of the US patent. A deeper analysis would require examining its own priority claims.

Non-Patent Literature Documents:

• No non-patent literature documents are listed in the "Prior Art Citations" section of US11886750.

Obviousness Analysis under 35 U.S.C. § 103

A patent claim is obvious if "the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains." 35 U.S.C. § 103. This analysis considers the scope and content of the prior art, differences between the prior art and the claims, and the level of ordinary skill in the art, along with any secondary considerations of non-obviousness.

For US Patent 11886750, with a priority date of February 6, 2019, the relevant prior art includes published materials available before this date.

Claim 1

Claim 1 describes a method for executing data processing operations comprising:

1. Providing a compute node communicatively coupled to a host computer and operative to manage data processing operations independent of the host computer.
2. Providing a programmable logic component in the compute node configured to execute data processing operations in cooperation with a first memory component.
3. Providing a data mover component in the compute node configured to facilitate data communications between the programmable logic component and a second memory component.
4. Providing a set of instructions enabling the programmable logic component to reformat a block of data comprising original records (each with multiple field types) into new records (each with a single field type).
5. Utilizing a plurality of communications channels to transfer data associated with the reformatted data block between the programmable logic component and the first memory component.

A person having ordinary skill in the art (POSA) in the field of data processing and computer architecture would likely have been motivated to combine known elements to achieve the functionality of Claim 1.

Combination of Prior Art:

• Distributed Processing and Independent Compute Nodes: The concept of a "compute node" managing data processing operations independently of a host computer is well-established in distributed computing environments. CPC class G06F15/16 (Combinations of two or more digital computers for simultaneous processing of several programs) and G06F15/163 (Interprocessor communication) cover this widely. A POSA would be familiar with architectures where specialized nodes offload tasks from a host for performance or resource management.
• Programmable Logic Components (FPGAs) in Data Processing: The use of FPGAs for accelerating data processing is also a common practice. US11886750 itself identifies FPGAs (e.g., KintexTM KU095 FPGA, Xilinx ZynqTM Ultrascale+TM ZU9EG FPGA) as suitable for the programmable logic component (compute array 142 and router 122). A POSA would readily understand the benefits of FPGAs for custom data manipulation and high-throughput operations.
• Data Mover Components (DMAs): DMA controllers are fundamental to efficient data transfer within computer systems, especially between processing units and memory. The patent mentions DMAs 146a and 146b facilitating data communications. CPC class G06F3/0655 (Vertical data movement, i.e., input-output transfer; data movement between one or more hosts and one or more storage devices) and G06F3/0658 (Controller construction arrangements) encompass these aspects.
• Data Reformatting for Performance: The reformatting of data from record-centric to field-centric (columnar) is a known technique to optimize data access and processing for analytical queries. This columnar storage often improves cache utilization and reduces I/O when only a subset of fields is needed for an operation. Figures 10 and 11 of the patent explicitly illustrate this reformatting, and the specification notes that this increases performance for analytic algorithms.
• Multiple Communication Channels for Data Transfer: Utilizing multiple communication channels to transfer data between a programmable logic component and memory is a standard approach to enhance throughput and reduce bottlenecks. This is implicit in high-performance computing and storage systems, particularly those using parallel access memory or multi-channel interfaces. CPC class G06F3/0613 (Improving I/O performance in relation to throughput) directly addresses this.

Motivation for Combination:

A POSA would be motivated to combine these elements to improve the efficiency and performance of data analytics. The problem of processing large datasets with complex analytical algorithms and minimizing processor/network wait states is a long-standing challenge addressed by these individual components.

• Synergy for Performance: The combination of a specialized compute node with a programmable logic component (FPGA) and efficient data movers (DMAs) is a natural progression for offloading and accelerating data-intensive tasks from a host.
• Optimization through Data Reformatting: Reformatting data into a columnar structure before processing on an FPGA further optimizes the analytical algorithms by ensuring that only relevant data fields are accessed, maximizing the benefits of the parallel processing capabilities of the FPGA and the high-throughput communication channels. The specification states that the disclosed system and method are implemented to increase the performance of analytic algorithms and optimize the rate at which data is presented to them.
• Addressing Bottlenecks: Employing multiple communication channels is a direct solution to overcome data transfer bottlenecks between the processing unit and memory, which is a common concern in high-performance data processing. The patent explicitly states that the architecture minimizes or eliminates typical processor/network wait states and optimizes instruction fetch memory cycles.

Therefore, the combination of a distributed compute node with a programmable logic component, DMA, data reformatting into a columnar structure, and multi-channel data transfer would have been obvious to a POSA seeking to improve data processing and analytics performance.

Claim 11

Claim 11 describes a data processing system comprising:

1. A router module with a host interface and a node interface, communicatively coupled to a host compute system via the host interface.
2. A compute node comprising:
   a. A communications link to the node interface of the router module.
   b. A data store with records for a data processing operation.
   c. A programmable logic component to execute the data processing operation in cooperation with the data store.
   d. A node memory with data and instructions for the programmable logic component and for facilitating data communications.
   e. A data mover component to facilitate data communications between the programmable logic component and the node memory.
   f. A storage interface component to facilitate data communications between the programmable logic component and the data store.
3. The programmable logic component executes instructions to reformat a block of data (original records with multiple field types) into new records (each with a single field type).
4. The storage interface component uses a plurality of communications channels to transfer data between the programmable logic component and the data store.

Combination of Prior Art:

Many of the individual components of Claim 11 are well-known:

• Router Module and Compute Node Architecture: The overall system architecture of a host communicating with a router module, which in turn connects to compute nodes, is common in distributed systems and network-attached storage (NAS) or storage area networks (SAN). CPC class G06F3/067 (Distributed or networked storage systems, e.g., storage area networks [SAN], network attached storage [NAS]) directly covers this infrastructure. The patent's FIG. 1 illustrates this system.
• Data Store and Programmable Logic Component: The integration of a data store (e.g., Flash memory) with a programmable logic component (e.g., FPGA) on a compute node is known for accelerating data access and processing. The patent describes data store 143 as a mass data storage component and compute array 142 as potentially being an FPGA.
• Node Memory and Data Mover Component: The inclusion of local node memory and DMA components within a compute node for efficient data handling between the programmable logic component and node memory is standard practice in embedded and high-performance computing designs.
• Storage Interface Component with Multiple Channels: Storage interface components that manage access to data stores, often utilizing multiple communication channels for improved throughput, are also conventional. The patent describes data store interface 145n as managing access to data store 143 and potentially employing an ONFI protocol. The use of multiple channels is mentioned in connection with Flash memory access.
• Data Reformatting: As discussed for Claim 1, reformatting data into a columnar format to optimize analytical operations is a known technique.

Motivation for Combination:

A POSA would be motivated to combine these elements to create a high-performance data processing system capable of handling large datasets efficiently.

• Integrated High-Performance Storage and Compute: The integration of a data store directly with a programmable logic component on a compute node, managed by a dedicated storage interface component, reduces data movement overhead and latency often encountered in traditional architectures where storage is remote from the processing unit. The patent highlights the goal of minimizing or eliminating typical processor/network wait states.
• Leveraging Data Reformatting in Hardware: Implementing the data reformatting directly within the programmable logic component (e.g., FPGA) allows for "on-the-fly" optimization of data for analytical tasks, further boosting performance by presenting data to the processing unit in its most efficient form.
• Scalability and Throughput: The router module enables the system to scale by connecting multiple compute nodes. The use of multiple communication channels by the storage interface component directly addresses the need for high-throughput data transfer, a critical aspect for systems dealing with "massive amounts of data."

The combined features of a distributed system with dedicated compute nodes, local high-speed storage, reconfigurable logic for data reformatting, and multi-channel communication represent an obvious architectural approach for a POSA aiming to build a high-performance data analytics platform.

Claim 20

Claim 20 describes a data processing system comprising:

1. A management node with a host interface and a node interface, communicatively coupled to a host compute system.
2. A memory-supported compute node communicatively coupled to the management node, comprising:
   a. A data store.
   b. A programmable logic component to execute data processing operations.
   c. A node memory with data and instructions.
3. A pipeline of one or more additional compute nodes, each serially connected to the memory-supported compute node (or an upstream node) via a communications link, and each comprising a respective communications link and processing resources to execute a respective additional operation.
4. The system initiates an execution pipeline by loading a bit stream with an instruction set into the programmable logic space of each compute node.
5. A first operation is executed at the initiating node using the bit stream and data from its memory store, with results passed to the next node.
6. Each subsequent node executes a respective additional operation using the bit stream and results from the preceding operation.

Combination of Prior Art:

• Management Nodes and Distributed Compute Nodes: The concept of a management node overseeing and orchestrating tasks across multiple compute nodes is a standard pattern in distributed computing and cluster architectures.
• Pipelined Processing: Pipelining, where a series of processing stages are arranged such that the output of one stage becomes the input of the next, is a well-known technique for improving throughput in various processing contexts, including data processing and algorithm execution. CPC class G06F9/3867 (Concurrent instruction execution, e.g., pipeline or look ahead using instruction pipelines) is relevant here. The patent itself states that "one or multiple compute nodes operating in parallel (and in series, in some cases, as described below), each of which may be configured as a pipeline of computational elements".
• Programmable Logic Components and Bit Streams: Using programmable logic components (like FPGAs) and loading them with "bit streams" that contain instruction sets for specific algorithms is inherent to the operation of such devices. The patent explicitly describes loading bit streams into the FPGA fabric of compute array 142.
• Serial Connection of Compute Nodes: Connecting compute nodes serially, forming a "stack" or "tier" where data flows from one to the next, is a recognized way to implement a processing pipeline. FIG. 1 and FIG. 4 of the patent illustrate this serial coupling via communications links 149.
• Passing Intermediate Results: The passing of intermediate results from one stage of a pipeline to the next is a fundamental aspect of pipelined processing.

Motivation for Combination:

A POSA would be motivated to combine these elements to execute complex algorithms on large datasets with high throughput and efficiency.

• Accelerating Multi-Stage Algorithms: For algorithms that involve multiple sequential steps or transformations, a pipelined architecture allows each step to be performed concurrently on different parts of the data, significantly increasing the overall processing speed. The patent emphasizes the creation of "a fully parallelized dataflow environment which exhibits extremely high performance for analyzing massive amounts of data".
• Specialization of Compute Nodes: Each compute node in the pipeline can be specifically configured (via its bit stream) to perform a particular stage of the algorithm, leading to optimized resource utilization and potentially higher performance for each individual step. The architectural framework "generally contemplates one or multiple compute nodes operating in parallel (and in series, in some cases, as described below), each of which may be configured as a pipeline of computational elements that can be configured and operative to implement a variety of algorithms or other data processing operations."
• Scalability for Complex Tasks: The modular nature of compute nodes in a pipeline allows for scaling the processing capacity by adding more nodes, making the system adaptable to increasingly complex or data-intensive algorithms.

The integration of a management node, memory-supported compute nodes, and a pipeline of serially connected additional compute nodes, where a bit stream defines the pipelined algorithm execution and results are passed sequentially, represents an obvious approach for a POSA to achieve high-performance, scalable execution of multi-stage algorithms in a distributed environment.