US 10877233

US patent 10877233, titled "Active ethernet cable with preset pre-equalization," was filed on November 27, 2019, and issued on December 29, 2020. The patent is assigned to Credo Technology Group Ltd. The inventors are Yifei Dai, Yattung Lam, and Rajan Pai.

Abstract:
The patent describes a cable, a manufacturing method, and a communications method that utilize preset transmit-side equalization to enhance performance and/or reduce receiver-side equalization needs. An exemplary cable includes first and second data recovery and re-modulation (DRR) devices that exchange multi-lane data streams with host interface ports via end connector plugs. Electrical conductors connect these DRR devices to convey electrical transit signals. Both DRR devices convert between these electrical transit signals and the multi-lane data streams for their respective host interface ports, providing pre-equalization of the electrical transit signals using transmit filter coefficient values stored in nonvolatile memories.

Plain-language overview of independent claims:

• Claim 1 (Cable): This claim describes an active Ethernet cable designed for high-speed data transmission. It includes two "data recovery and re-modulation" (DRR) devices, one at each end, connected by electrical conductors. Each DRR device handles data streams going to and from a host device via a connector plug. A key feature is that these DRR devices "pre-equalize" the signals traveling through the internal electrical conductors of the cable using specific filter settings stored permanently in memory. This pre-equalization helps overcome signal degradation over longer cable lengths.

• Claim 8 (Cable Manufacturing Method): This claim outlines a method for making such an active Ethernet cable. It involves connecting two DRR devices to their respective connector plugs and then connecting electrical conductors between these DRR devices. Similar to Claim 1, the DRR devices are configured to convert multi-lane data streams and perform pre-equalization of the electrical signals traveling through the cable's conductors using transmit filter coefficients stored in nonvolatile memories.

• Claim 15 (Communications Method): This claim describes a method for using the active Ethernet cable for communication. It involves plugging the cable's two end connectors into host interface ports. Each DRR device in the cable converts incoming multi-lane data from its host into electrical signals for transmission through the cable's conductors to the other DRR device. Conversely, it receives electrical signals from the cable and converts them back into multi-lane data for its host. This method also explicitly includes the DRR devices performing pre-equalization on the electrical transit signals using stored transmit filter coefficients.

Litigation Status:
As of April 26, 2026, US Patent 10877233 is active. The patent has been cited in several ongoing legal proceedings. Multiple US cases have been filed in the Texas Eastern District Court and Delaware District Court. Additionally, there are Inter Partes Review (IPR) cases filed before the Patent Trial and Appeal Board (PTAB), including IPR2025-01218, which is listed as "Pending - Instituted". The patent is also involved in an International Trade Commission (ITC) investigation, specifically Case 337-1446, titled "Certain Active Electrical Cables and Components Thereof," where Credo Technology Group Ltd. is a complainant, alleging patent infringement. A direct search of CAFC 2026 dockets for this specific patent number did not return explicit results, but the linked litigation information confirms ongoing legal challenges.

US Patent 10877233, "Active Ethernet Cable with Preset Pre-Equalization," is involved in multiple litigation proceedings. The current assignee of the patent is Credo Technology Group Ltd.

Known litigation involving US patent 10877233 includes:

1. US case filed in Texas Eastern District Court

   • Jurisdiction: Texas Eastern District Court [cite: US10877233B1]
   • Case Number: 2:25-cv-00298 [cite: US10877233B1]
   • Filing Date: 2025 (inferred from case number 2:25-cv-00298)
   • Plaintiff(s): Not specified in the provided data.
   • Defendant(s): Not specified in the provided data.
   • Outcome or Current Status: Litigation (critical) [cite: US10877233B1]

2. US case filed in Texas Eastern District Court

   • Jurisdiction: Texas Eastern District Court [cite: US10877233B1]
   • Case Number: 2:25-cv-00296 [cite: US10877233B1]
   • Filing Date: 2025 (inferred from case number 2:25-cv-00296)
   • Plaintiff(s): Not specified in the provided data.
   • Defendant(s): Not specified in the provided data.
   • Outcome or Current Status: Litigation [cite: US10877233B1]

3. US case filed in Texas Eastern District Court

   • Jurisdiction: Texas Eastern District Court [cite: US10877233B1]
   • Case Number: 2:25-cv-00297 [cite: US10877233B1]
   • Filing Date: 2025 (inferred from case number 2:25-cv-00297)
   • Plaintiff(s): Not specified in the provided data.
   • Defendant(s): Not specified in the provided data.
   • Outcome or Current Status: Litigation [cite: US10877233B1]

4. US case filed in Delaware District Court

   • Jurisdiction: Delaware District Court [cite: US10877233B1]
   • Case Number: 1:25-cv-00316 [cite: US10877233B1]
   • Filing Date: 2025 (inferred from case number 1:25-cv-00316)
   • Plaintiff(s): Not specified in the provided data.
   • Defendant(s): Not specified in the provided data.
   • Outcome or Current Status: Litigation [cite: US10877233B1]

5. US case filed in International Trade Commission

   • Jurisdiction: International Trade Commission [cite: US10877233B1]
   • Case Number: 337-TA-1446 [cite: US10877233B1]
   • Filing Date: Not specified, but listed with other 2025 cases.
   • Plaintiff(s): Not specified in the provided data.
   • Defendant(s): Not specified in the provided data.
   • Outcome or Current Status: Litigation [cite: US10877233B1]

6. PTAB case IPR2025-00835

   • Jurisdiction: Patent Trial and Appeal Board (PTAB) [cite: US10877233B1]
   • Case Number: IPR2025-00835 [cite: US10877233B1]
   • Filing Date: 2025 (inferred from case number IPR2025-00835)
   • Petitioner: Amphenol Corporation [cite: US10877233B1]
   • Opponent: Credo Technology Group Ltd. (as patent owner)
   • Outcome or Current Status: Settlement [cite: US10877233B1]

7. PTAB case IPR2025-01218

   • Jurisdiction: Patent Trial and Appeal Board (PTAB) [cite: US10877233B1]
   • Case Number: IPR2025-01218 [cite: US10877233B1]
   • Filing Date: 2025 (inferred from case number IPR2025-01218)
   • Petitioner: Marvell Semiconductor, Inc. [cite: US10877233B1]
   • Opponent: Credo Technology Group Ltd. (as patent owner)
   • Outcome or Current Status: Pending - Instituted [cite: US10877233B1]

8. PTAB case IPR2025-01385

   • Jurisdiction: Patent Trial and Appeal Board (PTAB) [cite: US10877233B1]
   • Case Number: IPR2025-01385 [cite: US10877233B1]
   • Filing Date: 2025 (inferred from case number IPR2025-01385)
   • Petitioner: Volex PLC [cite: US10877233B1]
   • Opponent: Credo Technology Group Ltd. (as patent owner)
   • Outcome or Current Status: Settlement [cite: US10877233B1]

Proceedings overview

US patent 10877233 has been involved in two AIA trial proceedings. One proceeding (IPR2025-01385) terminated as settled prior to institution, meaning no claims were formally invalidated by the PTAB. The other proceeding (IPR2025-01218) is currently in trial, actively challenging the patentability of certain claims. This gives a defendant a mixed defensive posture: while one challenge was resolved without claim invalidation, another is ongoing with the potential for claims to be canceled.

IPR2025-01218 — Marvell Semiconductor, Inc. v. Credo Technology Group Ltd.

• Type: Inter Partes Review
• Filed: 2025-08-01
• Status: Trial Instituted.
• Judge panel: Information regarding the specific judge panel for this proceeding on US10877233 was not found in the provided search results.
• Petition grounds: Specific details on which claims were challenged, the prior art asserted, and the statutory basis (§ 102 / § 103 / § 112) for this IPR on patent 10877233 were not explicitly available in the provided search snippets.
• Institution decision: Instituted. While the precise date and reasoning for the institution decision for this specific IPR on patent 10877233 were not found, based on typical PTAB timelines (six months from filing), institution likely occurred around February 2026.
• Final Written Decision (if issued): Not yet issued, as the proceeding is still in the trial phase.
• Settlement / termination: N/A.
• Appeal: N/A.
• Defensive value: This active IPR represents an ongoing challenge to the patentability of claims in US10877233. A defendant facing assertion of this patent should closely monitor this proceeding. If claims are ultimately invalidated, any infringement theories relying on those claims would be significantly weakened or rendered moot. The Final Written Decision is anticipated approximately one year from the institution date, likely around February 2027.

IPR2025-01385 — Volex plc v. Credo Technology Group Ltd.

• Type: Inter Partes Review
• Filed: 2025-08-07.
• Status: Terminated-Settled. This IPR was terminated prior to the institution of trial.
• Judge panel: Not applicable, as no trial was instituted.
• Petition grounds: Volex plc's petition challenged claims 1-20 of US Patent No. 10,877,233. Specific prior art and statutory grounds were not detailed in the public snippets.
• Institution decision: Denied (due to settlement prior to institution). The Patent Trial and Appeal Board (PTAB) issued a decision on September 9, 2025, granting a joint request to treat the settlement agreement as confidential, and subsequently granted a Joint Motion to Terminate Proceeding on September 10, 2025, prior to instituting a trial. Volex plc requested a refund of post-institution fees, confirming that no trial was instituted.
• Final Written Decision: Not issued, as the proceeding terminated before a trial was instituted.
• Settlement / termination: The proceeding terminated on September 10, 2025, due to a confidential license and settlement agreement reached between Volex plc and Credo Technology Group Ltd. The specific terms of the agreement remain confidential.
• Appeal: N/A.
• Defensive value: This IPR concluded without any claims of US10877233 being formally invalidated by the PTAB. All claims (1-20) challenged in the petition were not subjected to a PTAB trial on their merits. Consequently, for third parties, these claims retain their presumptive validity. For Volex plc and its privies, while the settlement likely resolves their specific dispute with Credo regarding this patent, the formal estoppel provisions of 35 U.S.C. § 315(e)(2) for grounds raised or reasonably could have raised in an instituted trial would not apply, as no trial was instituted.

Strategic summary

Currently, all claims of US10877233 remain patentable as no Final Written Decision has been issued invalidating any claims. In IPR2025-01385, Volex plc challenged claims 1-20, but the proceeding settled prior to institution of a trial, meaning these claims were not adjudicated by the PTAB and thus were not canceled. For IPR2025-01218, filed by Marvell Semiconductor, Inc., the trial has been instituted, indicating that the PTAB found a reasonable likelihood of unpatentability for at least some challenged claims. However, the specific claims under review and the outcome are still pending. Therefore, for a defendant, US10877233 has not yet been narrowed through PTAB proceedings.

Regarding estoppel, Volex plc and its privies are not formally estopped under 35 U.S.C. § 315(e)(2) for IPR2025-01385 because the proceeding settled before institution. Their ability to challenge the patent or specific claims in other forums would be governed by the confidential settlement agreement. Marvell Semiconductor, Inc. (and its privies) will face estoppel under § 315(e)(2) for IPR2025-01218 for any grounds raised or that reasonably could have been raised, upon the issuance of a Final Written Decision. For other potential petitioners, any prior art not raised in the instituted IPR (or the settled one) remains available for challenging the patent.

The patent owner, Credo Technology Group Ltd., has seen two separate petitioners challenge US10877233, suggesting the patent covers technology of commercial interest to competitors. The quick settlement of the Volex IPR before institution also indicates that Credo may be amenable to licensing agreements or other resolutions to avoid PTAB trials, or that the specific petition grounds for IPR2025-01385 were not strong enough to warrant institution from Volex's perspective once a settlement was reached.

Recommended next steps

For IPR2025-01218 (Marvell Semiconductor, Inc. v. Credo Technology Group Ltd.), which is in active trial, it is critical to monitor its progress. The Final Written Decision is expected approximately one year from the institution date (likely around February 2027). You should regularly check the USPTO PTAB E2E portal for updates on this proceeding, particularly for the release of the institution decision (if not yet found) and the eventual Final Written Decision, which will detail any claims canceled or sustained. The outcome of this trial will directly inform the strength of US10877233's claims.

Inventors

• Yifei Dai (Credo Technology Group Ltd)
• Yattung LAM (Credo Technology Group Ltd)
• Rajan PAI (Credo Technology Group Ltd)

Original assignee

The original assignee is Credo Technology Group Ltd. Credo Technology Group Ltd is an operating company focused on providing high-speed connectivity solutions for the data infrastructure market. Their products include integrated circuits, active electrical cables (AECs), SerDes chiplets, optical PAM4 digital signal processors, and low-power line card PHYs. They are currently an operating company, publicly traded on NASDAQ under the symbol CRDO.

Assignment timeline

• 2019-05-22 (executed) / recorded 2019-11-27 — Reel 051134/0419
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: LAM, YATTUNG; DAI, YIFEI; PAI, RAJAN
  • Assignee: CREDO TECHNOLOGY GROUP LIMITED
  • Correspondent: BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP, 1279 OAKMEAD PARKWAY, SUNNYVALE, CALIFORNIA, 94085-4040.

Timeline diagram

timeline
    title Ownership of US 10877233
    2019 : Filed by Credo Technology Group Ltd
    2019 : Inventors assigned to Credo Technology Group Limited
    2020 : Issued

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The sole recorded assignment is from the inventors to the original assignee, Credo Technology Group Limited, which is an operating company.
2. Known asserter in the chain — not present. Credo Technology Group Limited is an operating company, not a known NPE.
3. Repeat correspondent across the chain — not present. There is only one recorded assignment in the chain.
4. Cascading transfers — not present. There is only one recorded assignment.
5. Pre-litigation transfer — unclear. Without knowledge of any infringement suits, this cannot be determined.
6. Bankruptcy fire-sale — not present. Credo Technology Group Ltd is an active, publicly traded company.
7. Privateering — not present. The patent has not been transferred from the original operating company.
8. Defensive aggregator (anti-NPE) — not present. The patent is currently held by Credo Technology Group Limited.

Verdict

Insufficient data. The only recorded assignment is from the inventors to the original assignee, Credo Technology Group Limited. Credo Technology Group Limited is an operating company that develops and sells high-speed connectivity solutions. There is no evidence in the provided assignment record to suggest NPE activity.

USPTO Assignment Center search: https://assignmentcenter.uspto.gov/

I will search the USPTO database for US patent 10877233 and identify the most relevant prior art. Since direct access to the USPTO database for live querying is not available through this interface, I will rely on the provided patent text and the Google Patents citation list to identify prior art and analyze its relevance.

Here's an analysis of the most relevant prior art cited within US patent 10877233:

Prior Art Analysis for US Patent 10877233

The following prior art documents are cited in US Patent 10877233 and are assessed for their potential to anticipate the independent claims (Claims 1, 8, and 15) under 35 U.S.C. § 102.

1. US20070237464A1: Electrical-optical active optical cable

   • Full Citation: US20070237464A1 (Aronson Lewis B)
   • Publication/Filing Date: Publication: October 11, 2007. Filing: April 10, 2006.
   • Brief Description: This patent application describes an electrical-optical active optical cable. While it involves active cables, its core innovation lies in the conversion between electrical and optical signals. US10877233B1, in contrast, focuses on active electrical cables with electrical transit signals and pre-equalization.
   • Potential Anticipation: Less likely to anticipate Claims 1, 8, or 15 directly, as the primary distinction is the use of optical rather than electrical conductors for the main signal transmission within the cable. However, the general concept of an "active cable" with embedded electronics could be considered a broad precursor to the active Ethernet cable disclosed in US10877233B1.

2. US20130343400A1: Link training and training frame for 100gbps ethernet

   • Full Citation: US20130343400A1 (Lusted Kent C)
   • Publication/Filing Date: Publication: December 26, 2013. Filing: June 22, 2012.
   • Brief Description: This reference pertains to link training and training frames specifically for 100 Gbps Ethernet. It describes mechanisms for adapting transmit-side and receive-side equalization filters to combat channel non-idealities during a training phase. US10877233B1 also discusses a training phase during manufacturing to set initial equalization parameters, and the concept of adapting filter coefficients.
   • Potential Anticipation: Could potentially anticipate aspects of Claims 8 and 15 related to "characterizing channel characteristics... to determine the transmit filter coefficient values" and "programming the DRR devices to use the transmit coefficient values," if the disclosed training methods in US20130343400A1 are interpreted to inherently involve storing these values. However, the explicit "preset pre-equalization" stored in nonvolatile memories and used upon power-on in US10877233B1 differentiates it.

3. US20140086264A1: Method for rapid pma alignment in 100gbase-kp4

   • Full Citation: US20140086264A1 (Lusted Kent C)
   • Publication/Filing Date: Publication: March 27, 2014. Filing: September 24, 2012.
   • Brief Description: This patent application describes a method for rapid Physical Media Attachment (PMA) alignment in 100GBASE-KP4 Ethernet. It deals with lower-level physical layer operations related to signal transmission. While relevant to high-speed Ethernet, it doesn't appear to explicitly disclose the "preset pre-equalization" and storage in nonvolatile memory as a central feature for an active cable's DRR devices.
   • Potential Anticipation: Unlikely to directly anticipate the core claims of US10877233B1 due to its specific focus on PMA alignment rather than the broader concept of preset pre-equalization for active electrical cables.

4. US20140146833A1: Pma-size training frame for 100gbase-kp4

   • Full Citation: US20140146833A1 (Lusted Kent C)
   • Publication/Filing Date: Publication: May 29, 2014. Filing: November 29, 2012.
   • Brief Description: Similar to US20140086264A1, this reference focuses on PMA-size training frames for 100GBASE-KP4. It addresses training mechanisms at a specific layer of the Ethernet standard.
   • Potential Anticipation: Unlikely to directly anticipate the core claims of US10877233B1 for similar reasons as US20140086264A1.

5. US20150334186A1: Coax Adaptor for Ethernet Physical Layer Transceiver

   • Full Citation: US20150334186A1 (Safeciety LLC)
   • Publication/Filing Date: Publication: November 19, 2015. Filing: May 15, 2014.
   • Brief Description: This patent application describes a coax adaptor for an Ethernet Physical Layer Transceiver. It focuses on adapting coaxial cable for Ethernet, which involves different cable characteristics and equalization challenges than the twinaxial or twisted-pair conductors described in US10877233B1.
   • Potential Anticipation: While dealing with physical layer transceivers and equalization, the specific application to a "coax adaptor" may differentiate it from the active Ethernet cable with preset pre-equalization over twin-axial conductors as claimed in US10877233B1.

6. US9322704B1: Composite active optical cables

   • Full Citation: US9322704B1 (Superior Essex International LP)
   • Publication/Filing Date: Publication: April 26, 2016. Filing: October 18, 2013.
   • Brief Description: This patent describes composite active optical cables, again focusing on optical transmission. Like US20070237464A1, it is distinct from the all-electrical nature of the cable in US10877233B1.
   • Potential Anticipation: Unlikely to directly anticipate the claims of US10877233B1 due to the primary use of optical fiber for data transmission.

7. WO2018161273A1: Ethernet link extension method and device

   • Full Citation: WO2018161273A1 (Credo Technology Group Ltd.)
   • Publication/Filing Date: Publication: September 13, 2018. Filing: March 8, 2017.
   • Brief Description: This international patent application, by the same assignee as US10877233B1, describes an "Ethernet link extension method and device." The description of US10877233B1 explicitly refers to this PCT application regarding auto-negotiation implementation. This suggests a related field of invention. The background of US10877233B1 mentions active Ethernet cables with "hard-wired data recovery and remodulation (DRR) chips in the cable connectors" to offer "affordable high-bandwidth data transport."
   • Potential Anticipation: This is a strong candidate for prior art. Given the shared assignee and the description in US10877233B1, it is highly probable that WO2018161273A1 or its national counterparts cover aspects of active Ethernet cables with DRR devices. The extent to which it discloses "preset pre-equalization using transmit filter coefficient values stored in nonvolatile memories" would be key to determining direct anticipation of Claims 1, 8, and 15 of US10877233B1. Further detailed review of WO2018161273A1 would be necessary to confirm exact claim overlap.

8. US20200280329A1: Active 1:N breakout cable

   • Full Citation: US20200280329A1 (Credo Technology Group Limited)
   • Publication/Filing Date: Publication: September 3, 2020. Filing: March 1, 2019.
   • Brief Description: This patent application describes an "Active 1:N breakout cable." Breakout cables are explicitly discussed in US10877233B1 as an embodiment (e.g., FIG. 2). While the filing date is prior to US10877233B1, the publication date is after US10877233B1's priority date (June 21, 2019). Therefore, this would only be prior art if it shares a common earlier priority date with US10877233B1 or if its content predates the invention of US10877233B1 through other means (e.g., public disclosure).
   • Potential Anticipation: Could anticipate aspects related to active breakout cables, which are an embodiment of US10877233B1. The question of whether it specifically discloses "preset pre-equalization using transmit filter coefficient values stored in nonvolatile memories" would be crucial.

9. US20200280458A1: Active ethernet cable

   • Full Citation: US20200280458A1 (Credo Technology Group Limited)
   • Publication/Filing Date: Publication: September 3, 2020. Filing: March 1, 2019.
   • Brief Description: This patent application is also by the same assignee and is titled "Active ethernet cable," directly aligning with the subject matter of US10877233B1. Similar to US20200280329A1, the publication date is after the priority date of US10877233B1.
   • Potential Anticipation: Given the title and shared assignee, this is a very strong candidate for prior art. It likely covers many aspects of active Ethernet cables, and a detailed comparison of its disclosure with the specific claims of US10877233B1 regarding "preset pre-equalization using transmit filter coefficient values stored in nonvolatile memories" would be critical to determine direct anticipation.

Most Relevant Prior Art:

Based on the available information, the following are the most relevant prior art documents:

• WO2018161273A1 (Credo Technology Group Ltd.): This is highly relevant due to the shared assignee and the explicit reference in US10877233B1 to it for auto-negotiation. It likely covers foundational aspects of active Ethernet link extension, which could include the architecture of DRR devices and general equalization strategies. The extent to which it teaches "preset transmit filter coefficients stored in nonvolatile memories" is critical for direct anticipation.
• US20130343400A1 (Lusted Kent C): This reference is relevant for its discussion of link training and adaptation of transmit/receive equalization filters in high-speed Ethernet, which directly relates to the equalization aspects of US10877233B1.
• US20200280458A1 (Credo Technology Group Limited): Although published after the priority date, if it shares an earlier priority date or represents an earlier public disclosure by the same entity, its title "Active ethernet cable" makes it directly relevant to the claimed invention.

A definitive assessment of anticipation would require a detailed claim-by-claim comparison with the full disclosures of these prior art documents.

US patent 10877233 claims a cable, a manufacturing method, and a communications method featuring active Ethernet cables with Data Recovery and Re-modulation (DRR) devices at each end. A core inventive feature lies in these DRR devices providing preset pre-equalization of electrical transit signals using transmit filter coefficient values stored in nonvolatile memories. This aims to enhance performance and reduce receiver-side equalization requirements, especially in high-speed, extended-length cables.

An analysis of prior art reveals combinations that would render the claims of US10877233 obvious to a person having ordinary skill in the art (PHOSITA) under 35 U.S.C. § 103.

Obviousness Combination: WO2018161273A1 (Credo Technology Group Ltd.) in view of US9385897B2 (Avago Technologies)

References:

1. WO2018161273A1: "Ethernet link extension method and device" (Priority Date: March 8, 2017). This PCT application, by the same assignee as US10877233, describes "Ethernet link extension" and "active Ethernet cables" which typically incorporate DRR-like functionality for signal re-timing and re-driving over extended distances. The background of US10877233 itself acknowledges that "Active ethernet cable (AEC) is a newly-designed cable that offers affordable high-bandwidth data transport over distance spans up to at least seven meters using hard-wired data recovery and remodulation (DRR) chips in the cable connectors". The patent further explicitly states that auto-negotiation in its contemplated embodiments "may be implemented as described in PCT/CN2017/075961" (WO2018161273A1). This establishes that active Ethernet cables with DRR devices, converting between host data streams and electrical transit signals, were known in the art, especially to the applicant.
2. US9385897B2: "Methods and apparatus for adapting transmitter equalization coefficients based on receiver gain adaptation" (Priority Date: July 18, 2012). This patent explicitly teaches adaptive transmitter equalization using transmitter equalization coefficients. It describes methods for "adapting transmitter equalization coefficients" and "storing transmitter equalization coefficients in a memory." The abstract of US9385897B2 further states that adaptively setting transmit equalization coefficients can "reduce power consumed by a receive equalizer."

Rationale for Obviousness:

Problem: The background of US10877233 highlights the increasing difficulty in assuring robust performance for per-lane bit rates beyond 50 Gbps over distances more than a couple of meters, noting that "increased channel attenuation and dispersion necessitates increasing levels of equalization, to the point that receiver power consumption and dissipation may reach prohibitive levels." The invention proposes "preset transmit-side equalization to provide enhanced performance and/or to reduce receive-side equalization requirements."

Motivation to Combine: A PHOSITA designing or improving active Ethernet cables (as generally taught by WO2018161273A1) to handle higher data rates and longer distances would be keenly aware of the power consumption challenges associated with extensive receiver-side equalization. US9385897B2 directly addresses this problem by teaching the use of transmit-side equalization with adaptable coefficients as a means to reduce receiver equalizer power consumption.

Therefore, a PHOSITA would have been motivated to combine the active Ethernet cable architecture and DRR functionality of WO2018161273A1 with the transmit-side equalization principles taught by US9385897B2. The goal would be to leverage the power-saving benefits of pre-equalization in the context of active Ethernet cables to overcome the stated power consumption limitations of receive-side equalization. Storing these empirically determined transmit filter coefficient values in nonvolatile memory (as explicitly taught by US9385897B2, "storing transmitter equalization coefficients in a memory") and then retrieving them at power-on (as described in US10877233B1, e.g., MCU loads parameters from Flash memory 207 into DRR's configuration registers 208 at power-on) would be an obvious design choice for a PHOSITA to ensure consistent and optimal cable performance without requiring a full re-training process every time the cable is powered up or re-connected. The process of "characterizing channel characteristics... to determine the transmit filter coefficient values; and storing the transmit filter coefficient values in the nonvolatile memories" after cable assembly (Claims 4, 11, 18 of US10877233) is a standard engineering practice for optimizing the performance of active cables and would be an obvious implementation detail when combining these references.

Specific Claim Elements:

• Claims 1, 8, 15 (DRR devices, electrical conductors, converting data streams): These elements are well-understood functions of active Ethernet cables designed for link extension and would be apparent from WO2018161273A1 and the general state of the art for active cables as acknowledged in US10877233 itself. The description of US10877233 defines DRR devices as performing "clock and data recovery (CDR) and re-modulation of data streams" and processing "data streams traveling in each direction", which is inherent to an "Ethernet link extension method and device".
• Claims 1, 8, 15 (Pre-equalization of electrical transit signals using transmit filter coefficient values): US9385897B2 explicitly teaches "adapting transmitter equalization coefficients" for "transmit equalization."
• Claims 1, 8, 15 (Stored in nonvolatile memories): US9385897B2 teaches "storing transmitter equalization coefficients in a memory." While not explicitly "nonvolatile," selecting nonvolatile memory for persistently storing optimized configuration settings in an active cable device (like a DRR device in WO2018161673A1) would be an obvious engineering choice to ensure that the pre-equalization settings are retained across power cycles and readily available upon boot-up.
• Claims 2, 9, 16 (Controller configures DRR device in response to power-on event, retrieving coefficients): This is an obvious implementation detail for utilizing stored parameters. US10877233 itself describes an MCU (206) that "loads equalization parameters from Flash memory 207 into the DRR device's configuration registers 208" at power-on. This mechanism for loading stored coefficients from memory at power-on to configure the equalization filters would be a routine design choice for a PHOSITA.
• Claims 3, 10, 17 (Programmed to use transmit coefficient values each time power is supplied): This directly flows from storing coefficients in nonvolatile memory and retrieving them at power-on, ensuring consistent performance.
• Claims 4, 11, 18 (Coefficients determined and stored after assembly, characterizing channel characteristics): US9385897B2 teaches "adaptively setting" and "adapting" coefficients, implying a determination process. The step of characterizing the specific cable after assembly to determine optimal equalization parameters and storing them for subsequent use is a logical and common practice in optimizing active cable performance.
• Claims 5, 12, 19 (Receiver-based equalization): US10877233 discusses receiver-based equalization (CTLE, FFE, DFE) in FIG. 4, which is a known technique. The patent states that pre-equalization "enables the use of far fewer taps in the receive filters, potentially enabling the FFE filter to be omitted entirely." Thus, combining transmit-side pre-equalization with (potentially simplified) receiver-based equalization would be an obvious design choice for a PHOSITA aiming for an optimal balance of performance and power efficiency.
• Claims 6, 13 (Twin-axial conductors): Twin-axial conductors are a known type of electrical conductor suitable for differential signals and reducing crosstalk, as described in US10877233, and thus represent an obvious material choice in the field.
• Claims 7, 14, 20 (DRR devices do not perform pre-equalization of host-facing data streams): This implies that pre-equalization is specifically for the internal cable channel, not the host interface, which is consistent with the problem of signal degradation within the cable over extended lengths, and a logical design decision to maintain compliance with host interface standards.

In summary, the combination of active Ethernet cable technology (WO2018161273A1) with known transmit equalization techniques that store coefficients in memory to reduce receiver power (US9385897B2), would lead a PHOSITA to the claimed invention with a reasonable expectation of success to achieve improved power efficiency and robust performance in high-speed, extended-length active Ethernet cables.

Additional Obviousness Consideration: US20200280458A1 (Credo Technology Group Limited)

While not strictly necessary given the strength of the WO2018161273A1 + US9385897B2 combination, US20200280458A1, "Active ethernet cable" (Priority Date: March 1, 2019), is also prior art to US10877233. This patent also from Credo Technology Group Limited, further reinforces the state of the art regarding active Ethernet cables and DRR devices for extending link distances. A PHOSITA would similarly be motivated to apply the transmit equalization teachings of US9385897B2 to the active Ethernet cables described in US20200280458A1 for the same reasons of power efficiency and performance enhancement.

US Patent 10877233 was filed on November 27, 2019, and issued on December 29, 2020.

Patent Term Adjustments (PTA)

Patent Term Adjustment (PTA) is granted to compensate applicants for delays incurred during prosecution before the United States Patent and Trademark Office (USPTO). It generally applies to utility and plant patents issuing from applications filed on or after May 29, 2000. The PTA is calculated automatically at grant, but must be verified by the patentee. While the full text of the patent provides general details about the patent, it does not explicitly state any Patent Term Adjustment awarded to US10877233. The grant of PTA would be indicated on the face of the patent document itself.

Patent Term Extensions (PTE)

Patent Term Extension (PTE) is awarded to compensate for delays incurred in obtaining regulatory approval on a patented product or methods of manufacturing or using the product. This is typically relevant for patents covering pharmaceuticals, medical devices, and similar products requiring pre-market regulatory review. There is no information in the provided patent text or search results to suggest that US10877233 is subject to a Patent Term Extension.

Continuation Applications

A continuation application is a second application for the same invention claimed in a prior, co-pending parent application, without containing any new subject matter. It allows an applicant to pursue additional claims to an invention that were disclosed but not allowed in the parent application, or to pursue a different scope of claims based on the same disclosure. The provided information does not explicitly state if US10877233 is a continuation application or if any continuation applications have been filed from it.

Divisional Applications

A divisional application is filed when the parent application contains more than one distinct invention, typically in response to a "Restriction Requirement" from a USPTO Examiner. Like a continuation, a divisional application cannot contain any new matter and all claims are entitled to the filing date of the parent application. The provided information does not explicitly state if US10877233 is a divisional application or if any divisional applications have been filed from it.

Related Family Members

The patent family for US10877233 includes the following:

• US16/698,935: This is the application number for US10877233B1. [cite: US10877233B1]
• US20210003794A1: This is another publication version of the patent. [cite: US10877233B1]
• CN201910542576.3A (CN112117606A): This is a Chinese application claiming priority from the same priority date (2019-06-21) and shares the title "Active Ethernet cable with preset pre-equalization." [cite: US10877233B1]

Projected Expiration Date

The statutory term for US patents filed on or after June 8, 1995, is generally 20 years from the earliest filing date of the application. For US10877233, the filing date is November 27, 2019. Therefore, without any patent term adjustments, the projected expiration date would be November 27, 2039.

However, a legal event "MAFP - Maintenance fee payment" for the 4th year, large entity, with a free format text of "Anticipated expiration 2039-11-27" is listed. [cite: US10877233B1] This further confirms the expiration date, assuming no PTA or PTE is applied. The patent was subject to a Certificate of Correction on 2026-03-03. [cite: US10877233B1] The information provided does not indicate how this Certificate of Correction might affect the expiration date.

It's important to note that the USPTO does not calculate expiration dates for patents prior to grant, but provides the term on the face of the patent document, including any allowable patent term adjustments, after grant. As the provided data does not explicitly state any PTA, the expiration date remains November 27, 2039.

This Defensive Disclosure document outlines derivative variations of the core inventive concepts disclosed in US Patent 10877233, "Active Ethernet Cable with Preset Pre-Equalization." The aim is to defensively publish these concepts, rendering future incremental improvements by competitors obvious or non-novel by disclosing diverse implementations and applications. The core inventive concept across claims 1, 8, and 15 involves active electrical cables with Data Recovery and Re-modulation (DRR) devices at each end, where these DRR devices perform preset pre-equalization of electrical transit signals using transmit filter coefficient values stored in nonvolatile memories.

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Combination Prior Art Scenarios

Here are at least three scenarios combining the principles of US10877233 with existing open-source standards, demonstrating how a skilled artisan could integrate and extend the invention.

1. Integration with Open Compute Project (OCP) Networking Standards for Data Center Cabling:

   • Description: The active Ethernet cable with preset pre-equalization, as described in US10877233, is implemented within the mechanical and electrical specifications of Open Compute Project (OCP) network cabling, specifically adapting to OCP NIC (Network Interface Card) form factors and interconnect requirements. The nonvolatile memory within the DRR devices stores pre-equalization coefficients optimized not just for the cable length, but also for specific OCP rack topologies and server hardware, as determined by automated characterization processes compliant with OCP test specifications. The cable's embedded microcontroller (MCU 206) exposes management interfaces (e.g., I2C/MDIO as in US10877233, but potentially extended with OCP-defined telemetry protocols) to OCP-compliant switches or servers, allowing for querying of stored equalization profiles, error statistics, and cable health, all while leveraging the fundamental preset pre-equalization for optimal initial link performance upon power-on.
   • Relevance: OCP provides open standards for efficient data center hardware. Integrating active electrical cables with preset pre-equalization directly into this ecosystem would be an obvious step for a PHOSITA seeking to optimize inter-rack or intra-rack connectivity for performance and power efficiency within standardized OCP environments.

2. Implementation with the Gen-Z Interconnect Standard for Memory-Semantic Systems:

   • Description: The active electrical cable, employing DRR devices with preset pre-equalization, is adapted for use as a physical layer interconnect in a Gen-Z fabric. Gen-Z is an open systems interconnect standard providing memory-semantic access to data and devices. The electrical conductors (106) carry Gen-Z packets, and the DRR devices (202, 204) perform the specified pre-equalization using coefficients stored in nonvolatile memory (207). This ensures reliable high-speed, low-latency data transfer across the Gen-Z interconnect, which is crucial for memory-semantic operations. The preset coefficients are determined during manufacturing specifically for the impedance and dispersion characteristics mandated by Gen-Z physical layer specifications over various cable lengths, ensuring plug-and-play operation in a Gen-Z environment without requiring extensive link training upon connection. The management interfaces (e.g., I2C/MDIO) within the DRR device are leveraged to report cable health and loaded pre-equalization profile to a Gen-Z fabric manager.
   • Relevance: Gen-Z demands extremely low latency and high bandwidth for memory-semantic communication. Applying active electrical cables with stable, preset pre-equalization to this standard is an obvious extension for ensuring signal integrity and performance without incurring overhead from dynamic equalization training, thereby meeting the stringent requirements of memory-semantic fabrics.

3. Use with the CAN Bus (Controller Area Network) for Automotive Ethernet Backbones:

   • Description: An active electrical cable with DRR devices and preset pre-equalization, as per US10877233, is specifically engineered to carry Automotive Ethernet (e.g., IEEE 802.3ch, 802.3bp) traffic over a vehicle's high-speed backbone, while coexisting with or encapsulating traditional CAN bus management signals. The DRR devices (202, 204) are designed to operate within automotive environmental specifications (temperature, vibration). The nonvolatile memory (207) stores pre-equalization coefficients specifically tuned for automotive-grade shielded twisted-pair (or twin-axial) cables, accounting for the unique noise and impedance variations encountered in a vehicle. The preset nature of the equalization ensures rapid link-up and consistent performance in safety-critical applications, where predictable network behavior is paramount. The cable's management interface (e.g., I2C/MDIO) is configured to expose diagnostic information that can be accessed via a gateway to the vehicle's CAN bus for central diagnostics and maintenance.
   • Relevance: Automotive networks require robust, reliable, and often high-speed communication. Extending active electrical cable technology with preset pre-equalization to meet Automotive Ethernet standards and interact with existing CAN bus diagnostics is a natural and obvious application for enhancing in-vehicle networking performance, especially for ADAS and infotainment systems.

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Derivative Variations for Core Claims (1, 8, 15)

The following derivative variations expand upon the core inventive concept of US Patent 10877233, particularly focusing on the "preset pre-equalization of electrical transit signals using transmit filter coefficient values stored in nonvolatile memories" within active cable DRR devices. These derivatives apply to the cable apparatus (Claim 1), the manufacturing method (Claim 8), and the communications method (Claim 15).

1. Material & Component Substitution

Derivative 1.1: DRR Devices with On-Die Phase-Change Memory (PCM) and Carbon Nanotube Conductors

• Enabling Description: The Data Recovery and Re-modulation (DRR) devices (202, 204) are fabricated as System-on-Chip (SoC) solutions, integrating the transmit and receive equalization filters, CDR circuits, and an embedded controller (228). Crucially, the nonvolatile memory (207) for storing transmit filter coefficient values is implemented as on-die Phase-Change Memory (PCM). PCM offers byte-addressability, high endurance, and faster read/write speeds than traditional Flash memory, enabling quicker retrieval and potential in-field updates of pre-equalization coefficients. The electrical conductors (106) comprising the cable are manufactured using multi-walled carbon nanotubes (MWCNT) or graphene flakes embedded in a polymer matrix, providing superior conductivity and reduced skin effect at high frequencies compared to traditional copper twinaxial wires, thereby extending effective transmission distances or supporting higher data rates with less pre-equalization effort.

classDiagram
    class DRR_SoC {
        +CDR_Circuit
        +Tx_Equalizer
        +Rx_Equalizer
        +Embedded_Controller
        +OnDie_PCM_Memory<FilterCoeffs>
    }
    class Cable {
        +MWCNT_Graphene_Conductors
    }
    DRR_SoC <--> Cable : Electrical Transit Signals
    DRR_SoC : Store/Retrieve FilterCoeffs

Derivative 1.2: Ferrite-Loaded Connectors with Thermoelectric DRR Cooling

• Enabling Description: The end connector plugs (200, 201) are constructed with integrated ferrite beads or powdered iron cores surrounding the high-speed differential pairs near the DRR devices. These ferrite loads are strategically placed to provide broadband impedance matching and common-mode noise suppression at the connector-to-PCB interface, passively augmenting the pre-equalization by reducing reflected noise and improving signal integrity. Each DRR device (202, 204) is thermally coupled to a miniaturized solid-state thermoelectric cooler (TEC) module, powered by the cable's auxiliary power. The TEC actively manages the DRR device's junction temperature, ensuring stable operation of the high-speed SerDes circuits and consistent performance of the preset pre-equalization filters, particularly in environments with fluctuating ambient temperatures. The nonvolatile memory (207) for coefficients is a high-reliability Magnetic Random-Access Memory (MRAM).

graph TD
    A[Host Port] -- Plug 200 --> B{Ferrite-Loaded Connector}
    B -- PCB Traces --> C[DRR Device with MRAM]
    C -- TEC Module --> D[Heat Sink/Ambient]
    C -- Electrical Transit Signals --> E[Cable Conductors]
    E -- Electrical Transit Signals --> F[DRR Device with MRAM]
    F -- PCB Traces --> G{Ferrite-Loaded Connector}
    G -- Plug 201 --> H[Host Port]
    C -- Power --> TEC(Thermoelectric Cooler)
    F -- Power --> TEC

2. Operational Parameter Expansion

Derivative 2.1: Ultra-High Frequency (UHF) Coaxial Active Cable for Sub-THz Bandwidths

• Enabling Description: The active electrical cable is designed for sub-Terahertz (sub-THz) frequency operation (e.g., 100-300 GHz), enabling multi-terabit-per-second (Tbps) data rates. Instead of traditional twinaxial conductors, the cable utilizes impedance-controlled coaxial lines with dielectric-filled waveguides or specialized micro-coaxial structures to minimize dispersion and attenuation at these extreme frequencies. The DRR devices (202, 204) employ direct RF sampling architectures and integrate custom-designed transmit-side Finite Impulse Response (FIR) pre-equalization filters capable of operating at symbol rates exceeding 100 Giga-Baud, possibly using higher-order PAM (e.g., PAM8 or PAM16) modulation. The preset transmit filter coefficient values are stored in high-density, radiation-hardened nonvolatile memory (e.g., e-Flash or FeRAM) within the DRR ASIC, and are determined during a rigorous manufacturing test phase involving vector network analyzer (VNA) characterization up to 300 GHz.

flowchart TD
    A[Host Device TX] --> B(RF Front End)
    B --> C(Digital Pre-Equalizer)
    C --> D{Tx FIR Filter <br> Coefficients from NVM}
    D --> E(RF Modulator)
    E --> F[UHF Coaxial Cable]
    F --> G(RF Demodulator)
    G --> H(Rx Equalizer)
    H --> I[Host Device RX]
    D -- Preset Coefficients --> J[Nonvolatile Memory]
    J -- Stored during --> K(Manufacturing VNA Test)

Derivative 2.2: Cryogenic Active Cable with Superconducting Interconnects

• Enabling Description: The active electrical cable is engineered for operation within cryogenic environments, specifically at temperatures below 77K (liquid nitrogen) or 4K (liquid helium), for applications such as quantum computing interconnects or sensitive scientific instrumentation. The electrical conductors (106) are made from high-temperature superconducting (HTS) or low-temperature superconducting (LTS) materials, minimizing ohmic losses. The DRR devices (202, 204) are implemented using cryo-CMOS or superconducting electronics (e.g., Rapid Single Flux Quantum, RSFQ) that function reliably at these temperatures. The preset pre-equalization coefficients are stored in specialized cryogenic-compatible nonvolatile memory (e.g., superconducting memory cells) and are optimized to counteract subtle impedance mismatches and dispersion effects that become prominent at quantum scales, as characterized during a cryogenic assembly and test process. The goal is ultra-low power dissipation and maximum signal fidelity in the quantum domain.

stateDiagram
    state "Initialization" as Init
    state "Cryogenic Environment" as CryoEnv
    state "DRR Operating" as DRROp
    state "Coefficient Loading" as CoeffLoad

    Init --> CoeffLoad : Power-On
    CoeffLoad --> DRROp : Coefficients Loaded from CryoNVM
    DRROp --> CryoEnv : Stable Operation
    CryoEnv --> DRROp : Data Flow

    state "Cryogenic Nonvolatile Memory" as CryoNVM {
        [*] --> StoreCoeffs : Manufacturing
        StoreCoeffs --> ReadCoeffs : During Operation
    }

3. Cross-Domain Application

Derivative 3.1: Active Cable for High-Resolution Medical Imaging Data Transfer

• Enabling Description: An active electrical cable (AEC) with preset pre-equalization is adapted for high-bandwidth, real-time data transfer from medical imaging modalities (e.g., 7T MRI scanners, high-resolution CT, PET-CT) to processing workstations or cloud infrastructure. The cable's electrical conductors (106) are designed for low electromagnetic interference (EMI) emission, crucial in sensitive medical environments. The DRR devices (202, 204) and their nonvolatile memories (207) are encapsulated in biocompatible, MRI-compatible shielding materials (e.g., non-ferrous, non-magnetic alloys). The preset transmit filter coefficient values are specifically characterized and stored to maintain maximum signal-to-noise ratio (SNR) and image fidelity over extended cable lengths, compensating for frequency-dependent losses induced by varying medical device interfaces and cable routing within clinical settings. This ensures artifact-free, high-throughput image reconstruction.

sequenceDiagram
    participant MRI_Scanner
    participant AEC_DRR1
    participant AEC_Cable
    participant AEC_DRR2
    participant Workstation

    MRI_Scanner->>AEC_DRR1: Multi-lane Data Stream (Electrical)
    AEC_DRR1->>AEC_DRR1: Convert & Preset Pre-Equalize (Coeffs from NVM)
    AEC_DRR1->>AEC_Cable: Electrical Transit Signals (Low EMI)
    AEC_Cable->>AEC_DRR2: Electrical Transit Signals (Low EMI)
    AEC_DRR2->>AEC_DRR2: Convert (De-Equalize Implicit)
    AEC_DRR2->>Workstation: Multi-lane Data Stream (Electrical)
    Note over AEC_DRR1,AEC_DRR2: Encapsulated in Biocompatible, MRI-Compatible Shielding

Derivative 3.2: Ruggedized Active Cable for Industrial Robotics and Automation

• Enabling Description: The active electrical cable system is engineered for robust operation in harsh industrial environments, connecting robotic manipulators, vision systems, and PLCs (Programmable Logic Controllers) at gigabit Ethernet speeds. The cable jacket (106) is reinforced with aramid fibers and thermoplastic elastomers for enhanced abrasion, chemical, and oil resistance, as well as continuous flex durability. The DRR devices (202, 204) are housed in industrial-grade, IP67-rated connectors (e.g., M12 or RJ45 variants) and operate across an extended temperature range (-40°C to +85°C). The nonvolatile memories (207) store preset pre-equalization coefficients specifically tuned to maintain signal integrity despite dynamic cable movement, electromagnetic interference from industrial machinery, and temperature fluctuations, ensuring reliable, low-latency communication critical for synchronized robotic operations.

graph TD
    A[Robot Arm Sensor] -- High-Speed Ethernet --> B{IP67 Connector + DRR1}
    B -- Harsh Environment <br> Ruggedized Cable --> C{IP67 Connector + DRR2}
    C -- High-Speed Ethernet --> D[Industrial Controller / PLC]
    DRR1 -- Load Coeffs --> NVM1(Nonvolatile Memory)
    DRR2 -- Load Coeffs --> NVM2(Nonvolatile Memory)
    subgraph Cable Segment
        B -- Electrical Transit Signals --> C
    end
    NVM1 --- Preset Coeffs
    NVM2 --- Preset Coeffs

4. Integration with Emerging Tech

Derivative 4.1: AI-Optimized Adaptive Preset Pre-Equalization with Edge-Based Inference

• Enabling Description: The DRR devices (202, 204) incorporate a dedicated, ultra-low-power AI inference engine (e.g., a TinyML accelerator) alongside the embedded controller (228). The nonvolatile memories (207) not only store the initial factory-preset transmit filter coefficients but also multiple alternative coefficient profiles, or a compressed neural network model. The AI engine continuously monitors real-time channel characteristics (e.g., bit error rate, signal margin, eye height) via the DRR's internal SerDes diagnostic features (from registers 208) and uses an inferencing model to dynamically select or fine-tune the most appropriate preset coefficient profile for current environmental conditions (temperature, aging) or application demands. This extends the concept of "preset" to a library of presets, intelligently chosen or adapted at the edge, rather than a single static set, while still maintaining the power-on advantage of pre-stored values.

sequenceDiagram
    participant Cable_Factory
    participant ATE
    participant DRR_AI
    participant Cable_Deployment
    participant Host_Device

    Cable_Factory->>ATE: Characterize Cable
    ATE->>DRR_AI: Store Multiple Preset Profiles (NVM)
    DRR_AI->>DRR_AI: Train Edge AI Model (Offline/Factory)
    Cable_Deployment->>DRR_AI: Power-On
    DRR_AI->>DRR_AI: Load Initial Preset Coeffs from NVM
    loop Real-time Operation
        DRR_AI->>DRR_AI: Monitor Channel (BER, Eye)
        DRR_AI->>DRR_AI: AI Inference (Select/Fine-tune Profile)
        DRR_AI->>DRR_AI: Apply Optimized Preset Coeffs to Tx Filter
    end
    DRR_AI<->>Host_Device: Data Streams

Derivative 4.2: Active Cable with Integrated IoT Sensors and Blockchain for Lifecycle Management

• Enabling Description: The active electrical cable embeds an array of miniature IoT sensors (e.g., temperature, humidity, bending radius, vibration accelerometers) along its length and within the connector bodies. A low-power microcontroller (part of MCU 206 or a dedicated sensor hub) periodically collects data from these sensors. This sensor data, along with critical DRR performance metrics (e.g., actual pre-equalization coefficients used, link training outcomes, error rates), is hashed and periodically appended to a distributed ledger on a private blockchain network accessible by authorized entities. The nonvolatile memory (207) within the DRR devices stores immutable hashes of the factory-programmed preset coefficient values and a unique cable ID, verifiable against the blockchain. This provides an auditable, tamper-evident record of the cable's manufacturing provenance, operational history, and ensures the integrity of its initial preset pre-equalization profile throughout its lifecycle, enhancing trustworthiness in critical infrastructure.

graph TD
    A[Cable Manufacturing] --> B(Store Factory Coeffs & Hash in DRR NVM)
    B --> C(Log Hash & Cable ID to Blockchain)
    subgraph Cable Operation
        D[DRR Device] -- Preset Coeffs --> NVM(Nonvolatile Memory)
        D -- Real-time Data --> E(IoT Sensors <br> (Temp, Bend, Vib))
        E --> F(Sensor Hub / MCU)
        F --> G(Collect & Hash Metrics <br> (Coeffs, BER, Sensor Data))
        G --> H(Append Hash to Blockchain)
    end
    C --- Blockchain[Blockchain Network]
    H --- Blockchain

5. The "Inverse" or Failure Mode

Derivative 5.1: Graceful Degradation to "Basic Link" Mode with Reduced Pre-Equalization

• Enabling Description: The DRR devices (202, 204) are designed to detect various failure modes, particularly related to the nonvolatile memory (207) containing the preset transmit filter coefficients (e.g., memory corruption, inaccessible partitions) or insufficient power supply for full DRR functionality. Upon detection of such a condition, or if a "low-power" or "safety" mode is commanded, the DRR device transitions to a "Basic Link" operational mode. In this mode, the transmit pre-equalization is either disabled entirely, or a pre-defined, minimal, generic set of "failsafe" coefficients (also stored in a separate, highly-redundant NVM segment) is loaded, supporting a reduced data rate (ee.g., 10Gbps instead of 100Gbps). This ensures that a communication link, albeit with limited performance, is maintained, preventing total link failure. An indicator (e.g., LED or management interface flag) signals the degraded mode to the host.

stateDiagram
    state "Power-Off" as Off
    state "Boot-Up" as Boot
    state "Full Performance Mode" as FullPerf
    state "Basic Link Mode" as BasicLink
    state "NVM Fault" as NVM_Fault
    state "Low Power Event" as Low_Power

    Off --> Boot : Power-On
    Boot --> FullPerf : NVM OK, Full Power, Load Preset Coeffs
    Boot --> BasicLink : NVM Fault OR Low Power, Load Failsafe Coeffs
    FullPerf --> BasicLink : Detect NVM Fault / Low Power Event
    FullPerf --> NVM_Fault : NVM Corruption Detected
    FullPerf --> Low_Power : Power Supply Dropout
    NVM_Fault --> BasicLink : Transition to Basic Link
    Low_Power --> BasicLink : Transition to Basic Link
    BasicLink --> FullPerf : Fault Cleared / Power Restored

Derivative 5.2: Self-Contained Diagnostic Loopback Mode for Isolated Debugging

• Enabling Description: Each end connector (100, 101) incorporates a bypass switch (210) that, in a dedicated "Diagnostic Loopback Mode," electrically isolates its respective DRR device (202 or 204) from the host interface and simultaneously connects its center-facing transmitter outputs (set 222) directly to its center-facing receiver inputs (set 222) via on-paddle card traces. In this mode, the DRR device's embedded controller (228) can initiate internal pseudo-random binary sequence (PRBS) pattern generation and transmit it through its own pre-equalization filter (506), loop it back, and analyze the received signal with its receiver (400) without involving the main cable conductors or the remote DRR device. This allows for isolated verification of the preset transmit filter coefficients and overall SerDes functionality, enabling rapid diagnostics of a single connector/DRR unit even if the main cable or remote end is faulty, or if the NVM is suspected of storing incorrect coefficients. The results are stored in NVM (207) for later retrieval via the MCU (206) using a management interface.

graph TD
    A[DRR Device] --> B{Tx Filter 506}
    B -- CH_OUT --> C{Bypass Switch 210}
    C -- Loopback Trace --> D{Rx Filter 400}
    D -- CH_IN --> A
    A -- NVM Coeffs --> E[Nonvolatile Memory 207]
    A -- Internal PRBS Gen --> B
    A -- Internal Analyzer --> D
    C -- In Diagnostic Loopback Mode --> C