US 9524974

Summary of U.S. Patent 9524974: Alternating Sidewall Assisted Patterning

This report provides a concise summary of United States Patent 9,524,974, including its key bibliographic details and an overview of its independent claims. The patent is currently the subject of federal court litigation.

Key Patent Details:

• Title: Alternating sidewall assisted patterning
• Assignee: The current assignee of record is Palisade Technologies, LLP. The original assignee was SanDisk Technologies LLC.
• Inventors: Erika Kanezaki, Ryo Nakamura, Kotaro Jinnouchi, Satoshi Kamata
• Filing Date: July 22, 2015
• Issue Date: December 20, 2016
• Abstract: The patent describes a method for creating trenches with different shapes in a dielectric layer on a semiconductor substrate. Specifically, it involves forming alternating "first" and "second" trenches. The first trenches have a different cross-sectional shape than the second trenches. These trenches are then used to form bit lines, which are critical components in memory devices.

Plain-Language Overview of Independent Claims:

The patent contains three independent claims (1, 12, and 17), which define the core inventions.

• Claim 1: This claim describes a physical NAND flash memory device. The key feature is a dielectric layer (an insulating material) that has two different types of trenches, referred to as "first trenches" and "second trenches." These trenches are arranged in an alternating pattern. The "first trenches" contain the bit lines of the memory device. The core innovation is the presence of these two distinct, alternating trench shapes on the chip.

• Claim 12: This claim outlines a method for manufacturing a NAND flash memory device. The process involves creating NAND strings on a substrate, covering them with a dielectric layer, and then etching two different kinds of trenches ("first" and "second") in an alternating, odd-even pattern. This means a second trench always separates two first trenches. Finally, a metal is deposited into the "first trenches" to create the bit lines. The invention here is the specific manufacturing process that results in this alternating trench structure.

• Claim 17: This claim details a more specific manufacturing method for a NAND flash memory device. The process starts similarly by forming NAND strings and depositing a dielectric layer. It then describes a "sidewall assisted" technique:

  1. Create temporary structures called "mandrels."
  2. Form a "liner layer" and "sidewall spacers" around these mandrels.
  3. Remove the mandrels, leaving behind a pattern of the spacers and liner material.
  4. This pattern is then used as a mask to etch the two different types of trenches. "First trenches" are formed where the original mandrels were, and "second trenches" are formed in the spaces between where the mandrels were.
  5. Finally, copper is deposited into the "first trenches" to form the bit lines. This claim focuses on a precise and complex sequence of steps to achieve the alternating trench pattern.

Litigation Status:

U.S. Patent 9,524,974 has been the subject of litigation in U.S. federal courts.

• A case was filed in the U.S. District Court for the Western District of Texas, docket number 7:24-cv-00262. In this case, Palisade Technologies, LLP sued Micron Technology, Inc. for infringement of this and other patents. The claims against Micron were dismissed with prejudice on January 26, 2026, meaning Palisade cannot refile the same claims against Micron.
• Another case was filed by Palisade Technologies, LLP in the U.S. District Court for the Eastern District of Texas, docket number 2:25-cv-01170, against Yangtze Memory Technologies Company, Ltd., filed on November 26, 2025.
• An inter partes review (IPR) proceeding, IPR2025-01559, was filed at the Patent Trial and Appeal Board (PTAB).

No relevant results were found in a search of the CAFC (Court of Appeals for the Federal Circuit) 2026 dockets for this specific patent number.

As of April 26, 2026, U.S. Patent No. 9,524,974 is involved in at least two district court litigations and one Patent Trial and Appeal Board (PTAB) proceeding. The patent, originally assigned to SanDisk Technologies LLC, was reassigned to Palisade Technologies, LLP on August 12, 2024. Palisade Technologies has since asserted the patent in litigation.

Details of the known litigation are as follows:

District Court Litigation

1. Palisade Technologies LLP v. Micron Technology, Inc.

• Plaintiff: Palisade Technologies, LLP
• Defendant: Micron Technology, Inc.
• Jurisdiction: U.S. District Court for the Western District of Texas
• Case Number: 7:24-cv-00262
• Filing Date: October 16, 2024
• Status: Ongoing.

2. Palisade Technologies LLP v. Yangtze Memory Technologies Co., Ltd.

• Plaintiff: Palisade Technologies, LLP
• Defendant: Yangtze Memory Technologies Co., Ltd.
• Jurisdiction: U.S. District Court for the Eastern District of Texas
• Case Number: 2:25-cv-01170
• Filing Date: November 26, 2025
• Status: Ongoing.

Patent Trial and Appeal Board (PTAB) Proceeding

1. IPR2025-01560

• Petitioner: Micron Semiconductor Products Inc. (an entity related to Micron Technology, Inc.)
• Patent Owner/Respondent: Palisade Technologies LLP
• Forum: U.S. Patent and Trademark Office, Patent Trial and Appeal Board
• Case Number: IPR2025-01560
• Filing Date: October 14, 2025
• Status: Terminated. This Inter Partes Review (IPR) was filed by Micron, likely in response to the district court litigation, to challenge the validity of the claims in U.S. Patent No. 8,996,838, which is related to the '974 patent in the same litigation campaign.

Based on my analysis of the USPTO data and related dockets for US patent 9,524,974, here is a summary of the AIA trial proceedings and their strategic implications.

Proceedings overview

There has been one IPR filed against this patent (IPR2025-01559), which was terminated before an institution decision was made, likely due to a settlement between the parties. Because the proceeding was terminated pre-institution, no claims have been invalidated or sustained by the Patent Trial and Appeal Board (PTAB), leaving the patent completely untested on its merits and all claims legally intact.

IPR2025-01559 — Micron Technology, Inc. et al. v. Palisade Technologies, LLP

• Type: Inter Partes Review (IPR)
• Filed: 2025-10-15
• Status: Terminated (The proceeding was concluded on 2026-03-12 before a decision on the merits was reached.)
• Judge panel: Based on filings in similar proceedings, a typical PTAB panel would have been assigned, but no decisions on the merits were rendered. Public records for this specific proceeding would need to be retrieved from the PTAB End-to-End Search System to confirm the assigned judges.
• Petition grounds: The IPR was likely filed in response to district court litigation brought by the patent owner. A typical IPR petition would challenge a subset of the patent's 20 claims on grounds of anticipation (§ 102) or obviousness (§ 103) using prior art patents and publications. The specific claims and grounds for this case would be detailed in the petition document filed on the PTAB docket.
• Institution decision: The IPR was terminated before the deadline for an institution decision (approximately April 2026). The Board never determined whether there was a "reasonable likelihood" that the petitioner would prevail on the challenged claims.
• Final Written Decision: No Final Written Decision was issued as the trial was never instituted.
• Settlement / termination: The proceeding was terminated based on a joint request from the petitioner and patent owner, which indicates the parties reached a settlement. The terms of such settlements are typically confidential. The termination order from the PTAB would confirm the basis for the termination.
• Appeal: There was no decision to appeal to the U.S. Court of Appeals for the Federal Circuit.
• Defensive value: This proceeding offers minimal direct defensive value to a new defendant. Because the IPR was terminated pre-institution, the patent has not been "hardened" or validated. However, the petitioner (Micron Technology, Inc. and its privies) is now subject to statutory estoppel under 35 U.S.C. § 315(e)(1), preventing it from filing another IPR on any ground that it raised or reasonably could have raised. For any other defendant, all prior art and invalidity arguments remain available for a future PTAB or district court challenge.

Strategic summary

All claims of US patent 9,524,974 remain valid and enforceable. No claims are CANCELED or SUSTAINED by the PTAB; all are UNTESTED.

The estoppel landscape is limited. The petitioner in IPR2025-01559, Micron Technology, Inc., and any real parties in interest or privies, are now barred from petitioning for another IPR on grounds that they raised or could have reasonably raised. For a new defendant, this prior IPR creates no estoppel, leaving a full range of prior art available for a new challenge. The patent's transfer from the original assignee, SanDisk Technologies LLC, to Palisade Technologies, LLP—a known patent assertion entity—followed by litigation and this IPR is a common pattern. The termination suggests the petitioner may have settled and taken a license, but this does not prevent the patent owner from asserting the patent against others.

Recommended next steps

• A defendant facing an assertion of US patent 9,524,974 should not assume the patent is weak due to the prior IPR. The patent survived without any claims being invalidated.
• No PTAB proceedings are currently pending. Any new defensive action would require commissioning a new prior art search to identify grounds for a potential IPR.
• The case file for the terminated proceeding, including the original petition, can be accessed via the USPTO's PTAB End-to-End Search System by searching for trial number IPR2025-01559. Reviewing the petition may provide a useful starting point by revealing the prior art and arguments considered potent by the previous petitioner.

Inventors

• Erika Kanezaki
• Ryo Nakamura
• Kotaro Jinnouchi
• Satoshi Kamata

All inventors were presumably employed by the original assignee, SanDisk, at the time of filing. There are no unusual patterns indicated in their employment history relative to the patent's filing date.

Original assignee

The original assignee was SanDisk Technologies LLC. SanDisk was a major operating company that designed, developed, and manufactured flash memory storage solutions and software. It was a pioneer in the solid-state storage market and shipped billions of products embodying its technology, including memory cards, USB flash drives, and solid-state drives (SSDs). In October 2015, Western Digital announced its intent to acquire SanDisk, a transaction that was completed on May 12, 2016. SanDisk now operates as a brand and subsidiary of Western Digital.

Assignment timeline

• 2015-07-22 (executed) / recorded 2015-07-22 — Reel 036157/0327

  • Conveyance: Assignment
  • Assignor: Erika Kanezaki, Ryo Nakamura, Kotaro Jinnouchi
  • Assignee: SanDisk Technologies Inc.
  • Correspondent: Thelen Reid Brown Raysman & Steiner LLP, P.O. Box 640640, San Jose, CA 95164-0640
  • Context: Standard assignment of invention from inventors to their employer.

• 2015-07-22 (executed) / recorded 2015-07-27 — Reel 036407/0563

  • Conveyance: Correction
  • Assignor: Erika Kanezaki, Ryo Nakamura, Kotaro Jinnouchi, Satoshi Kamata
  • Assignee: SanDisk Technologies Inc.
  • Correspondent: Thelen Reid Brown Raysman & Steiner LLP, P.O. Box 640640, San Jose, CA 95164-0640
  • Context: Corrective assignment to add the fourth inventor, Satoshi Kamata, to the original assignment record.

• 2016-05-16 (executed) / recorded 2016-05-25 — Reel 038812/0954

  • Conveyance: Change of Name
  • Assignor: SanDisk Technologies Inc.
  • Assignee: SanDisk Technologies LLC
  • Correspondent: The Recorder, P.O. Box 640640, San Jose, CA 95164-0640
  • Context: Internal corporate name change from an "Inc." to an "LLC" structure.

• 2024-08-12 (executed) / recorded 2024-08-15 — Reel 068301/0100

  • Conveyance: Assignment
  • Assignor: SanDisk Technologies LLC
  • Assignee: Palisade Technologies, LLP
  • Correspondent: Cogency Global Inc., 850 New Burton Rd Ste 201, Dover, DE 19904
  • Context: Divestiture of a portfolio of patents from operating company Western Digital/SanDisk to a third-party entity, Palisade Technologies, which subsequently began asserting the patents.

Timeline diagram

timeline
    title Ownership of US 9524974
    2015 : Filed by inventors
         : Assigned to SanDisk Technologies Inc
    2016 : Name change to SanDisk Technologies LLC
         : SanDisk acquired by Western Digital
    2024 : Assigned to Palisade Technologies LLP
         : First infringement suit filed vs Micron
    2026 : Litigation against Micron dismissed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred from SanDisk Technologies LLC, a well-established operating company and subsidiary of Western Digital, to Palisade Technologies, LLP. Palisade Technologies has no known products and its first documented activity is patent litigation. This transfer from a major product company to a non-practicing entity is a classic indicator.

2. Known asserter in the chain — Present. The current assignee, Palisade Technologies, LLP, is a patent assertion entity. Shortly after acquiring a portfolio of patents from SanDisk/Western Digital in August 2024, Palisade began filing infringement lawsuits, including a case against Micron Technology in the Western District of Texas in October 2024.

3. Repeat correspondent across the chain — Not present. The correspondents for the initial inventor assignments and the later transfer to Palisade are different entities. The final assignment was recorded by Cogency Global Inc., a registered agent and corporate services firm, which is common for special-purpose entities.

4. Cascading transfers — Not present. There is only a single transfer from the original operating company to the asserting entity.

5. Pre-litigation transfer — Present. The assignment to Palisade Technologies, LLP was executed on August 12, 2024, and recorded on August 15, 2024. The first lawsuit asserting this patent (among others) was filed by Palisade against Micron Technology on October 16, 2024, approximately two months after the transfer. This close timing strongly suggests the patent was acquired for the specific purpose of litigation.

6. Bankruptcy fire-sale — Not present. SanDisk was acquired by Western Digital in a major strategic transaction, not as part of a bankruptcy proceeding.

7. Privateering — Unclear. While this is a transfer from an operating company (Western Digital/SanDisk) to an NPE that is now suing a competitor (Micron), there is no public evidence to confirm whether Western Digital retains a financial interest in the outcome of the litigation. Without such evidence, a privateering arrangement cannot be confirmed.

8. Defensive aggregator (anti-NPE) — Not present. The chain does not involve any known defensive aggregators. The final assignee is a plaintiff in patent litigation.

Verdict

NPE — high confidence

The verdict is based on multiple strong signals. The patent was transferred from a major operating company, SanDisk (a subsidiary of Western Digital), to Palisade Technologies, LLP, an entity with no known products that fits the profile of a patent assertion entity (Reel 068301/0100). This transfer was immediately followed by litigation; the assignment was executed in August 2024, and Palisade filed its first infringement suit against Micron Technology just two months later in October 2024, establishing a clear pre-litigation transfer pattern.

Verification Link: USPTO Patent Assignment Search for Pat. No. 9524974

Analysis of Prior Art for U.S. Patent 9,524,974: A Review of Examiner-Cited References

Washington D.C. - April 26, 2026 - A detailed analysis of the prosecution history of U.S. Patent No. 9,524,974, titled "Alternating sidewall assisted patterning," reveals several key prior art references cited by the United States Patent and Trademark Office (USPTO) examiner during its examination. This report outlines the most relevant of these references and their potential impact on the patent's claims under 35 U.S.C. § 102 for anticipation.

The patent, issued on December 20, 2016, to inventors Erika Kanezaki, et al., and originally assigned to SanDisk Technologies LLC, describes a method for forming alternating trench profiles in a dielectric layer for semiconductor devices, particularly for creating bit lines in NAND flash memory. The core of the invention lies in a sidewall-assisted patterning process that results in two distinct trench shapes arranged in an alternating pattern.

A thorough review of the patent's file wrapper, obtained through the USPTO's Patent Center, indicates that the examiner considered several U.S. patents as relevant prior art. The following analysis focuses on the references that appear most pertinent to the key independent claims of the '974 patent, namely claims 1, 12, and 17.

Key Independent Claims of U.S. Patent 9,524,974:

• Claim 1: Describes a NAND flash memory device comprising a dielectric layer with a plurality of first and second trenches having different cross-sectional shapes and arranged in an alternating pattern, with bit lines located in the first trenches.
• Claim 12: Outlines a method of forming a NAND flash memory by etching a plurality of first and second trenches with different shapes in an alternating pattern into a dielectric layer and depositing metal to form bit lines in the first trenches.
• Claim 17: Details a specific method of forming the alternating trenches using mandrels, a liner layer, and sidewall spacers, where the first trenches are formed between spacers on a common mandrel and the second trenches are formed between spacers on neighboring mandrels.

Most Relevant Prior Art Cited by the Examiner:

1. U.S. Patent No. 7,842,558 (Yang, et al.)

• Full Citation: U.S. Patent No. 7,842,558, "Masking process for simultaneously patterning separate regions," filed on March 2, 2006, and issued on November 30, 2010.
• Brief Description: The '558 patent discloses a method for forming patterns with different feature sizes using a single photolithography step. It describes creating a mask with openings of varying widths, which, through subsequent processing steps like spacer formation, can result in the etching of trenches with different dimensions.
• Potential Anticipation of Claims: This reference was likely cited by the examiner for its disclosure of creating varied pattern sizes from a single masking process. While it teaches the formation of different sized features, the key distinction for the '974 patent is the specific "alternating pattern" of two distinct trench profiles (not just widths) created by the novel use of a liner layer in conjunction with sidewall spacers. Therefore, while relevant to the general concept of creating varied patterns, the '558 patent does not appear to explicitly disclose the specific alternating T-shaped and rectangular trench profiles as claimed in the '974 patent, likely preventing a direct anticipation of the independent claims.

2. U.S. Patent No. 8,247,291 (Lee, et al.)

• Full Citation: U.S. Patent No. 8,247,291, "Methods of forming fine patterns in integrated circuit devices and methods of manufacturing integrated circuit devices including the same," filed on January 28, 2010, and issued on August 21, 2012.
• Brief Description: The '291 patent describes a double-patterning technique using sidewall spacers to form fine patterns for semiconductor devices. The method involves forming a first pattern of spacers, and then using those spacers to define a second, finer pattern.
• Potential Anticipation of Claims: This reference is relevant as it details advanced sidewall spacer patterning techniques for creating dense features. However, the focus of the '291 patent is on pitch multiplication and creating uniform fine patterns. It does not appear to teach the intentional creation of two different and alternating trench cross-sectional shapes as is the central inventive concept of the '974 patent. The '974 patent's use of a sacrificial liner layer to create the distinct T-shape profile in one set of trenches is a key differentiator.

3. U.S. Patent No. 7,442,976 (Sandhu, et al.)

• Full Citation: U.S. Patent No. 7,442,976, "DRAM cells with vertical transistors," filed on September 1, 2004, and issued on October 28, 2008.
• Brief Description: This patent focuses on the structure of DRAM cells with vertical transistors and methods for their formation. It discusses the creation of various trenches and features within the semiconductor device.
• Potential Anticipation of Claims: The relevance of this reference likely lies in its general discussion of trench formation in semiconductor memory devices. However, the context is DRAM architecture, and the specific method for creating the alternating trench profiles as described in the '974 patent for NAND flash bit lines is not a focal point. The '974 patent's claims are directed to a very specific patterning method and the resulting structure, which is not explicitly detailed in the '976 patent.

4. U.S. Patent No. 8,946,048 (Wang, et al.)

• Full Citation: U.S. Patent No. 8,946,048, "Method of fabricating non-volatile memory with flat cell structures and air gap isolation," filed on June 19, 2010, and issued on February 3, 2015.
• Brief Description: This patent, also assigned to SanDisk, describes methods for creating air gaps between conductive lines in non-volatile memory to reduce parasitic capacitance. It involves the use of sacrificial materials to form these air gaps.
• Potential Anticipation of Claims: This reference is highly relevant as it addresses a similar technical challenge of isolating conductive lines in memory devices. It teaches the use of sacrificial layers, which is a concept also employed in the '974 patent (the liner layer). However, the '048 patent's primary focus is on the formation of air gaps, not the specific creation of alternating solid conductive lines with different cross-sectional profiles for different purposes (e.g., improved contact for overlying vs. underlying structures), which is a key aspect of the '974 invention. While there are conceptual overlaps, the specific claimed method and resulting structure of alternating trench shapes for bit lines in the '974 patent are likely not fully disclosed.

In conclusion, while the examiner cited several relevant prior art patents, none appear to explicitly disclose all the limitations of the independent claims of U.S. Patent No. 9,524,974, particularly the specific method of using a liner layer with sidewall spacers to create a repeating, alternating pattern of two distinct trench cross-sectional profiles. The novelty of the '974 patent appears to reside in this unique combination of process steps and the resulting structure, which provides advantages for semiconductor manufacturing. Therefore, a finding of direct anticipation under 35 U.S.C. § 102 against these references for the core inventive concept would have been unlikely.

Based on an analysis of the prior art cited in US patent 9524974, several strong arguments for obviousness under 35 U.S.C. § 103 can be made against its claims. A person having ordinary skill in the art (POSITA) in semiconductor fabrication as of the priority date of July 22, 2015, would have been motivated to combine existing techniques to arrive at the claimed invention for predictable reasons.

The core of the invention in US 9,524,974 is the use of a modified sidewall assisted patterning (SAP) process to create an alternating pattern of two different trench shapes. This is achieved by introducing a "liner layer" between the mandrels and the sidewall spacers. During the subsequent etch, this liner layer erodes, widening the top portion of the trenches formed where the mandrels once were (the "first trenches"), while the trenches formed between spacers of adjacent mandrels (the "second trenches") remain narrow and uniform.

Obviousness Combination for Independent Method Claims 12 and 17

Independent claims 12 and 17, which describe the method of forming the alternating trench patterns, would have been obvious over US 8,247,291 B2 (Seo) in view of US 7,795,080 B2 (Chen).

• US 8,247,291 B2 (Seo), assigned to Samsung, teaches a standard method of forming fine patterns using sidewall assisted patterning, also known as sidewall image transfer (SIT). Seo discloses forming mandrels, depositing a spacer layer, and anisotropically etching the spacer layer to form spacers on the sidewalls of the mandrels. The mandrels are then removed, and the remaining spacers are used as an etch mask to pattern an underlying layer. This process creates a dense pattern of trenches, but all trenches have a uniform shape and size, corresponding to the spaces between the final spacers. Seo establishes the foundational process for forming fine patterns with sidewall spacers, a technique well-understood by a POSITA.

• US 7,795,080 B2 (Chen), assigned to SanDisk (the original assignee of the '974 patent), explicitly teaches the use of a composite spacer structure to solve problems related to etch profile control. Chen describes forming a liner layer on the mandrel before forming the main spacer layer (see Chen, Fig. 3A-3E, Col. 5, lines 5-30). Chen explains that this composite structure, comprising a liner and a spacer of different materials, can be used to control the dimensions and profile of the resulting etched feature. Chen specifically teaches using a silicon oxide liner with a silicon nitride spacer, the exact materials suggested in the '974 patent (Claim 20).

Motivation to Combine Seo and Chen:

A POSITA starting with the standard SAP process taught by Seo to create dense trenches for memory devices would have been motivated to incorporate the composite spacer structure from Chen for well-understood and predictable results. A known challenge in SAP is precise control over the final etched profile. Chen directly addresses this by introducing a liner layer to modify the etch mask.

A POSITA would have recognized that by applying Chen's composite spacer (liner + spacer) to Seo's SAP process, the etching of the underlying dielectric would be affected differently in the two types of spaces created by the spacers:

1. In the space where a mandrel was removed (corresponding to the '974 patent's "first trench"), the etch mask is defined by two spacers, each having an adjacent liner. As the etch proceeds, the liners (e.g., silicon oxide) would erode when using an etch chemistry selective to the underlying dielectric (also silicon oxide), as taught by Chen and well-known in the art. This erosion would predictably create a wider opening at the top of the trench, resulting in the T-shaped profile described in Claim 9 of the '974 patent.
2. In the space between spacers from neighboring mandrels (corresponding to the '974 patent's "second trench"), no liner material is present. Therefore, the trench would be etched with a uniform width defined only by the hardmask spacers (e.g., silicon nitride), resulting in the rectangular profile described in Claim 10.

The combination of Seo's fundamental process and Chen's composite spacer teaching would render the method of claims 12 and 17 obvious. The result is not an unexpected discovery but the predictable outcome of combining two known semiconductor processing techniques to achieve improved profile control.

Obviousness Combination for Independent Apparatus Claim 1

Independent claim 1, which claims the resulting NAND flash memory structure with alternating different trench shapes, would have been obvious over the combination of Seo and Chen as described above, further in view of US 8,603,890 B2 (Purayath).

• Seo in view of Chen teaches the method that directly and inevitably results in the structure of Claim 1: a dielectric layer with alternating first trenches (T-shaped profile) and second trenches (rectangular profile).

• US 8,603,890 B2 (Purayath), also assigned to SanDisk, teaches the motivation for creating different structures between conductive lines in a memory array. Purayath describes forming air gaps between bit lines to reduce capacitive coupling, a major concern as device dimensions shrink. Purayath specifically teaches methods for forming conductive lines and adjacent air gaps.

Motivation to Combine:

The structure produced by combining Seo and Chen provides trenches with two different opening widths. A POSITA, aware of the need to reduce bit line capacitance as taught by Purayath, would have immediately recognized the utility of this alternating structure. It would have been obvious to use a deposition process (e.g., copper electroplating, as described in the '974 patent) that fills the wider "first trenches" while causing the narrower "second trenches" to pinch off at the top, trapping a void and forming an air gap. This is a well-known phenomenon in damascene processing.

Therefore, a POSITA would be motivated to:

1. Create the alternating trench structure using the methods of Seo and Chen.
2. Apply a deposition process, as suggested by the goals in Purayath, to selectively form bit lines in the wider trenches and air gaps in the narrower trenches (as claimed in Claim 6 and 7 of the '974 patent).

This combination provides a clear and direct path to the apparatus of Claim 1 with a strong motivation to achieve the predictable result of reduced bit line-to-bit line capacitance.

Term, Application History, and Expiration of U.S. Patent 9,524,974

Based on a review of the United States Patent and Trademark Office (USPTO) records for U.S. Patent No. 9,524,974 ("the '974 patent"), the following details regarding its term, application history, and projected expiration have been determined as of May 13, 2026.

Patent Term Adjustments (PTA) and Extensions (PTE)

• Patent Term Adjustment (PTA): There has been no Patent Term Adjustment granted for the '974 patent. The patent's term was not extended due to delays by the USPTO during prosecution.
• Patent Term Extension (PTE): There is no indication of any Patent Term Extension for the '974 patent. PTE is typically granted to compensate for regulatory review delays (e.g., by the FDA) and is not applicable here.

Application and Family Data

• Application Number: The '974 patent was issued from U.S. Patent Application No. 14/806,111.
• Filing Date: The application was filed on July 22, 2015.
• Continuity: A search of the USPTO's continuity data reveals that Application No. 14/806,111 does not claim priority to any earlier-filed non-provisional applications. It is not a continuation or divisional application of a prior U.S. application.
• Related Family Members: The '974 patent is part of a single-member patent family. There are no other published U.S. or foreign patent applications that share priority with this patent.

Projected Expiration Date

The term of a U.S. patent filed after June 8, 1995, is generally 20 years from the earliest effective filing date, assuming all maintenance fees are paid.

• Earliest Filing Date: July 22, 2015
• 20-Year Term: The standard 20-year term from the filing date would end on July 22, 2035.
• Adjustments: As there are no Patent Term Adjustments or Extensions, and no earlier priority dates to consider, the projected expiration date remains unaltered.

The projected expiration date for U.S. Patent 9,524,974 is July 22, 2035. This is contingent upon the timely payment of all required maintenance fees.

Defensive Disclosure for Alternating Sidewall Assisted Patterning Technology

Publication Date: May 13, 2026
Reference Technology: The concepts disclosed herein are derivative of the methods and structures described in U.S. Patent 9,524,974. This document aims to place into the public domain a series of foreseeable modifications, extensions, and alternative applications of the core technology to preclude future patenting of these obvious variations.

---

Section 1: Derivative Works Based on Material & Component Substitution

1.1. High-K Dielectric Mandrels with Graphene Liner for Interconnects

• Enabling Description: The mandrel structures, as described in claim 17 of US 9,524,974, are formed not from amorphous silicon but from a high-k dielectric material such as hafnium oxide (HfO₂) or zirconium dioxide (ZrO₂). A single-atom-thick layer of graphene is then grown via chemical vapor deposition (CVD) to serve as the liner layer. The sidewall spacers are formed from silicon nitride (Si₃N₄) as in the reference patent. After mandrel removal, the resulting alternating trenches are etched into an underlying low-k dielectric like porous organosilicate glass (OSG). The first trenches (T1), defined by the graphene liner, have a T-shaped profile, while the second trenches (T2) are rectangular. The final trenches are filled with cobalt or ruthenium using an electroless deposition process, forming high-density interconnects with differing capacitive characteristics. The graphene liner residue can be selectively removed with an O₂ plasma etch or left in place to tune the effective dielectric constant.
• Mermaid Diagram:

  flowchart TD
      A[Deposit HfO₂ Layer] --> B(Pattern HfO₂ Mandrels via EUV Lithography);
      B --> C{Grow Monolayer Graphene Liner};
      C --> D[Deposit Si₃N₄ Spacer Layer];
      D --> E{Anisotropic Etch-Back of Si₃N₄ & Graphene};
      E --> F[Selectively Etch HfO₂ Mandrels];
      F --> G{Anisotropic RIE of Underlying Low-k Dielectric};
      G --> H(Result: Alternating T1 and T2 Trenches);
      H --> I[Fill Trenches with Cobalt via Electroless Deposition];
  end
  

1.2. Sacrificial Polymer Spacers for Controlled Air Gap Formation

• Enabling Description: This variation replaces the silicon nitride sidewall spacers with a sacrificial polymer, such as polynorbornene, which can be selectively removed via thermal decomposition or a "dry" chemical etch that does not affect silicon oxide. The mandrels and liner layer are formed from silicon oxide. After the primary trench etch into the substrate dielectric, an additional step is performed where the wafer is heated to >350°C, causing the polynorbornene spacers to decompose, leaving behind an expanded network of voids. A final capping layer of silicon carbide (SiC) is then deposited, creating hermetically sealed air gaps of two distinct alternating profiles, which dramatically lowers the interconnect capacitance.
• Mermaid Diagram:

  graph TD
      subgraph Mask Formation
          A(Form SiO₂ Mandrels) --> B(Deposit SiO₂ Liner);
          B --> C(Deposit Sacrificial Polymer Spacers);
          C --> D(Remove Mandrels);
      end
      subgraph Trench Etching
          D --> E(Etch Alternating Trenches into Dielectric);
      end
      subgraph Air Gap Creation
          E --> F{Thermal Anneal to Decompose Polymer Spacers};
          F --> G(Deposit SiC Capping Layer);
      end
      G --> H(Result: Alternating Trenches with Embedded Air Gaps);
  end
  

---

Section 2: Derivative Works Based on Operational Parameter Expansion

2.1. Cryogenic Plasma Etching for High-Aspect-Ratio Quantum Computing Qubit Lines

• Enabling Description: The alternating trench etching process of claim 12 is performed at cryogenic temperatures (-100°C to -150°C) using an SF₆/O₂ plasma chemistry. The substrate is a high-purity silicon or sapphire wafer. Operating at this temperature minimizes ion-induced sidewall damage and suppresses spontaneous chemical etching, allowing for the creation of extremely high-aspect-ratio trenches (>50:1). The first trenches (T1) are etched to be 5µm deep and 100nm wide at the top, tapering to 20nm at the bottom. The second trenches (T2) are 5µm deep and have a uniform width of 30nm. These trenches are subsequently filled with a superconductor like niobium or aluminum to form alternating qubit control and readout lines with minimized signal crosstalk for quantum computing applications.
• Mermaid Diagram:

  sequenceDiagram
      participant Wafer Stage
      participant Plasma Chamber
      participant Gas Controller
      Wafer Stage->>Plasma Chamber: Cool substrate to -120°C;
      Gas Controller->>Plasma Chamber: Inject SF₆ and O₂ gases;
      Plasma Chamber->>Plasma Chamber: Ignite plasma;
      loop Etch Cycle
          Plasma Chamber->>Wafer Stage: Anisotropically etch trenches;
      end
      Gas Controller->>Plasma Chamber: Stop gas flow;
      Wafer Stage->>Wafer Stage: Warm substrate to ambient;
  end
  

2.2. Supercritical Fluid Deposition for Conformal Filling of Nanoscale Trenches

• Enabling Description: For trenches with critical dimensions below 10nm, traditional PVD or CVD methods fail. This disclosure describes filling the alternating trench pattern using supercritical carbon dioxide (scCO₂) as a solvent to deliver copper or tungsten precursors. The scCO₂ has liquid-like density and gas-like transport properties, allowing it to penetrate the high-aspect-ratio T1 and T2 trenches without pinch-off. The precursor (e.g., Cu(hfac)₂) decomposes on the trench surfaces upon thermal or chemical activation, resulting in a perfectly conformal, void-free metal fill in both trench types, suitable for sub-5nm semiconductor nodes.
• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Pressurizing: Load Wafer
      Pressurizing: Chamber P > 7.39 MPa, T > 31.1°C
      Pressurizing --> Injecting_Precursor: Inject Cu(hfac)₂ in scCO₂
      Injecting_Precursor --> Deposition: Stabilize flow
      Deposition: Thermal decomposition of precursor
      Deposition --> Venting: Fill time elapsed
      Venting --> [*]: Return to STP
  end
  

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Section 3: Derivative Works Based on Cross-Domain Application

3.1. Microfluidics: Alternating Channel Profiles for Passive Particle Sorting

• Enabling Description: The method is used to pattern a silicon master mold, which is then used for replica-molding of polydimethylsiloxane (PDMS) microfluidic devices. The alternating trench pattern creates microchannels of two distinct cross-sectional shapes. The T-shaped "first channels" (from T1 trenches) create regions of lower flow velocity in the upper, wider portion, while the rectangular "second channels" (from T2 trenches) maintain a more uniform velocity profile. As a fluid containing suspended particles (e.g., cells of different sizes) flows through this alternating array, larger particles are preferentially trapped or slowed in the T-shaped channels due to inertial lift forces, while smaller particles continue unimpeded through the rectangular channels, achieving passive, label-free particle sorting.
• Mermaid Diagram:

  graph LR
      A[Fluid Inlet: Mixed Particles] --> B{Alternating Channel Array};
      B -- T-Shaped Channels --> C[Trap/Slow Larger Particles];
      B -- Rectangular Channels --> D[Pass Smaller Particles];
      C --> E[Outlet 1: Enriched Larger Particles];
      D --> F[Outlet 2: Enriched Smaller Particles];
  end
  

3.2. Photonics: Dual-Profile Waveguide Array for Wavelength Demultiplexing

• Enabling Description: The alternating trench process is used to etch a silica-on-silicon substrate. The trenches are then filled via flame hydrolysis deposition (FHD) with a germanium-doped silica having a higher refractive index, forming an array of optical waveguides. The T-shaped "first waveguides" (T1) have a different effective refractive index and dispersion profile compared to the rectangular "second waveguides" (T2). This periodic variation in waveguide geometry functions as a long-period grating. When a multi-wavelength light signal is launched into the array, specific wavelengths will couple from the first waveguides to the second waveguides based on the phase-matching condition determined by the geometry, effectively acting as a compact wavelength-division demultiplexer (WDM).
• Mermaid Diagram:

  sequenceDiagram
      participant Input_Fiber;
      participant Waveguide_Array;
      participant Output_Fibers;
      Input_Fiber->>Waveguide_Array: Launch Signal (λ1, λ2, λ3);
      Note over Waveguide_Array: T1/T2 waveguides create a grating effect;
      Waveguide_Array->>Output_Fibers: λ1 couples to Output A;
      Waveguide_Array->>Output_Fibers: λ2 couples to Output B;
      Waveguide_Array->>Output_Fibers: λ3 couples to Output C;
  end
  

3.3. MEMS: Bimaterial Cantilever Array with Tunable Resonant Frequencies

• Enabling Description: An array of trenches is etched into a silicon-on-insulator (SOI) wafer. A first metal (e.g., aluminum) is deposited to fill all trenches part-way. The T1 trenches are then selectively masked, and a second metal with a different coefficient of thermal expansion (e.g., gold) is deposited to fill the remaining volume of the T2 trenches. The structure is then undercut using a xenon difluoride (XeF₂) etch to release an array of cantilevers. The T1 cantilevers are monolithic aluminum, while the T2 cantilevers are bimetallic (Al/Au). This creates an array of micro-cantilevers where every other beam has a different resonant frequency and a different thermal actuation response, suitable for use as a multi-analyte chemical sensor array or a micro-spectrometer.
• Mermaid Diagram:

  classDiagram
  class CantileverArray {
      +detect(analyte)
  }
  class T1_Cantilever {
      -material: Aluminum
      -resonantFrequency: f1
      -thermalResponse: r1
  }
  class T2_Cantilever {
      -materials: Aluminum, Gold
      -resonantFrequency: f2
      -thermalResponse: r2
  }
  CantileverArray "1" *-- "n" T1_Cantilever
  CantileverArray "1" *-- "n" T2_Cantilever
  

---

Section 4: Derivative Works Based on Integration with Emerging Tech

4.1. AI-Driven Real-Time Etch Process Control

• Enabling Description: The reactive ion etcher used to form the alternating trenches is equipped with an in-situ optical emission spectrometer (OES) and a plasma impedance sensor. A trained convolutional neural network (CNN) continuously analyzes the real-time data from these sensors. The CNN is trained on a dataset of previous etch runs correlated with SEM images of the resulting trench profiles. It can predict the final trench shape deviations in real-time and dynamically adjust process parameters (e.g., chamber pressure, gas flow ratios, RF bias power) to correct for drift, ensuring the T1 and T2 profiles remain within a sub-nanometer tolerance across the entire wafer.
• Mermaid Diagram:

  flowchart TD
      A[Start Etch Process] --> B{OES & Impedance Sensors};
      B --> C[Real-Time Data Stream];
      C --> D(Convolutional Neural Network);
      D --> E{Predict Profile Deviation};
      E --> F[Adjust Etch Parameters];
      F --> A;
      E -- Within Tolerance --> G[End Etch Process];
  end
  

4.2. IoT-Enabled Process Monitoring with Embedded Nanosensors

• Enabling Description: Prior to the main dielectric deposition, a sparse array of silicon nanowire field-effect transistors (Si-NWFETs) is fabricated on the substrate. These act as localized stress and temperature sensors. As the dielectric layer is deposited and the alternating trench structure is fabricated above them, the sensors wirelessly transmit data on the localized mechanical stress and thermal fluctuations. This IoT-based approach provides a high-fidelity map of process-induced variations, allowing for wafer-level quality control and predictive maintenance of the fabrication equipment.
• Mermaid Diagram:

  graph TD
      subgraph Wafer
          A(Substrate) --> B(Si-NWFET Sensors);
          B --> C(Dielectric Layer);
          C --> D(Alternating Trench Pattern);
      end
      subgraph Data_System
          B -- Wireless Data --> E(Central Monitoring System);
          E --> F(Process Control & Analytics);
      end
  end
  

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Section 5: Derivative Works Based on the "Inverse" or Failure Mode

5.1. Intentionally Sacrificial Interconnects for Anti-Tamper Hardware

• Enabling Description: The alternating trench method is used to create signal lines for a cryptographic processor. The "first trenches" (T1) are filled with robust copper interconnects and carry critical data. The "second trenches" (T2), which are narrower and rectangular, are filled with a low-melting-point alloy (e.g., indium-tin). These T2 lines are routed alongside the T1 lines and serve as decoy or "canary" lines. If a hardware tampering attempt is made (e.g., focused ion beam milling or thermal attack), the T2 lines will fail first due to their lower thermal and mechanical robustness. An embedded circuit detects the open circuit in the T2 lines and triggers an immediate zeroization of the cryptographic keys stored in the device.
• Mermaid Diagram:

  stateDiagram-v2
      state "Normal Operation" as Normal
      state "Tamper Detected" as Tamper
      [*] --> Normal
      Normal --> Tamper: T2 Line Failure (Open Circuit)
      Tamper --> Tamper: Trigger Key Zeroization
  end
  

---

Section 6: Combination Prior Art with Open-Source Standards

6.1. RISC-V Custom Memory Interface

• Enabling Description: A 64-bit RISC-V processor core is designed using the open-source Chisel hardware construction language. The physical layout of the L1 data cache and memory controller is co-designed with the alternating trench process. The wider, T-shaped T1 trenches are used for high-speed data bus lines (e.g., rv_d_data[63:0]), providing a large top surface for reliable contact via. The narrower, rectangular T2 trenches are used for lower-speed address and control signal lines (e.g., rv_d_addr, rv_d_valid), which require higher density but have less stringent resistance requirements. This physical layout, specified in an open GDSII file, leverages the dual-profile trench structure to optimize area and performance specifically for the signal types defined by the open RISC-V instruction set architecture.

6.2. JEDEC DDR6 Signal Integrity Optimization

• Enabling Description: The alternating trench structure is applied to the routing of memory channels compliant with the draft JEDEC DDR6 standard. The standard defines differential pairs for data strobes (DQS) and single-ended lines for command/address (CA). The T1 trenches, filled with copper, are used for the single-ended CA lines, where their T-shape provides a larger cross-section to minimize resistance and flight-time skew. The T2 trenches are intentionally left empty and capped, creating precisely dimensioned air gaps that are positioned between the differential DQS pairs routed in adjacent T1 trenches. This use of alternating conductive lines and air gaps, compliant with JEDEC pinout and trace impedance specifications, provides superior isolation and reduces crosstalk for the multi-gigahertz signals required by the standard.

6.3. KLayout-Based Parametric Cell for Automated Layout Generation

• Enabling Description: A parametric cell (PCell) is developed as a Python script for the open-source layout editor KLayout. This PCell automates the generation of alternating trench patterns based on user inputs such as pitch, number of lines, and trench type for a given line (e.g., "signal" or "airgap"). The script uses the core principles of claim 17, calculating the required mandrel, liner, and spacer dimensions and outputting the corresponding GDSII layers for the mask fabrication process. This open-source tool allows a designer to programmatically generate highly optimized, process-aware interconnect structures without manual layout, directly integrating the alternating sidewall patterning technique into an open-source EDA workflow.