Prior art

Analysis of Prior Art for U.S. Patent 9,524,974: A Review of Examiner-Cited References

Washington D.C. - April 26, 2026 - A detailed analysis of the prosecution history of U.S. Patent No. 9,524,974, titled "Alternating sidewall assisted patterning," reveals several key prior art references cited by the United States Patent and Trademark Office (USPTO) examiner during its examination. This report outlines the most relevant of these references and their potential impact on the patent's claims under 35 U.S.C. § 102 for anticipation.

The patent, issued on December 20, 2016, to inventors Erika Kanezaki, et al., and originally assigned to SanDisk Technologies LLC, describes a method for forming alternating trench profiles in a dielectric layer for semiconductor devices, particularly for creating bit lines in NAND flash memory. The core of the invention lies in a sidewall-assisted patterning process that results in two distinct trench shapes arranged in an alternating pattern.

A thorough review of the patent's file wrapper, obtained through the USPTO's Patent Center, indicates that the examiner considered several U.S. patents as relevant prior art. The following analysis focuses on the references that appear most pertinent to the key independent claims of the '974 patent, namely claims 1, 12, and 17.

Key Independent Claims of U.S. Patent 9,524,974:

• Claim 1: Describes a NAND flash memory device comprising a dielectric layer with a plurality of first and second trenches having different cross-sectional shapes and arranged in an alternating pattern, with bit lines located in the first trenches.
• Claim 12: Outlines a method of forming a NAND flash memory by etching a plurality of first and second trenches with different shapes in an alternating pattern into a dielectric layer and depositing metal to form bit lines in the first trenches.
• Claim 17: Details a specific method of forming the alternating trenches using mandrels, a liner layer, and sidewall spacers, where the first trenches are formed between spacers on a common mandrel and the second trenches are formed between spacers on neighboring mandrels.

Most Relevant Prior Art Cited by the Examiner:

1. U.S. Patent No. 7,842,558 (Yang, et al.)

• Full Citation: U.S. Patent No. 7,842,558, "Masking process for simultaneously patterning separate regions," filed on March 2, 2006, and issued on November 30, 2010.
• Brief Description: The '558 patent discloses a method for forming patterns with different feature sizes using a single photolithography step. It describes creating a mask with openings of varying widths, which, through subsequent processing steps like spacer formation, can result in the etching of trenches with different dimensions.
• Potential Anticipation of Claims: This reference was likely cited by the examiner for its disclosure of creating varied pattern sizes from a single masking process. While it teaches the formation of different sized features, the key distinction for the '974 patent is the specific "alternating pattern" of two distinct trench profiles (not just widths) created by the novel use of a liner layer in conjunction with sidewall spacers. Therefore, while relevant to the general concept of creating varied patterns, the '558 patent does not appear to explicitly disclose the specific alternating T-shaped and rectangular trench profiles as claimed in the '974 patent, likely preventing a direct anticipation of the independent claims.

2. U.S. Patent No. 8,247,291 (Lee, et al.)

• Full Citation: U.S. Patent No. 8,247,291, "Methods of forming fine patterns in integrated circuit devices and methods of manufacturing integrated circuit devices including the same," filed on January 28, 2010, and issued on August 21, 2012.
• Brief Description: The '291 patent describes a double-patterning technique using sidewall spacers to form fine patterns for semiconductor devices. The method involves forming a first pattern of spacers, and then using those spacers to define a second, finer pattern.
• Potential Anticipation of Claims: This reference is relevant as it details advanced sidewall spacer patterning techniques for creating dense features. However, the focus of the '291 patent is on pitch multiplication and creating uniform fine patterns. It does not appear to teach the intentional creation of two different and alternating trench cross-sectional shapes as is the central inventive concept of the '974 patent. The '974 patent's use of a sacrificial liner layer to create the distinct T-shape profile in one set of trenches is a key differentiator.

3. U.S. Patent No. 7,442,976 (Sandhu, et al.)

• Full Citation: U.S. Patent No. 7,442,976, "DRAM cells with vertical transistors," filed on September 1, 2004, and issued on October 28, 2008.
• Brief Description: This patent focuses on the structure of DRAM cells with vertical transistors and methods for their formation. It discusses the creation of various trenches and features within the semiconductor device.
• Potential Anticipation of Claims: The relevance of this reference likely lies in its general discussion of trench formation in semiconductor memory devices. However, the context is DRAM architecture, and the specific method for creating the alternating trench profiles as described in the '974 patent for NAND flash bit lines is not a focal point. The '974 patent's claims are directed to a very specific patterning method and the resulting structure, which is not explicitly detailed in the '976 patent.

4. U.S. Patent No. 8,946,048 (Wang, et al.)

• Full Citation: U.S. Patent No. 8,946,048, "Method of fabricating non-volatile memory with flat cell structures and air gap isolation," filed on June 19, 2010, and issued on February 3, 2015.
• Brief Description: This patent, also assigned to SanDisk, describes methods for creating air gaps between conductive lines in non-volatile memory to reduce parasitic capacitance. It involves the use of sacrificial materials to form these air gaps.
• Potential Anticipation of Claims: This reference is highly relevant as it addresses a similar technical challenge of isolating conductive lines in memory devices. It teaches the use of sacrificial layers, which is a concept also employed in the '974 patent (the liner layer). However, the '048 patent's primary focus is on the formation of air gaps, not the specific creation of alternating solid conductive lines with different cross-sectional profiles for different purposes (e.g., improved contact for overlying vs. underlying structures), which is a key aspect of the '974 invention. While there are conceptual overlaps, the specific claimed method and resulting structure of alternating trench shapes for bit lines in the '974 patent are likely not fully disclosed.

In conclusion, while the examiner cited several relevant prior art patents, none appear to explicitly disclose all the limitations of the independent claims of U.S. Patent No. 9,524,974, particularly the specific method of using a liner layer with sidewall spacers to create a repeating, alternating pattern of two distinct trench cross-sectional profiles. The novelty of the '974 patent appears to reside in this unique combination of process steps and the resulting structure, which provides advantages for semiconductor manufacturing. Therefore, a finding of direct anticipation under 35 U.S.C. § 102 against these references for the core inventive concept would have been unlikely.