Derivative works — US Patent 9524974

Defensive Disclosure for Alternating Sidewall Assisted Patterning Technology

Publication Date: May 13, 2026
Reference Technology: The concepts disclosed herein are derivative of the methods and structures described in U.S. Patent 9,524,974. This document aims to place into the public domain a series of foreseeable modifications, extensions, and alternative applications of the core technology to preclude future patenting of these obvious variations.

Section 1: Derivative Works Based on Material & Component Substitution

1.1. High-K Dielectric Mandrels with Graphene Liner for Interconnects

Enabling Description: The mandrel structures, as described in claim 17 of US 9,524,974, are formed not from amorphous silicon but from a high-k dielectric material such as hafnium oxide (HfO₂) or zirconium dioxide (ZrO₂). A single-atom-thick layer of graphene is then grown via chemical vapor deposition (CVD) to serve as the liner layer. The sidewall spacers are formed from silicon nitride (Si₃N₄) as in the reference patent. After mandrel removal, the resulting alternating trenches are etched into an underlying low-k dielectric like porous organosilicate glass (OSG). The first trenches (T1), defined by the graphene liner, have a T-shaped profile, while the second trenches (T2) are rectangular. The final trenches are filled with cobalt or ruthenium using an electroless deposition process, forming high-density interconnects with differing capacitive characteristics. The graphene liner residue can be selectively removed with an O₂ plasma etch or left in place to tune the effective dielectric constant.

Mermaid Diagram:

flowchart TD
    A[Deposit HfO₂ Layer] --> B(Pattern HfO₂ Mandrels via EUV Lithography);
    B --> C{Grow Monolayer Graphene Liner};
    C --> D[Deposit Si₃N₄ Spacer Layer];
    D --> E{Anisotropic Etch-Back of Si₃N₄ & Graphene};
    E --> F[Selectively Etch HfO₂ Mandrels];
    F --> G{Anisotropic RIE of Underlying Low-k Dielectric};
    G --> H(Result: Alternating T1 and T2 Trenches);
    H --> I[Fill Trenches with Cobalt via Electroless Deposition];
end

1.2. Sacrificial Polymer Spacers for Controlled Air Gap Formation

Enabling Description: This variation replaces the silicon nitride sidewall spacers with a sacrificial polymer, such as polynorbornene, which can be selectively removed via thermal decomposition or a "dry" chemical etch that does not affect silicon oxide. The mandrels and liner layer are formed from silicon oxide. After the primary trench etch into the substrate dielectric, an additional step is performed where the wafer is heated to >350°C, causing the polynorbornene spacers to decompose, leaving behind an expanded network of voids. A final capping layer of silicon carbide (SiC) is then deposited, creating hermetically sealed air gaps of two distinct alternating profiles, which dramatically lowers the interconnect capacitance.

Mermaid Diagram:

graph TD
    subgraph Mask Formation
        A(Form SiO₂ Mandrels) --> B(Deposit SiO₂ Liner);
        B --> C(Deposit Sacrificial Polymer Spacers);
        C --> D(Remove Mandrels);
    end
    subgraph Trench Etching
        D --> E(Etch Alternating Trenches into Dielectric);
    end
    subgraph Air Gap Creation
        E --> F{Thermal Anneal to Decompose Polymer Spacers};
        F --> G(Deposit SiC Capping Layer);
    end
    G --> H(Result: Alternating Trenches with Embedded Air Gaps);
end

Section 2: Derivative Works Based on Operational Parameter Expansion

2.1. Cryogenic Plasma Etching for High-Aspect-Ratio Quantum Computing Qubit Lines

Enabling Description: The alternating trench etching process of claim 12 is performed at cryogenic temperatures (-100°C to -150°C) using an SF₆/O₂ plasma chemistry. The substrate is a high-purity silicon or sapphire wafer. Operating at this temperature minimizes ion-induced sidewall damage and suppresses spontaneous chemical etching, allowing for the creation of extremely high-aspect-ratio trenches (>50:1). The first trenches (T1) are etched to be 5µm deep and 100nm wide at the top, tapering to 20nm at the bottom. The second trenches (T2) are 5µm deep and have a uniform width of 30nm. These trenches are subsequently filled with a superconductor like niobium or aluminum to form alternating qubit control and readout lines with minimized signal crosstalk for quantum computing applications.

Mermaid Diagram:

sequenceDiagram
    participant Wafer Stage
    participant Plasma Chamber
    participant Gas Controller
    Wafer Stage->>Plasma Chamber: Cool substrate to -120°C;
    Gas Controller->>Plasma Chamber: Inject SF₆ and O₂ gases;
    Plasma Chamber->>Plasma Chamber: Ignite plasma;
    loop Etch Cycle
        Plasma Chamber->>Wafer Stage: Anisotropically etch trenches;
    end
    Gas Controller->>Plasma Chamber: Stop gas flow;
    Wafer Stage->>Wafer Stage: Warm substrate to ambient;
end

2.2. Supercritical Fluid Deposition for Conformal Filling of Nanoscale Trenches

Enabling Description: For trenches with critical dimensions below 10nm, traditional PVD or CVD methods fail. This disclosure describes filling the alternating trench pattern using supercritical carbon dioxide (scCO₂) as a solvent to deliver copper or tungsten precursors. The scCO₂ has liquid-like density and gas-like transport properties, allowing it to penetrate the high-aspect-ratio T1 and T2 trenches without pinch-off. The precursor (e.g., Cu(hfac)₂) decomposes on the trench surfaces upon thermal or chemical activation, resulting in a perfectly conformal, void-free metal fill in both trench types, suitable for sub-5nm semiconductor nodes.

Mermaid Diagram:

stateDiagram-v2
    [*] --> Pressurizing: Load Wafer
    Pressurizing: Chamber P > 7.39 MPa, T > 31.1°C
    Pressurizing --> Injecting_Precursor: Inject Cu(hfac)₂ in scCO₂
    Injecting_Precursor --> Deposition: Stabilize flow
    Deposition: Thermal decomposition of precursor
    Deposition --> Venting: Fill time elapsed
    Venting --> [*]: Return to STP
end

Section 3: Derivative Works Based on Cross-Domain Application

3.1. Microfluidics: Alternating Channel Profiles for Passive Particle Sorting

Enabling Description: The method is used to pattern a silicon master mold, which is then used for replica-molding of polydimethylsiloxane (PDMS) microfluidic devices. The alternating trench pattern creates microchannels of two distinct cross-sectional shapes. The T-shaped "first channels" (from T1 trenches) create regions of lower flow velocity in the upper, wider portion, while the rectangular "second channels" (from T2 trenches) maintain a more uniform velocity profile. As a fluid containing suspended particles (e.g., cells of different sizes) flows through this alternating array, larger particles are preferentially trapped or slowed in the T-shaped channels due to inertial lift forces, while smaller particles continue unimpeded through the rectangular channels, achieving passive, label-free particle sorting.

Mermaid Diagram:

graph LR
    A[Fluid Inlet: Mixed Particles] --> B{Alternating Channel Array};
    B -- T-Shaped Channels --> C[Trap/Slow Larger Particles];
    B -- Rectangular Channels --> D[Pass Smaller Particles];
    C --> E[Outlet 1: Enriched Larger Particles];
    D --> F[Outlet 2: Enriched Smaller Particles];
end

3.2. Photonics: Dual-Profile Waveguide Array for Wavelength Demultiplexing

Enabling Description: The alternating trench process is used to etch a silica-on-silicon substrate. The trenches are then filled via flame hydrolysis deposition (FHD) with a germanium-doped silica having a higher refractive index, forming an array of optical waveguides. The T-shaped "first waveguides" (T1) have a different effective refractive index and dispersion profile compared to the rectangular "second waveguides" (T2). This periodic variation in waveguide geometry functions as a long-period grating. When a multi-wavelength light signal is launched into the array, specific wavelengths will couple from the first waveguides to the second waveguides based on the phase-matching condition determined by the geometry, effectively acting as a compact wavelength-division demultiplexer (WDM).

Mermaid Diagram:

sequenceDiagram
    participant Input_Fiber;
    participant Waveguide_Array;
    participant Output_Fibers;
    Input_Fiber->>Waveguide_Array: Launch Signal (λ1, λ2, λ3);
    Note over Waveguide_Array: T1/T2 waveguides create a grating effect;
    Waveguide_Array->>Output_Fibers: λ1 couples to Output A;
    Waveguide_Array->>Output_Fibers: λ2 couples to Output B;
    Waveguide_Array->>Output_Fibers: λ3 couples to Output C;
end

3.3. MEMS: Bimaterial Cantilever Array with Tunable Resonant Frequencies

Enabling Description: An array of trenches is etched into a silicon-on-insulator (SOI) wafer. A first metal (e.g., aluminum) is deposited to fill all trenches part-way. The T1 trenches are then selectively masked, and a second metal with a different coefficient of thermal expansion (e.g., gold) is deposited to fill the remaining volume of the T2 trenches. The structure is then undercut using a xenon difluoride (XeF₂) etch to release an array of cantilevers. The T1 cantilevers are monolithic aluminum, while the T2 cantilevers are bimetallic (Al/Au). This creates an array of micro-cantilevers where every other beam has a different resonant frequency and a different thermal actuation response, suitable for use as a multi-analyte chemical sensor array or a micro-spectrometer.

Mermaid Diagram:

classDiagram
class CantileverArray {
    +detect(analyte)
}
class T1_Cantilever {
    -material: Aluminum
    -resonantFrequency: f1
    -thermalResponse: r1
}
class T2_Cantilever {
    -materials: Aluminum, Gold
    -resonantFrequency: f2
    -thermalResponse: r2
}
CantileverArray "1" *-- "n" T1_Cantilever
CantileverArray "1" *-- "n" T2_Cantilever

Section 4: Derivative Works Based on Integration with Emerging Tech

4.1. AI-Driven Real-Time Etch Process Control

Enabling Description: The reactive ion etcher used to form the alternating trenches is equipped with an in-situ optical emission spectrometer (OES) and a plasma impedance sensor. A trained convolutional neural network (CNN) continuously analyzes the real-time data from these sensors. The CNN is trained on a dataset of previous etch runs correlated with SEM images of the resulting trench profiles. It can predict the final trench shape deviations in real-time and dynamically adjust process parameters (e.g., chamber pressure, gas flow ratios, RF bias power) to correct for drift, ensuring the T1 and T2 profiles remain within a sub-nanometer tolerance across the entire wafer.

Mermaid Diagram:

flowchart TD
    A[Start Etch Process] --> B{OES & Impedance Sensors};
    B --> C[Real-Time Data Stream];
    C --> D(Convolutional Neural Network);
    D --> E{Predict Profile Deviation};
    E --> F[Adjust Etch Parameters];
    F --> A;
    E -- Within Tolerance --> G[End Etch Process];
end

4.2. IoT-Enabled Process Monitoring with Embedded Nanosensors

Enabling Description: Prior to the main dielectric deposition, a sparse array of silicon nanowire field-effect transistors (Si-NWFETs) is fabricated on the substrate. These act as localized stress and temperature sensors. As the dielectric layer is deposited and the alternating trench structure is fabricated above them, the sensors wirelessly transmit data on the localized mechanical stress and thermal fluctuations. This IoT-based approach provides a high-fidelity map of process-induced variations, allowing for wafer-level quality control and predictive maintenance of the fabrication equipment.

Mermaid Diagram:

graph TD
    subgraph Wafer
        A(Substrate) --> B(Si-NWFET Sensors);
        B --> C(Dielectric Layer);
        C --> D(Alternating Trench Pattern);
    end
    subgraph Data_System
        B -- Wireless Data --> E(Central Monitoring System);
        E --> F(Process Control & Analytics);
    end
end

Section 5: Derivative Works Based on the "Inverse" or Failure Mode

5.1. Intentionally Sacrificial Interconnects for Anti-Tamper Hardware

Enabling Description: The alternating trench method is used to create signal lines for a cryptographic processor. The "first trenches" (T1) are filled with robust copper interconnects and carry critical data. The "second trenches" (T2), which are narrower and rectangular, are filled with a low-melting-point alloy (e.g., indium-tin). These T2 lines are routed alongside the T1 lines and serve as decoy or "canary" lines. If a hardware tampering attempt is made (e.g., focused ion beam milling or thermal attack), the T2 lines will fail first due to their lower thermal and mechanical robustness. An embedded circuit detects the open circuit in the T2 lines and triggers an immediate zeroization of the cryptographic keys stored in the device.

Mermaid Diagram:

stateDiagram-v2
    state "Normal Operation" as Normal
    state "Tamper Detected" as Tamper
    [*] --> Normal
    Normal --> Tamper: T2 Line Failure (Open Circuit)
    Tamper --> Tamper: Trigger Key Zeroization
end

Section 6: Combination Prior Art with Open-Source Standards

6.1. RISC-V Custom Memory Interface

Enabling Description: A 64-bit RISC-V processor core is designed using the open-source Chisel hardware construction language. The physical layout of the L1 data cache and memory controller is co-designed with the alternating trench process. The wider, T-shaped T1 trenches are used for high-speed data bus lines (e.g., rv_d_data[63:0]), providing a large top surface for reliable contact via. The narrower, rectangular T2 trenches are used for lower-speed address and control signal lines (e.g., rv_d_addr, rv_d_valid), which require higher density but have less stringent resistance requirements. This physical layout, specified in an open GDSII file, leverages the dual-profile trench structure to optimize area and performance specifically for the signal types defined by the open RISC-V instruction set architecture.

6.2. JEDEC DDR6 Signal Integrity Optimization

Enabling Description: The alternating trench structure is applied to the routing of memory channels compliant with the draft JEDEC DDR6 standard. The standard defines differential pairs for data strobes (DQS) and single-ended lines for command/address (CA). The T1 trenches, filled with copper, are used for the single-ended CA lines, where their T-shape provides a larger cross-section to minimize resistance and flight-time skew. The T2 trenches are intentionally left empty and capped, creating precisely dimensioned air gaps that are positioned between the differential DQS pairs routed in adjacent T1 trenches. This use of alternating conductive lines and air gaps, compliant with JEDEC pinout and trace impedance specifications, provides superior isolation and reduces crosstalk for the multi-gigahertz signals required by the standard.

6.3. KLayout-Based Parametric Cell for Automated Layout Generation

Enabling Description: A parametric cell (PCell) is developed as a Python script for the open-source layout editor KLayout. This PCell automates the generation of alternating trench patterns based on user inputs such as pitch, number of lines, and trench type for a given line (e.g., "signal" or "airgap"). The script uses the core principles of claim 17, calculating the required mandrel, liner, and spacer dimensions and outputting the corresponding GDSII layers for the mask fabrication process. This open-source tool allows a designer to programmatically generate highly optimized, process-aware interconnect structures without manual layout, directly integrating the alternating sidewall patterning technique into an open-source EDA workflow.