Obviousness

Based on an analysis of the prior art cited in US patent 9524974, several strong arguments for obviousness under 35 U.S.C. § 103 can be made against its claims. A person having ordinary skill in the art (POSITA) in semiconductor fabrication as of the priority date of July 22, 2015, would have been motivated to combine existing techniques to arrive at the claimed invention for predictable reasons.

The core of the invention in US 9,524,974 is the use of a modified sidewall assisted patterning (SAP) process to create an alternating pattern of two different trench shapes. This is achieved by introducing a "liner layer" between the mandrels and the sidewall spacers. During the subsequent etch, this liner layer erodes, widening the top portion of the trenches formed where the mandrels once were (the "first trenches"), while the trenches formed between spacers of adjacent mandrels (the "second trenches") remain narrow and uniform.

Obviousness Combination for Independent Method Claims 12 and 17

Independent claims 12 and 17, which describe the method of forming the alternating trench patterns, would have been obvious over US 8,247,291 B2 (Seo) in view of US 7,795,080 B2 (Chen).

• US 8,247,291 B2 (Seo), assigned to Samsung, teaches a standard method of forming fine patterns using sidewall assisted patterning, also known as sidewall image transfer (SIT). Seo discloses forming mandrels, depositing a spacer layer, and anisotropically etching the spacer layer to form spacers on the sidewalls of the mandrels. The mandrels are then removed, and the remaining spacers are used as an etch mask to pattern an underlying layer. This process creates a dense pattern of trenches, but all trenches have a uniform shape and size, corresponding to the spaces between the final spacers. Seo establishes the foundational process for forming fine patterns with sidewall spacers, a technique well-understood by a POSITA.

• US 7,795,080 B2 (Chen), assigned to SanDisk (the original assignee of the '974 patent), explicitly teaches the use of a composite spacer structure to solve problems related to etch profile control. Chen describes forming a liner layer on the mandrel before forming the main spacer layer (see Chen, Fig. 3A-3E, Col. 5, lines 5-30). Chen explains that this composite structure, comprising a liner and a spacer of different materials, can be used to control the dimensions and profile of the resulting etched feature. Chen specifically teaches using a silicon oxide liner with a silicon nitride spacer, the exact materials suggested in the '974 patent (Claim 20).

Motivation to Combine Seo and Chen:

A POSITA starting with the standard SAP process taught by Seo to create dense trenches for memory devices would have been motivated to incorporate the composite spacer structure from Chen for well-understood and predictable results. A known challenge in SAP is precise control over the final etched profile. Chen directly addresses this by introducing a liner layer to modify the etch mask.

A POSITA would have recognized that by applying Chen's composite spacer (liner + spacer) to Seo's SAP process, the etching of the underlying dielectric would be affected differently in the two types of spaces created by the spacers:

1. In the space where a mandrel was removed (corresponding to the '974 patent's "first trench"), the etch mask is defined by two spacers, each having an adjacent liner. As the etch proceeds, the liners (e.g., silicon oxide) would erode when using an etch chemistry selective to the underlying dielectric (also silicon oxide), as taught by Chen and well-known in the art. This erosion would predictably create a wider opening at the top of the trench, resulting in the T-shaped profile described in Claim 9 of the '974 patent.
2. In the space between spacers from neighboring mandrels (corresponding to the '974 patent's "second trench"), no liner material is present. Therefore, the trench would be etched with a uniform width defined only by the hardmask spacers (e.g., silicon nitride), resulting in the rectangular profile described in Claim 10.

The combination of Seo's fundamental process and Chen's composite spacer teaching would render the method of claims 12 and 17 obvious. The result is not an unexpected discovery but the predictable outcome of combining two known semiconductor processing techniques to achieve improved profile control.

Obviousness Combination for Independent Apparatus Claim 1

Independent claim 1, which claims the resulting NAND flash memory structure with alternating different trench shapes, would have been obvious over the combination of Seo and Chen as described above, further in view of US 8,603,890 B2 (Purayath).

• Seo in view of Chen teaches the method that directly and inevitably results in the structure of Claim 1: a dielectric layer with alternating first trenches (T-shaped profile) and second trenches (rectangular profile).

• US 8,603,890 B2 (Purayath), also assigned to SanDisk, teaches the motivation for creating different structures between conductive lines in a memory array. Purayath describes forming air gaps between bit lines to reduce capacitive coupling, a major concern as device dimensions shrink. Purayath specifically teaches methods for forming conductive lines and adjacent air gaps.

Motivation to Combine:

The structure produced by combining Seo and Chen provides trenches with two different opening widths. A POSITA, aware of the need to reduce bit line capacitance as taught by Purayath, would have immediately recognized the utility of this alternating structure. It would have been obvious to use a deposition process (e.g., copper electroplating, as described in the '974 patent) that fills the wider "first trenches" while causing the narrower "second trenches" to pinch off at the top, trapping a void and forming an air gap. This is a well-known phenomenon in damascene processing.

Therefore, a POSITA would be motivated to:

1. Create the alternating trench structure using the methods of Seo and Chen.
2. Apply a deposition process, as suggested by the goals in Purayath, to selectively form bit lines in the wider trenches and air gaps in the narrower trenches (as claimed in Claim 6 and 7 of the '974 patent).

This combination provides a clear and direct path to the apparatus of Claim 1 with a strong motivation to achieve the predictable result of reduced bit line-to-bit line capacitance.