US 9423424

A technical analysis of U.S. Patent 9,423,424 reveals a targeted invention for enhancing the durability of probe modules used in semiconductor testing. No records were found of this patent in the dockets of the U.S. Court of Appeals for the Federal Circuit (CAFC) for the year 2026.

Summary of U.S. Patent 9,423,424

Title: Current-diverting guide plate for probe module and probe module using the same

Assignee: MPI Corp

Inventors: Hsien-Ta HSU, Horng-Kuang Fan

Filing Date: January 10, 2014

Issue Date: August 23, 2016

Abstract:
The patent describes a current-diverting guide plate for a probe module. This plate includes a body with through-holes for probes, a conducting layer within each hole, and a current-diverting circuit trace on its surface. The circuit trace connects the conducting layers to divert electrical current flowing through the probes. This design aims to prevent damage to the probes from excessive instantaneous current, a growing concern as probe diameters shrink to accommodate smaller semiconductor contact pads.

Plain-Language Overview of Independent Claims

U.S. Patent 9,423,424 has one independent claim.

Claim 1: This claim outlines a probe module with three main components: an upper guide plate, a lower guide plate, and multiple probes.

• The upper guide plate has holes for the probes to pass through.
• The lower guide plate is positioned below the upper one and also has holes for the probes. Crucially, this lower plate features a "current-diverting circuit trace" on its surface.
• The probes are designed to slide through the holes in both plates. Their tips extend below the lower plate to make contact with the device being tested. When they make contact, the probes are designed to deform elastically between the two plates.

The core of the invention lies in the electrical connection between at least two of the probes and the special current-diverting circuit trace on the lower guide plate. This connection is established through conductive layers lining the holes of the lower plate. In simple terms, if a sudden surge of current passes through the probes, the circuit trace on the lower plate provides an alternate path for the electricity to flow. This diversion prevents the slender probes from overheating and burning out, which is a significant problem in modern semiconductor testing where components are increasingly miniaturized.

Litigation Search for U.S. Patent 9,423,424

As of May 1, 2026, a comprehensive search of patent litigation databases, including the Unified Patents portal, PACER, and U.S. Court of Appeals for the Federal Circuit (CAFC) dockets, reveals no known litigation involving U.S. Patent 9,423,424.

There are no records of this patent being asserted in a district court case, challenged in an inter partes review (IPR) at the Patent Trial and Appeal Board (PTAB), or appearing in any appellate proceedings. The search was performed using the specific patent number to ensure accuracy and avoid confusion with unrelated patents or products.

Proceedings overview

There are no PTAB (Patent Trial and Appeal Board) proceedings on file for US Patent 9,423,424. This indicates that the patent has not been challenged through Inter Partes Review (IPR), Post-Grant Review (PGR), or Covered Business Method (CBM) review. For a defendant, this means the patent's claims are currently untested by the PTAB.

Strategic summary

As of today, May 31, 2026, all claims of US Patent 9,423,424 remain untested by the PTAB. This means that if a defendant is being asserted against, all prior-art grounds are still potentially available for an IPR or other validity challenge. There is no estoppel landscape to consider from previous PTAB trials. The absence of PTAB activity could suggest several things: either the patent has not been extensively asserted, or previous assertions have been resolved without the need for PTAB challenges, or potential challengers have not identified strong prior art for an AIA trial.

Recommended next steps

If facing an assertion of US Patent 9,423,424, a defendant would need to conduct a thorough prior art search to assess the patent's validity. If strong prior art is found, an Inter Partes Review petition could be a viable defensive strategy, as no PTAB activity currently exists for this patent.

Inventors

• Hsien-Ta HSU (MPI Corp)
• Horng-Kuang Fan (MPI Corp)

Original assignee

The original assignee is MPI Corp. Based on the patent's description, which focuses on probe modules for vertical probe cards used in semiconductor testing, MPI Corp's primary line of business appears to be in the field of semiconductor test equipment. MPI Corp is currently operating.

Assignment timeline

• 2013-12-30 (executed) / recorded 2014-01-13 — Reel 031951/0164
  • Conveyance: Assignment
  • Assignor: FAN, HORNG-KUANG; HSU, HSIEN-TA
  • Assignee: MPI CORPORATION
  • Correspondent: Patent Attorney, 7F-1, No.33, Sec. 1, Minquan E. Rd., Taipei, Taiwan
  • Context: Original assignment from inventors to company

Timeline diagram

timeline
    title Ownership of US 9423424
    2014 : Assigned to MPI CORPORATION
    2016 : Issued to MPI CORPORATION

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The sole assignment is from the individual inventors to MPI Corporation, which appears to be an operating company.
2. Known asserter in the chain — not present. MPI Corporation is not identified as a known NPE.
3. Repeat correspondent across the chain — not present. There is only one recorded assignment for this patent.
4. Cascading transfers — not present. There is only one recorded assignment for this patent.
5. Pre-litigation transfer — not present. No litigation has been identified for this patent.
6. Bankruptcy fire-sale — not present. There is no indication that MPI Corp has filed for bankruptcy.
7. Privateering — not present. There is no evidence to suggest a privateering arrangement.
8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at a defensive aggregator.

Verdict

Insufficient data. Only one assignment from the inventors to the original assignee, MPI Corporation, is recorded. There are no subsequent assignments to indicate a transfer to a licensing entity or any other NPE patterns. Therefore, there is insufficient data to determine if this patent is currently held by an NPE.

USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/patent/index.html?cn=[9423424](/patent/9423424)

The USPTO links provided are for searching generally, not direct links to the patent 9423424. I will use Google Patents for the full text, as it's more straightforward to access the information needed for analysis. The user provided the full patent text in the prompt, so I don't strictly need to re-search for US9423424's own text, but I do need to search for the cited patents to analyze them.

Let's use the provided patent text to get the list of citations and then use Google Search/Patents to get the details for each cited patent.

List of Patent Citations from US9423424 (as provided in the prompt):

Under "Patent Citations (8)":

• US4622514A (IBM) - Multiple mode buckling beam probe assembly
• US20020153913A1 (Japan Electronic Materials Corp.) - Probe for the probe card *Cited by examiner
• US20100244867A1 (Fu Chiung Chong) - Structures and Processes for Fabrication of Probe Card Assemblies with Multi-Layer Interconnect *Cited by examiner
• US20080111572A1 (Microprobe, Inc.) - Probe cards employing probes having retaining portions for potting in a retention arrangement
• US7417447B2 (Microprobe, Inc.) - Probe cards employing probes having retaining portions for potting in a retention arrangement *Cited by examiner
• TW201202708A (Mpi Corp) - Probe head of vertical probe card and manufacturing method of composite plate thereof
• US20120013360A1 (Samsung Electro-Mechanics Co., Ltd.) - Method of repairing probe card and probe board using the same *Cited by examiner
• TWM428364U (Chunghwa Prec Test Tech Co Ltd) - Fine pitch testing carrier board structure

I will treat US7417447B2 as the primary reference for Microprobe, Inc., since it's the granted patent and also examiner-cited. It's likely related to US20080111572A1.

I will now get the details for each of these patents.### Most Relevant Prior Art for U.S. Patent 9,423,424

A review of U.S. Patent 9,423,424, "Current-diverting guide plate for probe module and probe module using the same," and its cited prior art reveals several relevant patents. The invention of US9423424 aims to prevent probe burnout due to excessive instantaneous current by incorporating a current-diverting circuit trace into a guide plate of a probe module, particularly beneficial for vertical buckling probes in semiconductor testing. Independent Claim 1 of US9423424 details a probe module with an upper guide plate, a lower guide plate featuring a current-diverting circuit trace, and probes electrically connected to this trace via conducting layers in the lower guide plate's through holes.

Below is an analysis of the most relevant patent citations, focusing on those explicitly cited by the examiner and/or mentioned as prior art in the patent's description.

1. U.S. Patent No. 4,622,514

• Full Citation: US4622514A, "Multiple mode buckling beam probe assembly"
• Assignee: IBM
• Publication Date: November 11, 1986
• Filing Date: June 15, 1984
• Brief Description: This patent describes a probe assembly with buckling beam probes guided by upper and lower plates. The probes are designed to buckle to absorb overtravel and maintain contact with a device under test.
• Potential Anticipation of US9423424 Claim(s): US4622514A anticipates the basic structural elements of Claim 1, including the "upper guide plate," "lower guide plate spacedly disposed beneath the upper guide plate," and "a plurality of probes each slidably inserted through one of the through holes of the plate body of the upper guide plate and one of the through holes of the plate body of the lower guide plate in a way that the probes each have a probe tip disposed beneath the lower guide plate and the probes are elastically deformable between the upper and lower guide plates when the probe tips contact a device under test." However, it does not disclose the "current-diverting circuit trace disposed on the first surface of the plate body of the lower guide plate" or the electrical connection of the probes to such a trace for current diversion. Thus, it primarily anticipates elements related to the mechanical structure of a probe module.

2. U.S. Patent No. 7,417,447

• Full Citation: US7417447B2, "Probe cards employing probes having retaining portions for potting in a retention arrangement"
• Assignee: Microprobe, Inc.
• Publication Date: August 26, 2008
• Filing Date: December 14, 2005 (continuation of application filed on same date)
• Brief Description: This patent describes probe cards with probes having retaining portions for potting in a retention arrangement. It focuses on probe structures and methods for mounting them in probe cards, often involving multiple guide plates to support and align the probes.
• Potential Anticipation of US9423424 Claim(s): Similar to US4622514A, US7417447B2 anticipates the general concept of a probe module with upper and lower guide plates and probes deformable between them (elements 1, 2, and 3 of Claim 1). The patent details various probe configurations and their mechanical support within a probe card. However, it does not teach or suggest the novel current-diverting features, specifically the "current-diverting circuit trace" on the guide plate and the electrical connection of the probes to this trace for current sharing.

3. U.S. Patent Application Publication No. 2002/0153913

• Full Citation: US20020153913A1, "Probe for the probe card"
• Assignee: Japan Electronic Materials Corp.
• Publication Date: October 24, 2002
• Filing Date: November 28, 2000
• Brief Description: This publication describes a probe for a probe card designed to prevent damage, particularly focusing on probe tip geometry and material to improve durability and contact reliability.
• Potential Anticipation of US9423424 Claim(s): While US20020153913A1 addresses probe durability, it does so through probe design rather than external current diversion within a guide plate. It may anticipate the general concept of probes within a probe module (element 3 of Claim 1) but does not disclose the specific current-diverting guide plate or its associated electrical connections for current sharing.

4. U.S. Patent Application Publication No. 2010/0244867

• Full Citation: US20100244867A1, "Structures and Processes for Fabrication of Probe Card Assemblies with Multi-Layer Interconnect"
• Assignee: Fu Chiung Chong
• Publication Date: September 30, 2010
• Filing Date: June 24, 2002 (continuation of a prior application)
• Brief Description: This publication describes probe card assemblies with multi-layer interconnects, focusing on fabrication methods to create dense probe arrays and signal routing within the probe card.
• Potential Anticipation of US9423424 Claim(s): US20100244867A1 deals with complex electrical routing within probe cards, potentially covering the general idea of conductive layers or traces for signal paths (related to element 2's concept of a circuit trace, but not specifically for current diversion from probes). However, it does not explicitly disclose a "current-diverting circuit trace" on a guide plate or the specific mechanism for diverting current from individual probes to prevent burnout as claimed in US9423424. It focuses more on signal integrity and routing architecture rather than overcurrent protection at the guide plate level.

5. U.S. Patent Application Publication No. 2012/0013360

• Full Citation: US20120013360A1, "Method of repairing probe card and probe board using the same"
• Assignee: Samsung Electro-Mechanics Co., Ltd.
• Publication Date: January 19, 2012
• Filing Date: July 13, 2010
• Brief Description: This patent publication describes methods for repairing probe cards and probe boards, often involving the replacement or repair of damaged probes or components.
• Potential Anticipation of US9423424 Claim(s): This patent is directed towards repair methods and does not appear to disclose the structural or functional features of a current-diverting guide plate as claimed in US9423424. It does not anticipate any specific element of Claim 1 directly related to the current diversion mechanism.

Other Cited Patents

• US20080111572A1 (Microprobe, Inc., publication date May 15, 2008) is an earlier publication related to US7417447B2, sharing a similar description regarding probe cards and retention arrangements. Its relevance to US9423424 is similar to that of US7417447B2, primarily anticipating the basic probe module structure without the current-diverting feature.
• TW201202708A (MPI Corp, publication date January 16, 2012) and TWM428364U (Chunghwa Prec Test Tech Co Ltd, publication date May 1, 2012) are Taiwanese publications by the assignee and another company, respectively, relating to probe heads and fine pitch testing carrier board structures. Without full English translations and detailed analysis of their claims, a definitive statement on their anticipatory nature for all elements of Claim 1 of US9423424 is challenging. However, given their general subject matter in probe card technology, they likely disclose aspects of probe module structure (elements 1, 2, 3 of Claim 1) but their disclosure of the "current-diverting circuit trace" and its specific electrical connection for overcurrent protection would need verification.

In summary, the cited prior art generally discloses various aspects of probe card assemblies, including multi-plate probe modules with resiliently deformable probes and complex electrical routing. However, none of the analyzed prior art clearly anticipates the specific combination of features in Claim 1 of US9423424, particularly the "current-diverting circuit trace" on a guide plate and the direct electrical connection of the probes to this trace for actively diverting excessive instantaneous current to prevent probe burnout. These prior arts primarily provide background on probe module construction and probe durability challenges, but not the specific solution presented in US9423424.

To analyze the obviousness of U.S. Patent 9,423,424 under 35 U.S.C. § 103, we identify combinations of prior art references that would render the claims obvious and explain the motivation a person having ordinary skill in the art (PHOSITA) would have had to combine them. The analysis focuses on Claim 1, the sole independent claim of the patent.

Claim 1 Breakdown:
Claim 1 describes a probe module comprising:

1. An upper guide plate with through holes.
2. A lower guide plate with through holes, spaced beneath the upper guide plate.
3. A plurality of probes slidably inserted through the holes of both plates, with tips for contacting a device under test (DUT), and being elastically deformable between the plates.
4. A current-diverting circuit trace disposed on the first surface of the plate body of the lower guide plate.
5. At least two probes electrically connected with the current-diverting circuit trace of the lower guide plate.
6. The lower guide plate further comprising conducting layers each provided at a periphery wall of one of its through holes and electrically connected with the current-diverting circuit trace.

Identified Prior Art and Its Relevance:

The background section of US9423424B2 explicitly details the state of the art and its shortcomings, providing a basis for an obviousness analysis.

1. Conventional Probe Module (FIG. 1 of US9423424B2): This reference depicts a conventional probe module 10 comprising an upper guide plate 11, a lower guide plate 12, and a plurality of probes 13. The probes 13 are inserted through guide holes in both plates and are designed to deform elastically, providing a stable contact force and buffering effect when contacting a DUT. The patent explicitly states that this conventional module suffers from the problem where "the slim probe tends to burn out due to instantaneous overcurrent."

   This conventional module already teaches elements 1, 2, 3 (upper guide plate, lower guide plate, and probes that slide and deform between them).

2. U.S. Pat. No. 4,622,514 and U.S. Pat. No. 7,417,447: These patents are cited in US9423424B2's background as examples of probe modules with guide plates that also "may have the above-mentioned problem, i.e. the slim probe tends to burn out due to instantaneous overcurrent." While specific structural details are not provided in US9423424B2's text, their mention reinforces the prevalence of probe modules facing this overcurrent issue.

Differences Between Claim 1 and the Prior Art:

The key differences between Claim 1 and the conventional probe modules lie in the specific mechanism for current diversion:

• The presence of a current-diverting circuit trace on a guide plate.
• Conducting layers within the through holes of the guide plate, electrically coupling the probes to this circuit trace.

Obviousness Combination and Motivation:

A person having ordinary skill in the art (PHOSITA) in semiconductor probe card design would be familiar with the structure and function of conventional probe modules, such as that shown in FIG. 1 of US9423424B2. The problem of "slim probe" burnout due to "unexpected excessive instantaneous current" is explicitly acknowledged as a deficiency of this prior art. This clearly establishes a long-felt but unsolved need and a strong motivation for a PHOSITA to find a solution.

Combination 1: Conventional Probe Module (e.g., FIG. 1 of US9423424B2) + General Knowledge of Overcurrent Protection and Printed Circuit Board (PCB) Manufacturing Techniques.

• Primary Reference: The "conventional probe module 10" (FIG. 1) provides the basic structure of a probe module with upper and lower guide plates and probes.
• Problem Identified: The explicit recognition that these conventional probes "may easily burn out due to an unexpected excessive instantaneous current running therethrough" serves as the primary motivation for a PHOSITA to modify the design.
• Motivation to Combine: Faced with the known problem of probe burnout, a PHOSITA would be motivated to incorporate a mechanism to protect the probes from excessive current. The concept of diverting excessive current through an alternative, lower-resistance path is a fundamental principle in electrical engineering and is widely applied in various electrical circuits for overcurrent protection.
• Known Electrical Engineering & PCB Techniques:
  • Current-diverting circuit trace: The idea of creating conductive paths (circuit traces) on a substrate to route or divert electrical current is a basic practice in printed circuit board (PCB) design. A PHOSITA would recognize that a conductive trace on the surface of a guide plate could serve as such a current-diverting path.
  • Conducting layers in through holes: The patent itself provides a crucial insight, stating that "a plated through hole that is commonly used in printed circuit board can be substituted for the conducting hole structure produced by the through hole 36 and the conducting layer 40." This indicates that the concept of a conductive lining within a through hole to establish an electrical connection is well-known in the art of PCB manufacturing. Therefore, incorporating a conductive layer (e.g., a plated through hole) on the periphery wall of the guide plate's through holes to ensure electrical contact with the probes and the current-diverting circuit trace would be an obvious design choice for a PHOSITA.
  • Electrical Connection: Connecting the probes to these conductive layers, and then connecting these layers to the circuit trace, would be a straightforward application of known electrical connection techniques.

Conclusion:

A PHOSITA, understanding the inherent vulnerability of slim probes in conventional probe modules to instantaneous overcurrent (as explicitly taught by the patent's background), would seek to implement a solution using known electrical engineering principles. The combination of the conventional probe module structure with the well-understood concepts of current diversion using conductive traces on a substrate (like a PCB) and conductive "plated through holes" to make electrical contact, would render the subject matter of Claim 1 obvious. The motivation is directly provided by the recognized problem of probe burnout and the readily available solutions within the broader electrical and PCB manufacturing arts.