Prior art — US Patent 9093473

As a technical patent analyst, I have reviewed US patent 9093473B2, titled "Method for fabricating metal-oxide semiconductor transistor." The core innovation of this patent, particularly articulated in Claim 1, is a method that includes forming an epitaxial layer adjacent to two sides of a gate pattern, and then, after forming the epitaxial layer, performing a second photo-etching process on the gate pattern to form a slot, thereby separating the gate pattern into two gates. This sequence is presented as a solution to issues encountered in conventional approaches where the slot is formed before the epitaxial layer.

To identify the most relevant prior art and assess potential anticipation under 35 U.S.C. § 102, I have examined the patent citations listed in US9093473B2. Due to the limitations of this tool in accessing and performing detailed technical analysis of the full claims and specifications for all cited patents, the brief descriptions are primarily derived from the patent titles, and the potential anticipation assessment is based on a high-level comparison to the key distinguishing features of US9093473's Claim 1. A definitive anticipation ruling would require a full claim-by-claim comparison against the complete text of each prior art reference.

Below are selected patent citations, prioritizing those marked as "Cited by examiner" and those whose titles suggest direct relevance to MOS transistor fabrication, gate structures, or epitaxial layers:

Most Relevant Prior Art for US9093473B2

US20120012904A1
- Full Citation: US20120012904A1, "Metal-oxide semiconductor transistor and method for fabricating the same" by Ming-Te Wei et al.
- Publication Date: 2012-01-19 (Filing Date: 2010-07-15)
- Brief Description: This publication describes a metal-oxide semiconductor transistor and its fabrication method. Notably, this application shares at least one inventor with US9093473B2 and has the same priority date, indicating it is a related application, likely a parent or sibling. Such a related application, if disclosing the same invention, would be prior art under certain conditions (e.g., if it published earlier than the effective filing date of the asserted claims in US9093473B2, or if it's a parent application from which priority is claimed). The fact that this is by the same inventor(s) and has a similar title suggests a high degree of technical overlap.
- Potential Anticipation: Highly likely to potentially anticipate Claim 1 and its dependent claims of US9093473B2, as it is a related application from the same inventive entity with a similar subject matter and an earlier publication date than US9093473B2. A detailed comparison of the claims would be necessary, but given the relationship, it might disclose the specific sequence of forming the epitaxial layer before the polysilicon slot.
US20090186475A1
- Full Citation: US20090186475A1, "Method of manufacturing a MOS transistor" by Shyh-Fann Ting.
- Publication Date: 2009-07-23 (Filing Date: 2008-01-21)
- Brief Description: This patent application describes methods for manufacturing MOS transistors, a broad area directly relevant to US9093473B2. To determine specific anticipation, its disclosure regarding gate patterning, epitaxial layer formation, and any subsequent slot creation would be critical.
- Potential Anticipation: This reference could potentially anticipate aspects of Claim 1, particularly the general steps of forming a MOS transistor, gate pattern, and epitaxial layer. The key question for anticipation of Claim 1 of US9093473B2 would be whether it explicitly teaches forming the polysilicon slot after the epitaxial layer.
US20100081245A1
- Full Citation: US20100081245A1, "Methods for fabricating mos devices having highly stressed channels" by Advanced Micro Devices, Inc.
- Publication Date: 2010-04-01 (Filing Date: 2008-09-29)
- Brief Description: This patent application focuses on fabricating MOS devices with "highly stressed channels," which often involves the use of epitaxial layers (e.g., SiGe for compressive strain or SiC for tensile strain) to enhance carrier mobility. This directly relates to the context of epitaxial layer formation in US9093473B2 (e.g., lines-).
- Potential Anticipation: While it focuses on stressed channels and epitaxial layers, it would only anticipate Claim 1 of US9093473B2 if it also teaches the specific sequence of forming the gate pattern, then the epitaxial layer, and subsequently forming a slot in the gate pattern using a second photo-etching process. Without seeing its full claims and description, direct anticipation of the specific timing of the slot formation cannot be confirmed.
US7745847B2
- Full Citation: US7745847B2, "Metal oxide semiconductor transistor" by United Microelectronics Corp.
- Publication Date: 2010-06-29 (Filing Date: 2007-08-09)
- Assignee: United Microelectronics Corp., which is the original assignee of US9093473B2. This makes it a highly relevant piece of prior art from the same entity.
- Brief Description: The title indicates a focus on the MOS transistor structure itself. Being from the same assignee, it likely covers related semiconductor manufacturing techniques and could potentially disclose aspects of gate formation and epitaxial layers.
- Potential Anticipation: Given the common assignee, this patent could disclose a manufacturing method that includes elements of US9093473B2. The critical aspect for anticipation of Claim 1 would be whether it teaches the specific sequence of forming the epitaxial layer before the polysilicon slot in the gate pattern.
US7312129B2
- Full Citation: US7312129B2, "Method for producing two gates controlling the same channel" by Freescale Semiconductor, Inc.
- Publication Date: 2007-12-25 (Filing Date: 2006-01-25)
- Brief Description: This patent explicitly mentions "producing two gates controlling the same channel," which directly relates to the concept of separating a single gate pattern into two gates as described in US9093473B2 (Claim 1: "separating the gate pattern into two gates"). This makes it highly relevant for potentially anticipating the outcome of the second photo-etching process.
- Potential Anticipation: This patent is highly relevant to the "forming a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates" step of Claim 1. Detailed examination of its claims and description is needed to see if it also teaches the step of forming an epitaxial layer before this gate separation, which is the distinguishing feature of US9093473B2.
US6143606A
- Full Citation: US6143606A, "Method for manufacturing split-gate flash memory cell" by Worldwide Semiconductor Manufacturing Corp.
- Publication Date: 2000-11-07 (Filing Date: 1997-12-26)
- Brief Description: The title specifically mentions "split-gate" and "manufacturing," making it relevant to the gate separation aspect of US9093473B2. Split-gate structures inherently involve a separation of a gate element.
- Potential Anticipation: This patent could potentially anticipate the "forming a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates" element of Claim 1. The key for anticipation of Claim 1 of US9093473B2 would be whether this patent teaches the formation of an epitaxial layer before the split-gate formation.

General Statement Regarding Anticipation:

For each of the cited patents, and particularly for Claim 1 of US9093473B2, a thorough anticipation analysis under 35 U.S.C. § 102 would require a detailed, side-by-side comparison of every element of Claim 1 (and its dependent claims) against the complete disclosure (including all claims, specification, and drawings) of each prior art reference. The critical differentiating element in US9093473B2's Claim 1 is the sequence where the second photo-etching process for forming the gate slot occurs after the epitaxial layer is formed. Any prior art that explicitly teaches all the elements of Claim 1 in this specific order would anticipate it. Without full access to the detailed text and figures of each cited patent, it is not possible to provide a definitive claim-by-claim anticipation statement for all 49 references.