Obviousness

To analyze the obviousness of US patent 9093473 under 35 U.S.C. § 103, we will examine the independent claims and consider combinations of prior art references along with the motivation for a person having ordinary skill in the art (PHOSITA) to combine them. The key distinguishing feature of US9093473, as highlighted in its abstract and detailed description, is the sequence of steps, specifically forming the epitaxial layer before performing the second photo-etching process to create a slot in the gate pattern.

Independent Claim 1 of US9093473B2

Independent Claim 1 describes a method for fabricating a metal-oxide semiconductor (MOS) transistor, comprising:

1. Providing a semiconductor substrate.
2. Forming a silicon layer on the semiconductor substrate.
3. Performing a first photo-etching process on the silicon layer for forming a gate pattern.
4. Forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern.
5. After forming the epitaxial layer, performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.

Prior Art Combination and Obviousness Analysis

The core of the obviousness argument rests on whether a PHOSITA, at the time of the invention (priority date 2010-07-15), would have been motivated to combine existing prior art elements in the claimed sequence, particularly regarding the timing of epitaxial layer formation and gate slot creation. The patent itself provides significant insight into the "conventional approach" and the problems it seeks to solve.

Primary Reference 1: US20050112817A1 (Taiwan Semiconductor Manufacturing Company, Ltd.)

• Disclosure: This patent describes a "Semiconductor device having high drive current and method of manufacture thereof," which involves forming strained source/drain regions using epitaxial layers.
• Specifically, it teaches:
  • Providing a semiconductor substrate.
  • Forming a gate structure on the semiconductor substrate (which typically includes a silicon layer, e.g., polysilicon). (See paragraph discussing "a gate structure 104 is formed on the semiconductor substrate 100").
  • Forming an epitaxial layer (e.g., SiGe or SiC) in the semiconductor substrate adjacent to two sides of the gate structure to function as source/drain regions. (See paragraph "Source/drain regions are then formed next to the gate structure 104. In this embodiment, the source/drain regions are formed by an epitaxial process... For example, the epitaxial layers may be SiGe layers or SiC layers.")
• Contribution to Claim 1: US20050112817A1 discloses steps (1), (2), (3) (forming the gate pattern), and (4) (forming the epitaxial layer adjacent to the gate pattern) of Claim 1. It does not, however, disclose the step of forming a slot in the gate pattern to separate it into two gates.

Secondary Reference 2: US20080090360A1 (Krivokapic)

• Disclosure: This patent, titled "Methods for fabricating multiple finger transistors," teaches how to split a single gate electrode into multiple gate electrodes (fingers) by forming a slot.
• Specifically, it teaches:
  • Forming a gate stack (e.g., a polysilicon gate stack) on a semiconductor substrate and defining a first gate electrode within it. (See paragraph).
  • Forming source/drain regions in the semiconductor substrate. (See paragraph).
  • Subsequently, a "second gate electrode" is formed in the gate stack, which involves splitting the initial gate electrode by creating a slot (as illustrated in Figure 4, showing slot 110 splitting gate electrode 104 into 104a and 104b).
• Key Timing: Krivokapic explicitly describes forming the source/drain regions before forming the second gate electrode (i.e., splitting the gate via a slot). (See paragraph "Thereafter, source/drain regions are formed in the semiconductor substrate and a second gate electrode is formed in the gate stack.").
• Contribution to Claim 1: US20080090360A1 discloses steps (1), (2), (3) (forming the gate pattern), and (5) (performing a second photo-etching process on the gate pattern to form a slot and separate it into two gates). Crucially, its sequence of performing the gate splitting after source/drain formation aligns with the "after forming the epitaxial layer" aspect of Claim 1, assuming the source/drain regions are epitaxial.

Motivation to Combine US20050112817A1 and US20080090360A1, driven by US9093473's own Background:

A PHOSITA would be motivated to combine the teachings of US20050112817A1 and US20080090360A1 for the following reasons:

1. Synergistic Performance Enhancement: Both references address transistor performance. US20050112817A1 aims to increase drive current through strained epitaxial source/drain regions, a known technique for high-performance MOS devices. US20080090360A1 teaches fabricating multiple-finger transistors, a common approach to further enhance current drive, reduce resistance, or improve device matching. A PHOSITA seeking to maximize MOS transistor performance would naturally combine these complementary techniques.
2. Addressing Known Problems in the Prior Art (as disclosed in US9093473 itself): The "Description of the Prior Art" section of US9093473 explicitly details the problems associated with the "conventional approach" of forming the polysilicon slot before the epitaxial layer. These problems include:
   • "Polysilicon residue and line end bridge" if the etching ratio for the slot formation is too low.
   • "Consumption of the hard mask" and "consumption of the spacer" if the etching ratio is too high, leading to "a portion of the gate is exposed and un-wanted epitaxial layer would be formed on the exposed portion of the gate."
     A PHOSITA, confronted with these well-articulated problems arising from the conventional sequence, would be strongly motivated to find a solution. The sequencing taught by Krivokapic (forming source/drain regions before splitting the gate), when applied to epitaxial source/drain regions (as taught by US20050112817A1), directly addresses the identified issues. By ensuring the epitaxial layer is formed before the potentially damaging slot-etching step, the gate structure is protected, preventing unwanted epitaxial growth on exposed gate portions. This represents a clear problem-solution motivation for adopting the sequence claimed in US9093473.

Therefore, a PHOSITA, having reviewed these prior art documents and being aware of the explicit problems associated with the "conventional approach" of slot formation before epitaxial layer growth (as detailed in the background of US9093473), would have been motivated to combine the features of US20050112817A1 and US20080090360A1 to arrive at the method claimed in US9093473, particularly the critical step of forming the epitaxial layer before the second photo-etching process that forms the slot. This combination, driven by clear motivations, renders Independent Claim 1 obvious under 35 U.S.C. § 103.

Dependent Claims

Dependent claims 2-10 elaborate on the process with additional steps such as forming hard masks, first and second spacers, lightly doped drains, and specific dielectric layers. Many of these steps are standard techniques in MOS transistor fabrication and are disclosed in various general semiconductor manufacturing patents (e.g., US6593197B2 for spacers, US7812399B2 for multi-layer gate structures and spacers). If the independent claim is found obvious, adding these conventional and well-known fabrication steps, especially when motivated by common design choices or known process improvements (like using protective dielectric layers to avoid rework issues as discussed in US9093473 itself), would also be considered obvious to a PHOSITA.