US 9092352

US Patent 9092352 Summary

Title: Memory controller with write data error detection and remediation
Current Assignee: Signal LLP
Inventors: Yuanlong Wang, Frederick A. Ware
Filing Date: February 7, 2014
Issue Date: July 28, 2015

Abstract:
A controller includes a link interface configured to connect to a first link for bi-directional data communication and a second link for transmitting unidirectional error-detection information. An encoder dynamically adds first error-detection information to a portion of write data. A transmitter sends this write data via the link interface. A delay element is connected to the encoder's output. A receiver, also coupled to the link interface, receives second error-detection information corresponding to the write data portion. Error-detection logic, connected to both the delay element and the receiver, compares the first and second error-detection information to identify errors in the write data. If an error is found, an error condition is asserted.

Plain-Language Overview of Independent Claims:

• Independent Claim 1 (Controller for Write and Read Data Error Detection - Sideband): This claim describes a memory controller designed to detect errors in both write and read data using a separate "sideband" link for error-detection information.

  • The controller has a link interface that connects to two links: a first link for sending and receiving data (bi-directional) and a second link for only transmitting error-detection information (unidirectional).
  • When the controller prepares to write data, a first encoder creates initial error-detection information for that write data.
  • This write data is transmitted.
  • The initial error-detection information is delayed within the controller.
  • When the device (e.g., memory) sends back its own error-detection information for the write data it received, and also sends read data along with its error-detection information for that read data, the controller's error-detection logic compares these different sets of error-detection information.
  • Specifically, it compares the controller's initial (delayed) write data error-detection information with the device's received write data error-detection information to check for errors in the write path.
  • It also compares the controller's locally generated error-detection information for received read data with the device's transmitted read data error-detection information to check for errors in the read path.
  • If any errors are detected, the controller signals an error condition.

• Independent Claim 21 (Device for Write and Read Data Error Detection - Sideband): This claim describes a memory device (e.g., a DRAM chip) that works in conjunction with a controller like the one in Claim 1.

  • The device has a link interface that connects to a first link for bi-directional data and a second link for receiving unidirectional error-detection information (from the controller).
  • It has encoders to dynamically add error-detection information to both the read data it prepares to send and the write data it receives.
  • A transmitter is configured to send the read data and either its own generated error-detection information for read data or for the received write data, back to the controller (presumably via the second link mentioned in Claim 1, which transmits unidirectional error-detection information from the controller's perspective, but receives it from the device's perspective in this context).

• Independent Claim 28 (System for Write and Read Data Error Detection - Sideband): This claim describes a complete memory system incorporating both the controller and device elements described in Claims 1 and 21, specifying their interaction.

  • It includes a first link for bi-directional data and a second link for unidirectional error-detection information.
  • The controller component matches the description in Claim 1, performing its local encoding, transmitting write data, receiving read data and both types of error-detection information, and comparing them to assert an error condition.
  • The device component matches the description in Claim 21, performing its local encoding of read and received write data, and transmitting its respective error-detection information.

• Independent Claim 36 (Controller for Write Data Error Detection - Sideband): This claim is a more focused version of Claim 1, specifically addressing error detection for write data only.

  • It has a link interface for bi-directional data and unidirectional error-detection information transmission.
  • An encoder adds error-detection information to write data.
  • A transmitter sends the write data.
  • A delay element holds the locally generated error-detection information.
  • A receiver gets error-detection information related to the sent write data (from the device).
  • Error-detection logic compares the delayed local error-detection information with the received error-detection information to find errors in the write data and asserts an error condition if detected.

• Independent Claim 41 (Controller for Read Data Error Detection - Sideband): This claim focuses specifically on error detection for read data only.

  • It has a link interface for bi-directional data and unidirectional error-detection information transmission.
  • A first receiver gets read data.
  • An encoder dynamically adds error-detection information to this received read data.
  • A second receiver gets error-detection information corresponding to the read data (from the device).
  • Error-detection logic compares the locally generated read data error-detection information with the received read data error-detection information to find errors in the read data and asserts an error condition if detected.

• Independent Claim 46 (System for Write and Read Data Error Detection - In-Band): This claim describes a system where both bi-directional data and unidirectional error-detection information are communicated using a single common link (in-band signaling), unlike the separate links in previous claims.

  • The controller dynamically adds error-detection information to write data and transmits it.
  • It receives read data and the device's error-detection information (which covers both write and read data) over the same link.
  • The controller also generates its own error-detection information for the received read data and compares it with the received device-generated error-detection information.
  • The device receives write data, dynamically adds error-detection information to it, and also adds error-detection information to its read data.
  • The device then transmits both the read data and its combined error-detection information back over the same link.
  • Error-detection logic in the controller compares the relevant error-detection information to determine errors in both write and read operations.

• Independent Claim 53 (Device for Write and Read Data Error Detection - In-Band): This claim describes a device component for the in-band signaling system of Claim 46.

  • It has a link interface connected to a single link for both bi-directional data and unidirectional error-detection information.
  • A receiver gets write data.
  • An encoder dynamically adds error-detection information to the received write data.
  • Another encoder dynamically adds error-detection information to its read data, combining it with the write data error-detection information.
  • A transmitter sends this combined read data and error-detection information back on the single link.

• Independent Claim 57 (Controller for Write and Read Data Error Detection - In-Band): This claim describes a controller component for the in-band signaling system of Claim 46.

  • It has a link interface connected to a single link for both bi-directional data and unidirectional error-detection information.
  • An encoder dynamically adds error-detection information to write data.
  • A transmitter sends this write data.
  • A delay element holds the locally generated write data error-detection information.
  • A receiver gets read data and the device's combined error-detection information for both write and read data.
  • Another encoder dynamically adds its own error-detection information to the received read data, potentially combined with the delayed local write data error-detection.
  • Error-detection logic compares the received device-generated error-detection information with the controller's internally generated and delayed error-detection information for both write and read data to detect errors.

• Independent Claim 62 (Device for Write Mask Error Detection): This claim describes a device specifically for detecting errors in write mask information.

  • It has a link interface connected to a first link for receiving write mask information and a second link for receiving unidirectional error-detection information.
  • A first receiver gets the write mask information.
  • An encoder dynamically adds its own error-detection information to the received write mask information.
  • A second receiver gets error-detection information for the write mask (from the controller).
  • Error-detection logic compares the device's locally generated write mask error-detection information with the received controller-generated write mask error-detection information.
  • If an error is detected, a write operation to the memory core is disabled to prevent erroneous data overwrites.

Litigation Information:
The patent 9092352 has known litigation. A case was filed in the Texas Eastern District Court, identified as 2:26-cv-00093. This case was filed in 2026.