Patent 8993384

Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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To identify the most relevant prior art for US Patent 8993384, I will examine the "Cited By" and "Citations" sections of the patent, focusing on the patents listed as prior art. "Prior art" refers to information publicly available before the effective filing date of a patent application, which for US8993384 is June 9, 2013 [cite: Original Patent Text, 3].

I will now list the patent citations for US8993384, providing the full citation, publication/filing date, a brief description, and which claims it potentially anticipates under 35 U.S.C. § 102.

Cited Prior Art for US Patent 8993384:

  1. US6043138A

    • Full Citation: US6043138A - Multi-step polysilicon deposition process for boron penetration inhibition [cite: Original Patent Text]
    • Priority Date: September 16, 1996 [cite: Original Patent Text]
    • Publication Date: March 28, 2000 [cite: Original Patent Text]
    • Brief Description: This patent describes a multi-step polysilicon deposition process aimed at inhibiting boron penetration in semiconductor devices. This is relevant to the general field of semiconductor fabrication and gate structures. [cite: Original Patent Text]
    • Potentially Anticipates: This patent broadly relates to gate formation and semiconductor processing. Given its early filing date and general nature, it could potentially anticipate aspects of Claim 1, particularly steps involving "forming a gate structure" and general semiconductor device fabrication, though it does not describe FinFETs or epitaxial recess structures.

  2. US6492216B1

    • Full Citation: US6492216B1 - Method of forming a transistor with a strained channel [cite: Original Patent Text]
    • Priority Date: February 7, 2002 [cite: Original Patent Text]
    • Publication Date: December 10, 2002 [cite: Original Patent Text]
    • Brief Description: This patent focuses on methods for forming transistors with strained channels to improve performance, which is a key objective of US8993384. It describes inducing biaxial tensile strain in an epitaxial silicon layer due to lattice constant differences. [cite: Original Patent Text]
    • Potentially Anticipates: This patent is highly relevant to US8993384, specifically regarding the use of strained channels and epitaxial layers. It directly relates to the concept of forming an epitaxial layer to impose stress on channel regions (as mentioned in the background of US8993384). It could potentially anticipate the "forming an epitaxial layer to fill up the recess" step of Claim 1, especially the underlying purpose of applying stress.

  3. US20040195624A1

    • Full Citation: US20040195624A1 - Strained silicon fin field effect transistor [cite: Original Patent Text]
    • Priority Date: April 4, 2003 [cite: Original Patent Text]
    • Publication Date: October 7, 2004 [cite: Original Patent Text]
    • Brief Description: This publication describes a strained silicon fin field effect transistor (FinFET). This is highly pertinent as US8993384 specifically addresses FinFETs and strained epitaxial structures. [cite: Original Patent Text]
    • Potentially Anticipates: This patent directly relates to "fin structures" and "strained silicon," central elements of US8993384. It could potentially anticipate the "forming a fin structure" step and the general concept of a FinFET with a strained region, as outlined in Claim 1.

  4. US20050051825A1

    • Full Citation: US20050051825A1 - Semiconductor device and manufacturing method thereof [cite: Original Patent Text]
    • Priority Date: September 9, 2003 [cite: Original Patent Text]
    • Publication Date: March 10, 2005 [cite: Original Patent Text]
    • Brief Description: This patent discusses a semiconductor device and its manufacturing method, broadly covering the field. [cite: Original Patent Text]
    • Potentially Anticipates: Without a more specific description from the patent text, it's difficult to pinpoint exact claims. However, it generally relates to the fabrication method (Claim 1) and the semiconductor device itself.

  5. US6921963B2

    • Full Citation: US6921963B2 - Narrow fin FinFET [cite: Original Patent Text]
    • Priority Date: January 23, 2003 [cite: Original Patent Text]
    • Publication Date: July 26, 2005 [cite: Original Patent Text]
    • Brief Description: This patent describes a FinFET with narrow fins, addressing a specific architectural detail of FinFETs. [cite: Original Patent Text]
    • Potentially Anticipates: This patent could potentially anticipate the "forming a fin structure" step of Claim 1, specifically regarding the geometry of the fin.

  6. US20060099830A1

    • Full Citation: US20060099830A1 - Plasma implantation using halogenated dopant species to limit deposition of surface layers [cite: Original Patent Text]
    • Priority Date: November 5, 2004 [cite: Original Patent Text]
    • Publication Date: May 11, 2006 [cite: Original Patent Text]
    • Brief Description: This publication relates to plasma implantation techniques for doping, specifically using halogenated dopant species to limit surface layer deposition. [cite: Original Patent Text]
    • Potentially Anticipates: This patent is less directly related to the core innovation of US8993384 (epitaxial layer with recessed isolation) but broadly falls under semiconductor fabrication methods. It might be relevant to doping processes that could occur during or after the formation of fin structures or epitaxial layers, potentially anticipating some implied or optional steps in Claim 1.

  7. US7087477B2

    • Full Citation: US7087477B2 - FinFET SRAM cell using low mobility plane for cell stability and method for forming [cite: Original Patent Text]
    • Priority Date: December 4, 2001 [cite: Original Patent Text]
    • Publication Date: August 8, 2006 [cite: Original Patent Text]
    • Brief Description: This patent describes a FinFET SRAM cell design and its fabrication method, focusing on cell stability. [cite: Original Patent Text]
    • Potentially Anticipates: This patent is relevant to FinFET structures and their fabrication (Claim 1), particularly the "forming a fin structure" step and the overall integration of FinFETs into circuits.

  8. US7091551B1

    • Full Citation: US7091551B1 - Four-bit FinFET NVRAM memory device [cite: Original Patent Text]
    • Priority Date: April 13, 2005 [cite: Original Patent Text]
    • Publication Date: August 15, 2006 [cite: Original Patent Text]
    • Brief Description: This patent describes a four-bit FinFET NVRAM memory device, again focusing on FinFET applications. [cite: Original Patent Text]
    • Potentially Anticipates: Similar to US7087477B2, this patent broadly anticipates the "forming a fin structure" step and the general concept of FinFET devices in Claim 1.

  9. US20060286729A1

    • Full Citation: US20060286729A1 - Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate [cite: Original Patent Text]
    • Priority Date: June 21, 2005 [cite: Original Patent Text]
    • Publication Date: December 21, 2006 [cite: Original Patent Text]
    • Brief Description: This publication describes CMOS integrated circuits utilizing raised source/drain regions and replacement metal gates. US8993384 also mentions a "high-k last replacement metal gate (RMG) process." [cite: Original Patent Text]
    • Potentially Anticipates: This patent is relevant to the "forming a gate structure" step (Claim 1) and the subsequent "removing the gate structure to leave a trench" and "forming a conductive layer to fill up the trench" steps (Claim 9), particularly concerning the use of replacement metal gates and raised source/drain areas.

  10. US20070108528A1

    • Full Citation: US20070108528A1 - Sram cell [cite: Original Patent Text]
    • Priority Date: November 15, 2005 [cite: Original Patent Text]
    • Publication Date: May 17, 2007 [cite: Original Patent Text]
    • Brief Description: This publication describes an SRAM cell. [cite: Original Patent Text]
    • Potentially Anticipates: Broadly relevant to semiconductor devices, potentially to the context in which FinFETs (as in Claim 1) might be used.

  11. US20070158756A1

    • Full Citation: US20070158756A1 - Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement [cite: Original Patent Text]
    • Priority Date: January 12, 2006 [cite: Original Patent Text]
    • Publication Date: July 12, 2007 [cite: Original Patent Text]
    • Brief Description: This publication describes a production method for a FinFET transistor arrangement. [cite: Original Patent Text]
    • Potentially Anticipates: Highly relevant to the "forming a fin structure" and "forming a gate structure" steps of Claim 1, as it directly concerns FinFET fabrication methods.

  12. US7247887B2

    • Full Citation: US7247887B2 - Segmented channel MOS transistor [cite: Original Patent Text]
    • Priority Date: July 1, 2005 [cite: Original Patent Text]
    • Publication Date: July 24, 2007 [cite: Original Patent Text]
    • Brief Description: This patent describes a segmented channel MOS transistor. [cite: Original Patent Text]
    • Potentially Anticipates: While not explicitly a FinFET, it pertains to MOS transistor channel design, which is a fundamental aspect of the fin structure and gate structure of Claim 1.

  13. US7250658B2

    • Full Citation: US7250658B2 - Hybrid planar and FinFET CMOS devices [cite: Original Patent Text]
    • Priority Date: June 26, 2003 [cite: Original Patent Text]
    • Publication Date: July 31, 2007 [cite: Original Patent Text]
    • Brief Description: This patent describes hybrid planar and FinFET CMOS devices, showing the co-existence and fabrication of both types of transistors. [cite: Original Patent Text]
    • Potentially Anticipates: This is highly relevant to the context of US8993384, which also discusses FinFETs and even mentions that planar FETs could be formed. It could anticipate the "forming a fin structure" and "forming a gate structure" steps of Claim 1, as well as the overall semiconductor device.

  14. US7309626B2

    • Full Citation: US7309626B2 - Quasi self-aligned source/drain FinFET process [cite: Original Patent Text]
    • Priority Date: November 15, 2005 [cite: Original Patent Text]
    • Publication Date: December 18, 2007 [cite: Original Patent Text]
    • Brief Description: This patent describes a quasi self-aligned source/drain FinFET process. [cite: Original Patent Text]
    • Potentially Anticipates: This is relevant to the overall FinFET fabrication method (Claim 1), particularly the formation of source/drain regions which would be adjacent to the gate and where epitaxial structures are formed.

  15. US7352034B2

    • Full Citation: US7352034B2 - Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures [cite: Original Patent Text]
    • Priority Date: August 25, 2005 [cite: Original Patent Text]
    • Publication Date: April 1, 2008 [cite: Original Patent Text]
    • Brief Description: This patent details semiconductor structures integrating damascene-body FinFETs and planar devices on a common substrate, along with their formation methods. [cite: Original Patent Text]
    • Potentially Anticipates: Similar to US7250658B2, this patent is relevant to the overall fabrication method (Claim 1) and the integration of FinFETs on a substrate.

  16. US20080157208A1

    • Full Citation: US20080157208A1 - Stressed barrier plug slot contact structure for transistor performance enhancement [cite: Original Patent Text]
    • Priority Date: December 29, 2006 [cite: Original Patent Text]
    • Publication Date: July 3, 2008 [cite: Original Patent Text]
    • Brief Description: This publication describes a stressed barrier plug slot contact structure for enhancing transistor performance. [cite: Original Patent Text]
    • Potentially Anticipates: This patent relates to performance enhancement through stress, similar to the goal of US8993384. It could potentially anticipate the use of stressed materials around the transistor, although the specific structure (barrier plug slot contact) differs from the epitaxial recess of US8993384.

  17. US7470570B2

    • Full Citation: US7470570B2 - Process for fabrication of FinFETs [cite: Original Patent Text]
    • Priority Date: November 14, 2006 [cite: Original Patent Text]
    • Publication Date: December 30, 2008 [cite: Original Patent Text]
    • Brief Description: This patent describes a process for the fabrication of FinFETs. [cite: Original Patent Text]
    • Potentially Anticipates: This is broadly anticipatory of the fabrication method of Claim 1, specifically the initial steps of "forming a fin structure" and "forming a gate structure" in a FinFET context.

  18. US7525160B2

    • Full Citation: US7525160B2 - Multigate device with recessed strain regions [cite: Original Patent Text]
    • Priority Date: December 27, 2005 [cite: Original Patent Text]
    • Publication Date: April 28, 2009 [cite: Original Patent Text]
    • Brief Description: This patent describes a multigate device with recessed strain regions. This is directly relevant to the concept of forming a recess for a strained epitaxial layer in US8993384. [cite: Original Patent Text]
    • Potentially Anticipates: This patent is highly relevant to Claim 1, particularly the "forming a recess in the fin structure at a side of the gate structure" and "forming an epitaxial layer to fill up the recess" steps, as it describes similar features for strain enhancement in multigate devices.

  19. US7531437B2

    • Full Citation: US7531437B2 - Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material [cite: Original Patent Text]
    • Priority Date: September 30, 2004 [cite: Original Patent Text]
    • Publication Date: May 12, 2009 [cite: Original Patent Text]
    • Brief Description: This patent details a method for forming metal gate electrodes using sacrificial materials. This is similar to the "gate-last for high-k last process" described in US8993384. [cite: Original Patent Text]
    • Potentially Anticipates: This patent could anticipate the "forming a gate structure" step of Claim 1, and more specifically the process of replacing a dummy gate with a metal gate as described in Claim 9.

  20. US20090124097A1

    • Full Citation: US20090124097A1 - Method of forming narrow fins in FinFET devices with reduced spacing therebetween [cite: Original Patent Text]
    • Priority Date: November 9, 2007 [cite: Original Patent Text]
    • Publication Date: May 14, 2009 [cite: Original Patent Text]
    • Brief Description: This publication describes methods for forming narrow fins in FinFET devices with reduced spacing. [cite: Original Patent Text]
    • Potentially Anticipates: This is relevant to the "forming a fin structure" step of Claim 1, specifically regarding the dimensions and density of the fins.

  21. US7569857B2

    • Full Citation: US7569857B2 - Dual crystal orientation circuit devices on the same substrate [cite: Original Patent Text]
    • Priority Date: September 29, 2006 [cite: Original Patent Text]
    • Publication Date: August 4, 2009 [cite: Original Patent Text]
    • Brief Description: This patent discusses dual crystal orientation circuit devices on the same substrate. [cite: Original Patent Text]
    • Potentially Anticipates: Broadly relevant to semiconductor devices and substrates, potentially influencing the material choices for the fin structure in Claim 1.

  22. US20090242964A1

    • Full Citation: US20090242964A1 - Non-volatile memory device [cite: Original Patent Text]
    • Priority Date: April 26, 2006 [cite: Original Patent Text]
    • Publication Date: October 1, 2009 [cite: Original Patent Text]
    • Brief Description: This publication describes a non-volatile memory device. [cite: Original Patent Text]
    • Potentially Anticipates: Broadly relevant to semiconductor devices, potentially to the context in which FinFETs (as in Claim 1) might be used.

  23. US20090269916A1

    • Full Citation: US20090269916A1 - Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges [cite: Original Patent Text]
    • Priority Date: April 28, 2008 [cite: Original Patent Text]
    • Publication Date: October 29, 2009 [cite: Original Patent Text]
    • Brief Description: This publication describes methods for fabricating memory cells with fin structures having specific top surface and corner profiles. [cite: Original Patent Text]
    • Potentially Anticipates: This is relevant to the "forming a fin structure" step of Claim 1, specifically regarding the shape and profile of the fin.

  24. US20100048027A1

    • Full Citation: US20100048027A1 - Smooth and vertical semiconductor fin structure [cite: Original Patent Text]
    • Priority Date: August 21, 2008 [cite: Original Patent Text]
    • Publication Date: February 25, 2010 [cite: Original Patent Text]
    • Brief Description: This publication describes a smooth and vertical semiconductor fin structure. [cite: Original Patent Text]
    • Potentially Anticipates: This is relevant to the "forming a fin structure" step of Claim 1, specifically concerning the quality and orientation of the fin.

  25. US20100072553A1

    • Full Citation: US20100072553A1 - METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE [cite: Original Patent Text]
    • Priority Date: September 23, 2008 [cite: Original Patent Text]
    • Publication Date: March 25, 2010 [cite: Original Patent Text]
    • Brief Description: This publication describes a metal gate stress film for mobility enhancement in FinFET devices. This relates to using stress to improve FinFET performance. [cite: Original Patent Text]
    • Potentially Anticipates: This is highly relevant to the objective of US8993384 to increase carrier mobility through stress. It could potentially anticipate the functional aspect of "stress imposed on the channel region" (Claim 1) and the use of materials to achieve this.

  26. US20100144121A1

    • Full Citation: US20100144121A1 - Germanium FinFETs Having Dielectric Punch-Through Stoppers [cite: Original Patent Text]
    • Priority Date: December 5, 2008 [cite: Original Patent Text]
    • Publication Date: June 10, 2010 [cite: Original Patent Text]
    • Brief Description: This publication describes Germanium FinFETs with dielectric punch-through stoppers. [cite: Original Patent Text]
    • Potentially Anticipates: This is relevant to the "forming a fin structure" step of Claim 1 (specifically if the fin material is Germanium or includes it), and the overall FinFET architecture.

  27. US20100167506A1

    • Full Citation: US20100167506A1 - Inductive plasma doping [cite: Original Patent Text]
    • Priority Date: December 31, 2008 [cite: Original Patent Text]
    • Publication Date: July 1, 2010 [cite: Original Patent Text]
    • Brief Description: This publication describes inductive plasma doping. [cite: Original Patent Text]
    • Potentially Anticipates: Similar to US20060099830A1, this broadly relates to doping processes that might be part of the fabrication method in Claim 1.

  28. US20120193713A1

    • Full Citation: US20120193713A1 - FinFET device having reduce capacitance, access resistance, and contact resistance [cite: Original Patent Text]
    • Priority Date: January 31, 2011 [cite: Original Patent Text]
    • Publication Date: August 2, 2012 [cite: Original Patent Text]
    • Brief Description: This publication describes a FinFET device designed to reduce capacitance, access resistance, and contact resistance. [cite: Original Patent Text]
    • Potentially Anticipates: This patent is relevant to the overall FinFET device structure and performance optimization, which would include elements of Claim 1, particularly concerning the fin and gate structures.

  29. US8765533B2

    • Full Citation: US8765533B2 - Fin-like field effect transistor (FinFET) channel profile engineering method and associated device [cite: Original Patent Text]
    • Priority Date: December 4, 2012 [cite: Original Patent Text]
    • Publication Date: July 1, 2014 [cite: Original Patent Text]
    • Brief Description: This patent describes a FinFET channel profile engineering method and associated device. [cite: Original Patent Text]
    • Potentially Anticipates: This patent's filing date (December 4, 2012) is prior to US8993384's filing date (June 9, 2013). It directly addresses FinFET channel profiles, making it highly relevant to the "fin structure" and potentially the "recess" formation in Claim 1, as the profile of the channel would be influenced by these steps.

Most Relevant Prior Art:

Based on the descriptions, the following prior art references appear most relevant to the distinct features of US8993384, particularly the combination of FinFET structures with strained epitaxial layers and recessed isolation:

  • US6492216B1 (Method of forming a transistor with a strained channel): Directly addresses forming strained channels using epitaxial layers for performance improvement, a core concept of US8993384. [cite: Original Patent Text]
  • US20040195624A1 (Strained silicon fin field effect transistor): Combines the concepts of FinFETs and strained silicon, both central to US8993384. [cite: Original Patent Text]
  • US7525160B2 (Multigate device with recessed strain regions): Explicitly mentions "recessed strain regions" in a multigate device context, which directly parallels the "recess in the fin structure" filled with an epitaxial layer in Claim 1 of US8993384. [cite: Original Patent Text]
  • US20100072553A1 (METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE): Directly addresses mobility enhancement in FinFETs through stress, aligning with the objective of US8993384. [cite: Original Patent Text]
  • US8765533B2 (Fin-like field effect transistor (FinFET) channel profile engineering method and associated device): Its priority date is before US8993384, and it addresses FinFET channel profile engineering, which would impact the fin and recess structures of Claim 1. [cite: Original Patent Text]

These patents collectively show that the individual components of FinFETs, strained channels, and even recessed regions for strain were known in the prior art. The novelty of US8993384 likely lies in the specific combination of these elements and the detailed method for forming the epitaxial layer in the recess while addressing void defects, particularly the relationship between the depth of the isolation structure etch and the depth of the fin recess.

Generated 5/19/2026, 12:47:09 PM