Derivative works — US Patent 8993384

Defensive Disclosure for US Patent 8993384

Current Date: April 26, 2026

Role: Senior Patent Strategist and Research Engineer specializing in Defensive Publishing.

This document details derivative variations of the core claims of US Patent 8993384, aimed at preemptively disclosing potential incremental improvements by competitors. The focus is on Claim 1, the independent method claim, as it defines the foundational fabrication process.

Derivations based on Claim 1: A fabrication method for a semiconductor device, comprising:

forming a fin structure, protruding from a surface of a substrate, wherein the fin structure comprises a top surface and two side surfaces;
forming an isolation structure to surround the fin structure;
forming a gate structure, overlaying the top surface and the two side surfaces of a portion of the fin structure, and covering a portion of the isolation structure;
after the step of forming the gate structure, etching the isolation structure exposed from the gate structure until a top surface of the isolation structure is etched down to a first depth;
forming a recess in the fin structure at a side of the gate structure; and
forming an epitaxial layer to fill up the recess, wherein a bottom surface of the recess has a second depth, and the second depth is deeper than the first depth. [cite: Original Patent Text]

Derivative 1.1: Material & Component Substitution - III-V FinFET with High-k/Metal Gate

Enabling Description:
A fabrication method for a semiconductor device comprising: forming a fin structure from a III-V semiconductor material, such as InGaAs, epitaxially grown on a GaAs-on-silicon substrate, wherein the fin structure comprises a (100) top surface and two (110) side surfaces. An isolation structure, specifically a deep trench isolation (DTI) using a spin-on dielectric (SOD) such as polysilazane, is formed to surround the InGaAs fin structure. A replacement high-k/metal gate (RMG) structure is then formed. Initially, a dummy polysilicon gate is fabricated, overlaying the top surface and two side surfaces of a portion of the InGaAs fin structure, and covering a portion of the DTI structure. After the dummy gate formation and spacer definition (e.g., using SiN), the SOD isolation structure exposed from the dummy gate and spacers is etched down to a first depth (e.g., 50 Å) using a CHF3/CF4 plasma etch. Subsequently, a recess is formed in the InGaAs fin structure at a side of the gate structure by selective wet etching using a citric acid/H2O2 solution at 50°C. Finally, a strained epitaxial layer of InAs is grown selectively within the recess via metal-organic chemical vapor deposition (MOCVD) using trimethylindium and arsine precursors, achieving a second depth (e.g., 150 Å) deeper than the first depth, thereby providing tensile strain to the InGaAs channel. The dummy gate is later removed and replaced with a high-k dielectric (e.g., HfO2 deposited by atomic layer deposition) and a metal gate electrode (e.g., TaN/TiN/W stack).

flowchart TD
    A[Form Fin Structure (InGaAs on GaAs/Si)] --> B{Form DTI Isolation (Polysilazane)};
    B --> C[Form Dummy Gate (Polysilicon) & SiN Spacers];
    C --> D[Etch Exposed DTI to First Depth (50Å) via CHF3/CF4 Plasma];
    D --> E[Form Recess in InGaAs Fin to Second Depth (150Å) via Citric Acid Wet Etch];
    E --> F[Grow Strained InAs Epitaxial Layer via MOCVD];
    F --> G[Replace Dummy Gate with High-k/Metal Gate];

Derivative 1.2: Operational Parameter Expansion - Ultra-High Aspect Ratio FinFET for Cryogenic Applications

Enabling Description:
A fabrication method for a semiconductor device intended for cryogenic computing, comprising: forming an ultra-high aspect ratio (AR > 10:1) silicon fin structure protruding from a bulk silicon-on-insulator (SOI) substrate. The fin structures are defined by electron beam lithography and deep reactive ion etching (DRIE) using a Bosch process. An isolation structure, specifically a sub-10nm feature size shallow trench isolation (STI) filled with a low-k dielectric such as a porous organosilicate glass (OSG), is formed to surround the silicon fin structure, with void-free filling achieved via supercritical CO2 drying. A gate-all-around (GAA) gate structure, utilizing a nanowire architecture, is formed, overlaying the top surface and all four side surfaces of a fully depleted portion of the silicon fin structure, and covering a portion of the OSG isolation structure. Post-gate and spacer formation (using a multi-layer SiN/SiO2 spacer), the exposed OSG isolation structure is etched down to a first depth (e.g., 20 Å) using a highly selective dry etch (e.g., C4F8/Ar plasma) optimized for maintaining fin integrity. Recesses are formed in the silicon fin structure at both source/drain sides of the gate structure to a second depth (e.g., 80 Å) using anisotropic cryogenic dry etching (e.g., SF6/O2 at -110°C) to maintain vertical sidewalls. These recesses are then filled with an epitaxially grown strained silicon-germanium (SiGe) layer (e.g., 50% Ge concentration, in-situ phosphorous doped) via low-temperature selective epitaxial growth (SEG) at 550°C, ensuring robust electrical contact and strain for enhanced carrier mobility at sub-4K operating temperatures. The critical dimensions for the fin width are below 5nm.

classDiagram
    class Substrate {
        +Silicon-on-Insulator (SOI)
        +Bulk Si
    }
    class FinStructure {
        +Material: Si
        +Aspect Ratio: >10:1 (Ultra-High)
        +Fabrication: E-beam Litho, DRIE (Bosch)
        +Width: <5nm
    }
    class IsolationStructure {
        +Type: STI
        +Material: Porous OSG (Low-k)
        +Fabrication: Supercritical CO2 drying
        +Recess Depth: First Depth (20Å)
    }
    class GateStructure {
        +Type: Gate-All-Around (GAA)
        +Architecture: Nanowire
        +Material: High-k/Metal (Post-RMG)
    }
    class Recess {
        +Location: Fin Source/Drain
        +Depth: Second Depth (80Å)
        +Fabrication: Cryogenic Dry Etch
    }
    class EpitaxialLayer {
        +Material: Strained SiGe (50% Ge, P-doped)
        +Fabrication: Low-Temp SEG (550°C)
    }
    Substrate --> FinStructure
    FinStructure --> IsolationStructure
    FinStructure --> GateStructure
    GateStructure --> IsolationStructure
    FinStructure <--> Recess
    Recess --> EpitaxialLayer

Derivative 1.3: Cross-Domain Application - FinFET-based Biosensor Array for Pathogen Detection

Enabling Description:
A fabrication method for a FinFET-based biosensor array, where the fin structure acts as the transducer surface for molecular binding. A silicon fin structure is formed protruding from a silicon-on-insulator (SOI) substrate, each fin tailored for a specific pathogen binding. An isolation structure, comprised of a biocompatible silicon nitride (SiNx) layer deposited by plasma-enhanced chemical vapor deposition (PECVD), surrounds each fin structure to electrically isolate individual sensor elements. A gate structure, consisting of a transparent indium tin oxide (ITO) electrode covered by a non-fouling hydrogel dielectric (e.g., polyethylene glycol diacrylate, PEGDA), is formed over a portion of the fin, leaving the active biosensing region of the fin exposed. After gate and spacer (SiO2) formation, the SiNx isolation structure not covered by the gate and spacers is selectively etched down to a first depth (e.g., 100 nm) using a dry etch, exposing additional fin sidewalls for functionalization. A recess is formed in the exposed silicon fin structure at a side of the gate structure to a second depth (e.g., 250 nm) using a KOH anisotropic wet etch, creating a larger surface area for analyte immobilization. This recess is then functionalized with specific antibodies (e.g., anti-Salmonella antibodies) via silane chemistry, and a "passive" epitaxial layer of SiO2 is deposited by atomic layer deposition (ALD) to backfill the remaining recess volume and passivate the non-functionalized surfaces, thereby forming the specific molecular binding sites on the fin surface. This design allows for label-free, real-time electrical detection of pathogen binding events.

graph TD
    A[Silicon Fin on SOI (Transducer)] --> B(Biocompatible SiNx Isolation);
    B --> C[Transparent ITO Gate + PEGDA Dielectric];
    C --> D[Etch Exposed SiNx Isolation (100nm)];
    D --> E[KOH Anisotropic Wet Etch for Fin Recess (250nm)];
    E --> F{Functionalize Recess with Antibodies};
    F --> G[ALD SiO2 Epitaxial Layer (Passivation)];
    G --> H(Real-time Electrical Detection);

Derivative 1.4: Integration with Emerging Tech - AI-Optimized FinFET Fabrication with IoT Monitoring and Blockchain Traceability

Enabling Description:
A fabrication method for a semiconductor device where process parameters are optimized by an AI-driven system and monitored in real-time via IoT sensors, with all process data recorded on a blockchain. Initially, a silicon fin structure is formed on a silicon substrate. The geometry of the fin (e.g., height, width, pitch) is dynamically adjusted based on AI feedback from simulated device performance models. An isolation structure, specifically a shallow trench isolation (STI) using flowable oxide (FOx) for gap fill, is formed, with its planarization (Chemical Mechanical Planarization - CMP) endpoint precisely controlled by IoT-enabled in-situ optical emission spectroscopy (OES) sensors. A gate structure (High-k/Metal Gate, RMG process) is formed over the fin. During the etching of the isolation structure exposed from the gate, the etch depth (first depth, 75 Å) is adjusted by an AI agent considering previous wafer data, real-time plasma etch uniformity sensors, and predicted device stress. All etching parameters (gas flow, RF power, pressure) are logged to a private blockchain for immutable process traceability. Recesses are formed in the fin structure at source/drain regions. The recess profile and depth (second depth, 200 Å) are continuously monitored by in-situ atomic force microscopy (AFM) and optical profilometry, with data streamed via IoT to the AI for closed-loop control of subsequent etching steps. An epitaxial layer (e.g., in-situ doped SiGe) is then grown in the recesses. The epitaxial growth parameters (temperature, precursor flow, pressure) are optimized in real-time by the AI to achieve target strain levels and dopant activation, with all growth metrics and source material batch IDs cryptographically linked on the blockchain for supply chain verification and quality assurance.

sequenceDiagram
    participant AI as AI Optimization System
    participant IoT as IoT Sensors (OES, Plasma, AFM, Profilometry)
    participant B as Blockchain Ledger
    participant Fab as Fabrication Tools

    Fab->>AI: Send simulated device performance data
    AI->>Fab: Dynamically adjust fin geometry
    Fab->>IoT: Stream CMP data (OES)
    IoT->>AI: Provide real-time CMP feedback
    AI->>Fab: Adjust CMP endpoint
    Fab->>B: Log CMP data & parameters
    Fab->>IoT: Stream plasma etch uniformity data
    IoT->>AI: Provide real-time etch feedback
    AI->>Fab: Adjust isolation etch parameters (First Depth)
    Fab->>B: Log etch parameters to blockchain
    Fab->>IoT: Stream recess profile data (AFM, Opt. Profilometry)
    IoT->>AI: Provide real-time recess feedback
    AI->>Fab: Adjust recess etch parameters (Second Depth)
    Fab->>B: Log recess parameters
    Fab->>AI: Send target strain, dopant activation
    AI->>Fab: Optimize epitaxial growth parameters
    Fab->>B: Log growth metrics & material batch IDs

Derivative 1.5: The "Inverse" or Failure Mode - Low-Power FinFET with Controlled Degradation

Enabling Description:
A fabrication method for a semiconductor device designed for low-power operation with predictable degradation characteristics, suitable for disposable or single-use applications. A fin structure is formed from a lightly doped p-type silicon (Si) on a bulk Si substrate. An isolation structure, specifically an STI filled with a deliberately porous low-density plasma-enhanced tetraethyl orthosilicate (PE-TEOS) oxide, is formed to surround the fin structure. This porous oxide is chosen for its higher moisture absorption and controlled dielectric degradation over time. A gate structure, composed of a sacrificial aluminum (Al) layer over a thin silicon dioxide (SiO2) gate dielectric, is formed. After gate and spacer (undoped SiO2) formation, the porous PE-TEOS isolation structure exposed from the gate and spacers is etched down to a first depth (e.g., 200 Å) using a buffered hydrofluoric acid (BHF) solution, specifically chosen to attack the porous oxide at a controlled rate, initiating a degradation mechanism. A shallow recess is formed in the silicon fin structure at the source/drain sides of the gate structure to a second depth (e.g., 300 Å), using a non-selective wet etch (e.g., NH4OH/H2O2) that creates a slightly rougher surface. This recess is then filled with a non-strained, intentionally defect-rich amorphous silicon (a-Si) layer via low-temperature plasma-enhanced chemical vapor deposition (PECVD). The a-Si layer is designed to have high trap densities and lower carrier mobility, contributing to the device's low-power characteristics and designed degradation profile (e.g., increasing leakage current over a predetermined operational lifespan due to trap-assisted tunneling and electromigration in the Al gate). This allows for predictable performance over a finite lifespan before transitioning to a limited-functionality or safe-fail mode.

stateDiagram
    [*] --> FinFormation
    FinFormation --> IsolationFormation
    IsolationFormation --> GateFormation
    GateFormation --> IsolationEtch_InitialDegradation
    IsolationEtch_InitialDegradation --> RecessFormation_DefectInduction
    RecessFormation_DefectInduction --> EpitaxialFill_LowPower
    EpitaxialFill_LowPower --> OperationalPhase
    OperationalPhase --> DegradationOnset : (Porous Oxide Degradation)
    DegradationOnset --> LimitedFunctionality : (Trap-assisted tunneling, Electromigration)
    LimitedFunctionality --> SafeFailMode
    SafeFailMode --> [*]

Combination Prior Art Scenarios

Here are at least three "Combination Prior Art" scenarios where US Patent 8993384 could be combined with existing open-source standards to make further developments obvious:

US8993384 + Open-Source Process Design Kit (PDK) Standards (e.g., OpenPDK or iPDK):
- Scenario: A competitor claims a new method for integrating a strained epitaxial layer into a FinFET process where the recess formation and epitaxial growth parameters are optimized for a specific design rule and material stack defined within an open-source Process Design Kit (PDK).
- Prior Art Argument: The core steps of forming a fin, isolation, gate, etching isolation to a first depth, forming a recess to a deeper second depth, and filling with an epitaxial layer (as taught by US8993384, Claim 1) are known. It would be obvious for a person skilled in the art, when implementing this known FinFET fabrication method using an open-source PDK (which provides standardized design rules, device models, and process flows for a given technology node), to optimize the specific etch depths, materials, and epitaxial growth parameters (e.g., temperature, pressure, precursor flow, dopant concentrations) to comply with or enhance the performance metrics defined within that open-source PDK. The selection and optimization of these parameters within a known framework like a PDK would be a routine engineering choice, not an inventive step. This combines the structural and methodological teachings of US8993384 with the publicly available and standardized constraints and guidance offered by an open-source PDK.
US8993384 + SEMI Standards for Wafer Fabrication Equipment & Materials:
- Scenario: A competitor patents a method for forming a FinFET with enhanced epitaxial layer quality, where the specific gas delivery system for selective epitaxial growth (SEG) and the wafer handling robotics are compliant with certain SEMI standards (e.g., SEMI E10, SEMI E54, SEMI F19).
- Prior Art Argument: US8993384 (Claim 1) clearly discloses the method of forming a fin, isolation, gate, etching isolation, forming a recess, and critically, forming an epitaxial layer to fill the recess. The enhancement of epitaxial layer quality (or any other process step) by utilizing manufacturing equipment and materials that adhere to widely adopted SEMI (Semiconductor Equipment and Materials International) standards is a well-known practice in the semiconductor industry. A person skilled in the art would understand that implementing the epitaxial growth step of US8993384 using commercially available, SEMI-compliant MOCVD or MBE equipment, which ensures standardized interfaces, contamination control, and consistent material delivery, would lead to improved process control and potentially higher quality epitaxial layers. Such compliance with industry standards, while leading to beneficial results, is a standard engineering implementation rather than an inventive modification of the core method.
US8993384 + Open-Source EDA Tools (e.g., OpenLane, Skywater PDK on GitHub):
- Scenario: A competitor claims a method for fabricating FinFETs with improved electrical characteristics achieved by simulating the strained epitaxial region using an open-source Electronic Design Automation (EDA) tool flow (e.g., incorporating process simulation modules within a framework like OpenLane).
- Prior Art Argument: The fundamental method for fabricating a FinFET with a strained epitaxial layer formed in a recess after differential etching of isolation (US8993384, Claim 1) is established. It would be obvious for a person skilled in the art to simulate and optimize the design and process parameters of such a device, including the geometry of the fin, the dimensions of the recess, and the characteristics of the epitaxial layer (e.g., composition, strain), using readily available open-source EDA tools. For example, using a tool flow like OpenLane (which integrates various open-source tools for ASIC design, including synthesis, placement, routing, and simulation, often leveraging open PDKs like Skywater 130nm) to model the structural and electrical impact of the epitaxial layer formation described in US8993384 would be a routine application of known computational methods to a known fabrication process. Any "improvement" derived from such simulation and optimization, when applied to the core method of US8993384, would be considered an obvious engineering refinement.