Obviousness

To assess the obviousness of US patent 8993384 under 35 U.S.C. § 103, we will analyze combinations of prior art references that would render the independent claim (Claim 1) obvious to a person having ordinary skill in the art (POSA).

Claim 1 of US8993384 (Fabrication Method):

1. Forming a fin structure, protruding from a surface of a substrate, wherein the fin structure comprises a top surface and two side surfaces;
2. Forming an isolation structure to surround the fin structure;
3. Forming a gate structure, overlaying the top surface and the two side surfaces of a portion of the fin structure, and covering a portion of the isolation structure;
4. After the step of forming the gate structure, etching the isolation structure exposed from the gate structure until a top surface of the isolation structure is etched down to a first depth;
5. Forming a recess in the fin structure at a side of the gate structure; and
6. Forming an epitaxial layer to fill up the recess, wherein a bottom surface of the recess has a second depth, and the second depth is deeper than the first depth. [cite: Original Patent Text]

Hypothetical Person Having Ordinary Skill in the Art (POSA):
A POSA in the field of semiconductor device fabrication would typically possess a Bachelor's degree in electrical engineering, materials science, or a related field, along with several years of experience in semiconductor process development, particularly involving FinFETs, strain engineering, and epitaxial growth techniques. Such a person would be familiar with common challenges in these processes, such as defect formation.

Prior Art References and their Relevance:
The patent itself lists several prior art documents, some of which are particularly relevant to FinFETs, strained channels, and recessed structures.

1. US20040195624A1 (Strained silicon fin field effect transistor): This reference discloses the fundamental concept of a FinFET device and the use of strained silicon to enhance performance. It provides the context for steps 1, 2, 3 (forming fin, isolation, and gate structures in a FinFET) and the general idea of an epitaxial layer for strain (step 6). [cite: Original Patent Text]
2. US7525160B2 (Multigate device with recessed strain regions): This patent explicitly teaches forming "recessed strain regions" in a multigate device. This directly implies creating recesses in the active semiconductor body (e.g., a fin structure) and filling these recesses with strain-inducing epitaxial material. This reference thus anticipates steps 5 (forming a recess in the fin structure) and 6 (filling the recess with an epitaxial layer) within a multigate context similar to a FinFET. [cite: Original Patent Text]

Differences Between the Prior Art and Claim 1:
The primary distinguishing feature of Claim 1 of US8993384 lies in the specific etching of the isolation structure (step 4) to a "first depth" and the subsequent formation of a recess in the fin structure (step 5) where the "bottom surface of the recess has a second depth, and the second depth is deeper than the first depth" (step 6). This defines a specific geometric relationship where the bottom of the fin recess is physically lower than the top surface of the adjacent, etched isolation structure.

Motivation to Combine and Obviousness Analysis:
The background section of US8993384 clearly articulates a known problem in the field: "due to the continuous shrinkage in the size of the semiconductor devices, the aspect ratio of the epitaxial layer also gets higher, which often incur unwanted defects, such as void defects in the epitaxial layer." It further states, "These defects inside the epitaxial layer reduce the stress required to be imposed onto the corresponding channel region. As a result, how to prevent the formation of the defects inside the epitaxial layer is an important issue." [cite: Original Patent Text]

A POSA, familiar with FinFETs incorporating strained regions (as taught by US20040195624A1 and US7525160B2), would undoubtedly encounter this common and acknowledged problem of void defects during the epitaxial growth process, especially when forming deep recesses for strain in increasingly smaller devices.

To address this known problem of voids and facilitate robust epitaxial filling, a POSA would be motivated to optimize the geometry of the surrounding structures. The patent itself highlights the solution: "Since the process for etching the isolation structure is optionally carried out prior to and/or after the formation of the recess, the height of the isolation structure at two sides of the gate structure may be reduced. In this way, the epitaxial layer may be filled into the corresponding recess easily during the epitaxial growth process. Furthermore, since the epitaxial structure is not sealed during the epitaxial growth process, the void defects may be also avoided as a result." [cite: Original Patent Text]

This motivation directly points to reducing the height of the isolation structure adjacent to the epitaxial growth region (Claim 1, step 4) as an obvious engineering solution to improve the aspect ratio for filling and prevent premature sealing, thereby avoiding void defects. The specific geometric outcome described in Claim 1—where the bottom surface of the fin recess (second depth) is deeper than the top surface of the etched isolation structure (first depth) (as visually confirmed by Figures 8 and 11 of US8993384)—would be a natural and routine design choice for a POSA attempting to ensure complete and defect-free epitaxial growth into the deeper fin recesses. By reducing the height of the isolation structure, even if its top surface remains above the deepest part of the fin recess, the overall constraint on epitaxial material flow into the recess is alleviated. The exact depths would be a matter of routine optimization to achieve the desired defect-free growth.

Conclusion:
A combination of US20040195624A1 and US7525160B2, combined with the common general knowledge in the art regarding the challenges of void formation in high-aspect-ratio epitaxial growth (as explicitly stated in the background of US8993384), would render Claim 1 obvious. A person having ordinary skill in the art would have been motivated to combine the teachings of FinFETs with strained regions and recessed epitaxial areas, and then, to overcome the known problem of epitaxial voids, would have found it obvious to reduce the height of the adjacent isolation structure to facilitate easier and more complete filling of the recesses.