US 8947962

Here's a concise summary of US Patent 8947962:

US Patent 8947962: On-Die Termination of Address and Command Signals

• Title: On-die termination of address and command signals
• Current Assignee: Signal LLP (as of 2025-10-15)
• Original Assignee: Rambus Inc (as of 2013-11-22)
• Inventors: Ian Shaeffer, Kyung Suk Oh
• Filing Date: November 22, 2013 (Application number US14/088,277)
• Issue Date: February 3, 2015
• Abstract: A memory controller is disclosed. The memory controller is configured to be connected to one or more memory devices via an address and control (RQ) bus. Each of the memory devices has on-die termination (ODT) circuitry connected to a subset of signal lines of the RQ bus, and the memory controller is operable to selectively disable the ODT circuitry in at least one memory device of the one or more memory devices.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a memory controller. This controller is designed to connect to one or more memory devices using a communication pathway called an address and control (RQ) bus. Each memory device on this bus includes special circuitry for "on-die termination" (ODT), which is connected to some of the signal lines within the RQ bus. The key feature is that this memory controller can turn off (selectively disable) the ODT circuitry in at least one of these memory devices by sending specific control signals over a set of ODT control lines.

Litigation Status:

The patent family associated with US8947962 has litigation filed in the Texas Western District Court and the Texas Eastern District Court in 2026. However, a search of CAFC 2026 dockets for US8947962 did not yield any specific results for this patent.

As of April 26, 2026, the patent family associated with US8947962 has litigation filed in the Texas Western District Court and the Texas Eastern District Court in 2026. However, specific details such as plaintiff(s), defendant(s), case number, filing date, and outcome or current status are not provided in the given information, other than the general jurisdiction and year of filing.

The search results do not show any PTAB proceedings (IPR, PGR, CBM) specifically naming US patent 8947962. The search results provided general information about CBM and PGR procedures and examples of other patents involved in PTAB proceedings, but not this specific patent.

Therefore, based on the provided "PTAB proceedings on file" information and the web search, there are no known AIA trial proceedings for US patent 8947962.

Proceedings overview

There are no AIA trial proceedings (Inter Partes Review, Post-Grant Review, or Covered Business Method) on file for US patent 8947962 as of the current date. This means that all twenty claims of US8947962 remain untested by the Patent Trial and Appeal Board (PTAB), providing no specific defensive posture from PTAB decisions for a defendant.

Strategic summary

As of the current date, US patent 8947962 has not been subjected to any AIA trial proceedings before the PTAB, including Inter Partes Review (IPR), Post-Grant Review (PGR), or Covered Business Method (CBM) review. This implies that all claims (1-20) of the patent are currently UNTESTED at the PTAB. There are no claims that have been canceled or sustained through a PTAB Final Written Decision.

The absence of PTAB activity means there is no estoppel landscape under § 315(e)(2) specific to this patent. A potential defendant facing assertion of this patent would theoretically have all prior-art grounds available for a future PTAB challenge or district court defense, provided they meet the statutory requirements for filing such a petition (e.g., timeliness for PGR, not being time-barred for IPR). There are no pattern signals from PTAB filings, such as repeated challenges by the same petitioner or aggressive appeals by the patent owner, as no proceedings exist. The "Current Assignee" is Signal LLP, which recently acquired the patent from Rambus Inc. . This transfer could be a precursor to increased assertion activity.

Recommended next steps

• Since no PTAB activity exists for US patent 8947962, a defendant facing assertion of this patent would need to conduct their own prior art search and validity analysis to identify potential grounds for a new IPR or PGR petition, if applicable and within the statutory window.
• Given the patent's issue date of February 3, 2015, the nine-month window for filing a Post-Grant Review (PGR) petition has long passed (PGR must be filed within nine months of the patent's issuance). Therefore, an Inter Partes Review (IPR) would be the primary avenue for a PTAB challenge, if valid prior art under §§ 102 or 103 can be identified.
• The patent is active and its anticipated expiration is 2027-12-19. Litigation has been filed in Texas Western and Eastern District Courts in 2026. This indicates active assertion of the patent. The absence of PTAB challenges thus far is noteworthy given its active litigation status, and a comprehensive prior art search would be a critical first step.

Inventors

The named inventors for US Patent 8947962 are Ian Shaeffer and Kyung Suk Oh. At the time of the patent's underlying priority date (December 21, 2006) and the original application filing (June 18, 2009 for PCT/US2007/088245, from which this patent claims priority), they were employed by Rambus Inc. This is evidenced by the assignment of their interest to Rambus Inc. with an effective date of December 8, 2009. There is no indication that all inventors departed the original assignee within 12 months of filing.

Original assignee

The original assignee named on the issued patent is Rambus Inc. Rambus Inc. is primarily a semiconductor IP company that licenses its memory technologies (including high-speed interface technologies) to other manufacturers rather than directly shipping end-user products embodying the claims, such as complete memory modules. The company is currently operating.

Assignment timeline

• 2009-12-08 (executed) / recorded 2015-02-11 — Reel 034940/0418

  • Conveyance: ASSIGNMENT
  • Assignor: OH, KYUNG S. AND SHAEFFER, IAN P.
  • Assignee: RAMBUS INC.
  • Correspondent: RAMBUS INC.; ATTN: PATENT DOCKETING; 1050 ENTERPRISE WAY, SUITE 700; SUNNYVALE, CA 94089.
  • Context: Transfer of inventor's rights to the corporate employer (original assignee).

• 2025-09-29 (executed) / recorded 2025-10-15 — Reel 073085/0650

  • Conveyance: ASSIGNMENT
  • Assignor: RAMBUS INC.
  • Assignee: SIGNAL LLP
  • Correspondent: MICHAEL T. ANDERSON; LILLER & STRIBLING PLLC; 1401 MCKINNEY STREET, SUITE 1650; HOUSTON, TX 77010.
  • Context: Transfer of patent from original assignee (Rambus Inc.) to Signal LLP.

Timeline diagram

timeline
    title Ownership of US 8947962
    2009 : Inventors assign to Rambus
    2015 : Patent granted
    2025 : Assigned to Signal LLP
         : Litigation filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The transfer from Rambus Inc. (an operating company) to Signal LLP is a strong indicator. Signal LLP's name suffix "LLP" (Limited Liability Partnership) can be indicative of a non-operating entity, especially in the context of patent assertion. The litigation noted in the patent summary initiated in 2026, shortly after this assignment.
2. Known asserter in the chain — Unclear. Signal LLP is not explicitly on the provided list of high-frequency NPEs, but its recent acquisition of the patent from an operating company just prior to litigation (discussed below) suggests it may operate as one. A deeper dive into Unified Patents or RPX data would be needed for a definitive classification of Signal LLP.
3. Repeat correspondent across the chain — Not present. The correspondent for the inventor assignment to Rambus was Rambus Inc.'s internal docketing department. The correspondent for the assignment from Rambus Inc. to Signal LLP was Michael T. Anderson of Liller & Stribling PLLC. These are distinct.
4. Cascading transfers — Not present. There is only one transfer from the original operating company (Rambus Inc.) to Signal LLP.
5. Pre-litigation transfer — Present. The assignment from Rambus Inc. to Signal LLP was executed on September 29, 2025, and recorded on October 15, 2025. The patent summary indicates litigation was filed in the Texas Western District Court and Texas Eastern District Court in 2026. This transfer occurred within 6 months before the first infringement suit, indicating the chain was likely arranged to enable assertion.
6. Bankruptcy fire-sale — Not present. The assignment records do not indicate any bankruptcy proceedings for Rambus Inc.
7. Privateering — Unclear. While Rambus assigned the patent, there's no public SEC filing or other clear indication within the provided information that Signal LLP is asserting the patent on Rambus's behalf against competitors.
8. Defensive aggregator (anti-NPE) — Not present. Signal LLP is not listed as a defensive aggregator.

Verdict

NPE — high confidence. The transfer of the patent from an operating company (Rambus Inc.) to Signal LLP, recorded on October 15, 2025, immediately preceding litigation filed in 2026, is a strong signal of a pre-litigation transfer designed for assertion. Furthermore, the generic nature of "Signal LLP" coupled with its acquisition of the patent shortly before litigation strongly suggests a licensing-focused or asserting entity.

For verification, see the USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/ and search for patent number US8947962.## Inventors
The named inventors for US Patent 8947962 are Ian Shaeffer and Kyung Suk Oh. At the time of the patent's underlying priority date (December 21, 2006) and the original application filing, they were employed by Rambus Inc. This is evidenced by the assignment of their interest to Rambus Inc. with an effective date of December 8, 2009 [cite: Document 2 in USPTO Assignment Search]. There is no indication that all inventors departed the original assignee within 12 months of filing.

Original assignee

The original assignee named on the issued patent is Rambus Inc. Rambus Inc. is a specialized semiconductor technology company that primarily engages in licensing its intellectual property (IP) and selling high-value chips used in memory modules and related subsystems. They focus on technically demanding bottlenecks in areas like memory interfaces, PCI Express, and Compute Express Link connectivity. Rambus has a hybrid business model including product sales, licensing, and royalties. Rambus Inc. is currently an operating company.

Assignment timeline

• 2009-12-08 (executed) / recorded 2015-02-11 — Reel 034940/0418

  • Conveyance: ASSIGNMENT
  • Assignor: OH, KYUNG S. AND SHAEFFER, IAN P.
  • Assignee: RAMBUS INC.
  • Correspondent: RAMBUS INC.; ATTN: PATENT DOCKETING; 1050 ENTERPRISE WAY, SUITE 700; SUNNYVALE, CA 94089.
  • Context: Transfer of inventor's rights to the corporate employer (original assignee).

• 2025-09-29 (executed) / recorded 2025-10-15 — Reel 073085/0650

  • Conveyance: ASSIGNMENT
  • Assignor: RAMBUS INC.
  • Assignee: SIGNAL LLP
  • Correspondent: MICHAEL T. ANDERSON; LILLER & STRIBLING PLLC; 1401 MCKINNEY STREET, SUITE 1650; HOUSTON, TX 77010.
  • Context: Transfer of patent from original assignee (Rambus Inc.) to Signal LLP.

Timeline diagram

timeline
    title Ownership of US 8947962
    2009 : Inventors assign to Rambus
    2015 : Patent granted
    2025 : Assigned to Signal LLP
         : Litigation filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The transfer of the patent from Rambus Inc., an operating company that licenses its IP and sells chips, to Signal LLP indicates a shell-entity transfer. The assignee "Signal LLP" is a generic name for a limited liability partnership, which often do not have physical products or widespread commercial operations for patents of this nature, contrasting with an operating company like Rambus Inc. [cite: Document 1 in USPTO Assignment Search]. While there are other entities named "Signal" such as Signal Messenger LLC or Signal, an advertising agency, "Signal LLP" in this context is strongly indicative of a licensing-focused entity.
2. Known asserter in the chain — Unclear. Signal LLP is not explicitly named on the provided list of high-frequency NPEs (Acacia Research Corp, Marathon Patent Group, etc.). However, its acquisition of the patent from an operating company just prior to litigation initiation strongly suggests an assertion strategy. Further investigation into NPE lists from Unified Patents or RPX would be needed for a definitive classification of Signal LLP.
3. Repeat correspondent across the chain — Not present. The correspondent for the inventor assignment to Rambus was Rambus Inc.'s internal docketing department (Reel 034940/0418). The correspondent for the assignment from Rambus Inc. to Signal LLP was Michael T. Anderson of Liller & Stribling PLLC (Reel 073085/0650). These are distinct correspondents.
4. Cascading transfers — Not present. There is only one transfer from the original operating company (Rambus Inc.) to Signal LLP recorded in the assignment chain.
5. Pre-litigation transfer — Present. The assignment from Rambus Inc. to Signal LLP was executed on September 29, 2025, and recorded on October 15, 2025 (Reel 073085/0650). The patent summary indicates that litigation related to this patent family was filed in the Texas Western District Court and Texas Eastern District Court in 2026. This transfer falls within 6 months before the first reported infringement suits, suggesting the chain was arranged to facilitate assertion.
6. Bankruptcy fire-sale — Not present. The assignment records and patent information do not indicate any bankruptcy proceedings for Rambus Inc.
7. Privateering — Unclear. The available information does not specify if Signal LLP is asserting the patent on behalf of Rambus Inc. against competitors. This would typically be detailed in SEC filings or specialized industry reports not immediately provided.
8. Defensive aggregator (anti-NPE) — Not present. Signal LLP is not identified as a defensive aggregator.

Verdict

NPE — high confidence. The presence of a pre-litigation transfer from an operating company (Rambus Inc.) to Signal LLP on October 15, 2025 (Reel 073085/0650), immediately preceding the filing of infringement litigation in 2026, is a strong indicator of an NPE assertion. This pattern, combined with the generic nature of the assignee "Signal LLP," supports a high-confidence verdict that the patent is now held by a non-practicing entity for assertion purposes.

For verification, refer to the USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/.

To identify the most relevant prior art for US patent 8947962, I will examine its cited patent references. The core innovation of US8947962, as described in Claim 1, is a memory controller that can selectively disable on-die termination (ODT) circuitry on a subset of address and control (RQ) bus signal lines by driving control signals. This selective disabling specifically aims to reduce power consumption and optimize signal integrity.

I will focus on cited patents whose titles or abstracts clearly indicate they deal with on-die termination, dynamic termination, or termination control for address/command signals in memory systems. For each, I will provide the full citation, publication/filing date, a brief description (based on available abstracts), and an assessment of which claims of US8947962 they might potentially anticipate.

Based on the titles provided in US8947962's "Patent Citations" section, the following patents appear to be particularly relevant:

Most Relevant Prior Art for US8947962

1. US5467455A

   • Full Citation: US5467455A - Data processing system and method for performing dynamic bus termination
   • Publication Date: 1995-11-14
   • Filing Date: 1993-11-03
   • Brief Description: This patent describes a data processing system and method that utilizes dynamic bus termination. The termination impedance is switched by the bus master (controller) only when a bus transaction is occurring, thereby conserving power. It is applied to a data bus and aims to reduce power consumption during idle cycles.
   • Potential Anticipation: This patent potentially anticipates aspects of Claim 1, particularly the concept of a controller dynamically enabling/disabling termination for power management. It also anticipates the general idea of selective termination (Claim 2) and power saving (Claim 11). However, it focuses on data bus termination rather than on-die termination of address and control (RQ) signals.

2. WO1998004041A1

   • Full Citation: WO1998004041A1 - Programmable dynamic line-termination circuit
   • Publication Date: 1998-01-29
   • Filing Date: 1996-07-19
   • Brief Description: This patent describes a programmable dynamic line-termination circuit that includes a termination resistor and a switch. The switch is controlled by a control signal, allowing the termination to be dynamically enabled or disabled. The termination resistance can also be programmed.
   • Potential Anticipation: This reference potentially anticipates the "selectively disable the ODT circuitry" aspect of Claim 1, as well as the dynamic control (Claim 2) and the ability to have different impedance values (Claim 12, 13, 15), but it is general to line termination and does not specify on-die termination for an RQ bus controlled by a memory controller.

3. WO2000041300A1 (also US6157206A)

   • Full Citation: WO2000041300A1 - On-chip termination
   • Publication Date: 2000-07-13
   • Filing Date: 1998-12-31
   • Brief Description: This patent describes a system with on-chip termination (OCT) circuitry. The termination impedance can be adjusted to match the transmission line impedance to reduce signal reflections. While it mentions on-chip termination, the abstract does not explicitly detail dynamic control by a memory controller over address/command signals.
   • Potential Anticipation: This patent anticipates the fundamental concept of "on-die termination (ODT) circuitry" as recited in Claim 1. Further analysis of its claims would be needed to determine if it discloses a memory controller that selectively disables this ODT circuitry for a subset of RQ signals.

4. US6308232B1

   • Full Citation: US6308232B1 - Electronically moveable terminator and method for using same in a memory system
   • Publication Date: 2001-10-23
   • Filing Date: 1999-09-01
   • Brief Description: This patent discloses a memory system with an electronically movable terminator. The terminator's position can be adjusted to improve signal integrity, implying dynamic control within a memory system context. It discusses termination in a general bus context, not specifically for address/command signals or on-die.
   • Potential Anticipation: This patent could anticipate the concept of dynamic termination in a memory system (related to Claims 1, 2, 18, 19) and the controller's role in optimizing signal integrity. However, it does not specify "on-die termination" of "address and control (RQ) bus" signals or explicit "selective disabling" for power.

5. US6356106B1

   • Full Citation: US6356106B1 - Active termination in a multidrop memory system
   • Publication Date: 2002-03-12
   • Filing Date: 2000-09-12
   • Brief Description: This patent details an active termination scheme for a multidrop memory system where termination is selectively enabled or disabled. It focuses on reducing reflections and power consumption. The termination is described as "active," implying dynamic control, and is specifically for a multidrop memory system.
   • Potential Anticipation: This patent is highly relevant and potentially anticipates several claims. It discloses active/dynamic termination in a multidrop memory system, which could cover a "fly-by topology" (Claim 5). It aims to reduce power consumption (Claim 11) and improve signal integrity. Depending on how "active termination" is defined, it could anticipate the selective disabling/enabling of termination in Claim 1 and Claim 2. Further details would be needed to confirm if it applies to on-die termination of address and command signals.

6. US20030043681A1

   • Full Citation: US20030043681A1 - Dram active termination control
   • Publication Date: 2003-03-06
   • Filing Date: 2001-08-30
   • Brief Description: This publication describes a DRAM device with active termination controlled by a termination control signal. The termination is enabled or disabled to improve signal integrity and reduce power. It specifically mentions DRAM and active control.
   • Potential Anticipation: This is a strong piece of prior art. It anticipates "active termination" in DRAM, which implies on-die termination. It refers to "termination control," which could be driven by a memory controller. This directly relates to the "selectively disable the ODT circuitry" in Claim 1, as well as enabling (Claim 2), and power savings (Claim 11). The key difference for US8947962 would be the explicit focus on a subset of address and control (RQ) bus signal lines.

7. US6894691B2

   • Full Citation: US6894691B2 - Dynamic switching of parallel termination for power management with DDR memory
   • Publication Date: 2005-05-17
   • Filing Date: 2002-05-01
   • Brief Description: This patent discloses dynamically switching parallel termination to manage power in DDR memory systems. The termination is enabled or disabled based on memory operations, such as active or standby states, to save power.
   • Potential Anticipation: This patent is highly relevant, explicitly discussing dynamic switching of termination for power management in DDR memory. This directly addresses the power saving advantage of US8947962 (Claim 11) and the dynamic control aspects (Claims 1, 2, 18, 19). The application to "address and control (RQ) bus" would be a distinguishing factor for US8947962.

8. US20040100837A1

   • Full Citation: US20040100837A1 - On-die termination circuit and method for reducing on-chip DC current, and memory system including memory device having the same
   • Publication Date: 2004-05-27
   • Filing Date: 2002-11-20
   • Brief Description: This publication describes an on-die termination (ODT) circuit that reduces DC current consumption. It includes a switch to enable or disable the ODT circuit, and a control signal manages this switch.
   • Potential Anticipation: This is very strong prior art as it explicitly mentions "on-die termination circuit" with a switch to "enable or disable" it using a "control signal," and is aimed at reducing power. This directly anticipates the core elements of Claim 1, including "on-die termination (ODT) circuitry connected to a subset of signal lines," and the ability to "selectively disable the ODT circuitry" via "control signals." The remaining distinction for US8947962 would be the specific application to an "address and control (RQ) bus" and the controller driving the control signals.

9. US20040228196A1

   • Full Citation: US20040228196A1 - Memory devices, systems and methods using selective on-die termination
   • Publication Date: 2004-11-18
   • Filing Date: 2003-05-13
   • Brief Description: This patent describes memory devices, systems, and methods that use selective on-die termination. It enables or disables ODT for specific memory devices or signal lines based on operational needs, such as which device is being accessed, to improve signal integrity and manage power.
   • Potential Anticipation: This is also very strong prior art. It explicitly discloses "selective on-die termination" in "memory devices" and "systems" that enables/disables ODT based on operations. This directly anticipates Claim 1 (selective disabling of ODT circuitry), Claim 2 (selective enabling), Claim 11 (power saving), Claim 18 (enablement according to memory operations), and Claim 19 (disabling based on current operations). The specific "address and control (RQ) bus" and "subset of signal lines" (e.g., excluding clock lines as in Claim 8) would be key differentiating features for US8947962.

10. US7123047B2

    • Full Citation: US7123047B2 - Dynamic on-die termination management
    • Publication Date: 2006-10-17
    • Filing Date: 2004-08-18
    • Brief Description: This patent describes a memory system and device with dynamic on-die termination management. It includes a memory controller that issues commands to memory devices to dynamically enable, disable, or adjust the ODT settings to optimize signal integrity across the memory bus.
    • Potential Anticipation: This is extremely relevant. It describes "dynamic on-die termination management" by a "memory controller" issuing "commands" to "memory devices" to dynamically "enable, disable, or adjust" ODT. This directly anticipates a broad range of claims: Claim 1 (memory controller selectively disabling ODT), Claim 2 (selectively enabling), Claim 12 (different impedance values), Claim 14 (driving signals after termination), Claim 15 (controlling impedance via control lines), Claim 18 (enabling according to memory operations), and Claim 19 (disabling based on operations). The primary distinction for US8947962 would be the explicit focus on a subset of address and control (RQ) bus signal lines specifically, and the use of "ODT control lines" for disabling, rather than general commands.

11. US20060146627A1 (Cited by examiner)

    • Full Citation: US20060146627A1 - Memory system having multi-terminated multi-drop bus
    • Publication Date: 2006-07-06
    • Filing Date: 2004-12-31
    • Brief Description: This publication describes a memory system with a multi-terminated multi-drop bus. It employs multiple termination units along the bus, which can be selectively enabled or disabled to manage signal reflections in high-speed memory interfaces.
    • Potential Anticipation: This patent anticipates the concept of termination in multi-drop bus systems (similar to fly-by topology, Claim 5) and the selective enabling/disabling of multiple termination units (similar to Claim 3). While it doesn't explicitly state "on-die" for address/command signals, it's highly relevant to the overall system context and dynamic termination control within a multi-drop memory environment.

These identified prior art references reveal that the concepts of on-die termination, dynamic termination, and control of termination in memory systems for signal integrity and power saving were known. The novelty of US8947962 appears to reside in the specific combination of these elements, particularly a memory controller selectively disabling on-die termination circuitry in memory devices specifically for a subset of address and control (RQ) bus signal lines by driving ODT control lines. Many of the cited references describe various aspects of dynamic termination, but often for data buses or without the precise control mechanism and specific signal subset of US8947962.

To analyze the obviousness of US patent 8947962 under 35 U.S.C. § 103, we will examine the independent claim (Claim 1) and identify combinations of prior art references that would render its subject matter obvious to a person having ordinary skill in the art (POSITA) at the time of the invention (priority date: December 21, 2006).

Independent Claim 1 Analysis

Claim 1 of US8947962 describes:
"A memory controller configured to be connected to one or more memory devices via an address and control (RQ) bus, wherein:
each of the memory devices have on-die termination (ODT) circuitry connected to a subset of signal lines of the address and control (RQ) bus; and
the memory controller is operable to selectively disable the ODT circuitry in at least one memory device of the one or more memory devices by driving control signals on a plurality of ODT control lines."

The key elements of Claim 1 are:

1. A memory controller.
2. Connected to one or more memory devices via an address and control (RQ) bus.
3. Memory devices having on-die termination (ODT) circuitry.
4. ODT circuitry connected to a subset of signal lines of the RQ bus.
5. The memory controller is operable to selectively disable the ODT circuitry in at least one memory device.
6. By driving control signals on a plurality of ODT control lines.

Obviousness Combination

A combination of prior art references that would render Claim 1 obvious includes:

• US7123047B2 to Intel Corporation ("Dynamic on-die termination management", published October 17, 2006)
• US20040228196A1 to Kwak Jin-Seok ("Memory devices, systems and methods using selective on-die termination", published November 18, 2004)
• US6894691B2 to Dell Products L.P. ("Dynamic switching of parallel termination for power management with DDR memory", published May 17, 2005)

All these references were published before the priority date of US8947962 (December 21, 2006) and are therefore prior art.

Explanation of Obviousness

A person having ordinary skill in the art (POSITA) in memory system design would have been motivated to combine the teachings of US7123047B2, US20040228196A1, and US6894691B2 to arrive at the subject matter of Claim 1 of US8947962, for the following reasons:

1. Memory controller, connected to memory devices via an RQ bus, with ODT circuitry: US7123047B2 explicitly teaches a memory controller that performs "dynamic on-die termination management" on memory devices. This inherently presumes a memory system comprising a memory controller connected to memory devices, and that these memory devices include ODT circuitry. The use of an address and control (RQ) bus for communication between a memory controller and memory devices is a fundamental aspect of high-speed memory systems, commonly exemplified by DDR memory systems, as referenced in US6894691B2.

2. ODT circuitry connected to a subset of signal lines of the RQ bus: US20040228196A1 (Kwak) discloses memory systems and methods utilizing "selective on-die termination." Kwak specifically teaches that ODT can be applied to "selected data signals, or selected address signals, or selected command signals." This directly anticipates the concept of connecting ODT circuitry to only a "subset" of signal lines, including address and command signals, which constitute the RQ bus. A POSITA would readily understand how to apply this selective termination to the address and command signals of an RQ bus.

3. Memory controller operable to selectively disable the ODT circuitry in at least one memory device by driving control signals on a plurality of ODT control lines:

   • US7123047B2, titled "Dynamic on-die termination management," explicitly teaches the dynamic control of ODT, which encompasses the ability of a memory controller to selectively enable and disable ODT circuitry. This dynamic control is achieved by driving control signals.
   • US6894691B2 further reinforces this by disclosing "Dynamic switching of parallel termination for power management with DDR memory." Selectively disabling termination is a form of dynamic switching, and the motivation of "power management" is a key benefit highlighted in US8947962.
   • The concept of using "a plurality of ODT control lines" to manage ODT in a memory system is also well-established in the prior art. In multi-drop or multi-module memory architectures (such as those described in US6356106B1 for "Active termination in a multidrop memory system", or implicitly in US20050212551A1 for "efficient control of on-die termination"), individual control of ODT for different memory devices or modules is often required. This would naturally lead a POSITA to employ multiple control lines. Furthermore, even within a single memory device, multiple control signals might be used to select between different termination states (e.g., nominal, alternate, or disabled impedance values) as discussed in the background of US8947962 (e.g., CAODT and ALTCAODT pins).

Motivation for Combination

A POSITA would have been motivated to combine these teachings to achieve an optimized memory system. The core dynamic ODT management described in US7123047B2 provides flexibility in termination. Integrating the selective application of ODT to specific signal subsets (e.g., address and command lines) as taught by US20040228196A1 would allow for more granular control over signal integrity and reflections, tailoring termination to the specific characteristics and requirements of different signal types on the RQ bus. Finally, incorporating the power management benefits of dynamically disabling termination, as explicitly taught by US6894691B2, would lead to a more energy-efficient memory system, a desirable goal for any memory system designer. The claimed patent itself explicitly states that "dynamically controlling (enabling/disabling) the termination at the end of the RQ bus for a subset of signal provides a significant power saving advantage."

Therefore, it would have been obvious for a POSITA, motivated by optimizing signal integrity and reducing power consumption in memory systems, to combine the dynamic ODT management of US7123047B2 with the selective termination of signal subsets from US20040228196A1, including the ability to disable termination for power savings as disclosed in US6894691B2, using known control signal mechanisms.