US 8898395

US Patent 8898395: Memory Management for Cache Consistency

Title: Memory management for cache consistency

Assignee:

• Current: Intellectual Ventures II LLC (as of January 16, 2024)
• Original: Individual (subsequently assigned to TRANSMETA LLC, then INTELLECTUAL VENTURE FUNDING LLC, then INTELLECTUAL VENTURES HOLDING 81 LLC)

Inventors: Guillermo J. Rozas

Filing Date: May 15, 2008

Issue Date: November 25, 2014

Abstract:
The patent describes methods and systems for maintaining cache consistency. It involves executing a group of instructions that can include multiple memory operations. When an instruction within this group causes a cache line to be accessed, an associated indicator for that instruction group is updated to reflect this access. This indication remains active until the instruction group's execution concludes. If an external agent (e.g., another processor or a Direct Memory Access (DMA) system) attempts to snoop the cache and finds that the cache line, or any other cache line, is indicated as being accessed by an instruction group, that instruction group is rolled back and reissued. If no cache line is indicated as accessed, the snoop proceeds using a conventional cache coherency protocol (e.g., MESI).

Plain-Language Overview of Independent Claims:

• Independent Claim 1 (Method): This claim outlines a method for managing cache memory involving multiple instruction groups.

  1. A "first bit" of an indicator for a cache line is set if a processor accesses that cache line while executing a "first group of instructions."
  2. A "second bit" of the same indicator is set if the processor also accesses the cache line while executing a "second group of instructions," and the first bit is still set.
  3. If an "agent other than said processor" (an external agent) tries to access the cache line (as part of executing a "third group of instructions"), the system checks these bits.
  4. If the first bit is set, the first group of instructions is rolled back. If the second bit is set, the second group of instructions is rolled back. This rollback happens before the external agent is allowed to access the cache line.
  5. If neither bit is set, the external agent is immediately granted access.
  6. The overall processing of the first and second instruction groups is determined by the state of this indicator.

• Independent Claim 7 (Computer System): This claim describes a computer system designed to implement the method of Claim 1. It comprises a processor, a cache memory, and a memory unit that stores specific instructions. These instructions guide the processor to:

  1. Execute a first group of instructions that reads a cache line and sets a first indicator bit.
  2. Execute a second group of instructions that also reads the cache line and sets a second indicator bit while the first bit is still set.
  3. When a third group of instructions (from an external agent) attempts to access the cache line, the system rolls back the first and/or second instruction groups if their respective bits are set, prior to granting access to the external agent. Otherwise, access is granted.
  4. The system also includes instructions to process the first and second instruction groups based on the indicator's value.

• Independent Claim 13 (Method of Managing Shared Memory): This claim details a method for managing shared memory in a computer system:

  1. A processor executes a first group of instructions.
  2. A cache line is associated with a first state (e.g., from MESI protocol) and then a "second state" which specifically indicates it was accessed by the first instruction group.
  3. The processor then executes a second group of instructions.
  4. During the execution of the second group, the cache line is associated with a "third state" indicating it was accessed by the second group.
  5. If a third group of instructions attempts to access the cache line, both the first and second groups of instructions are rolled back before access is granted to the third group.

• Independent Claim 19 (Computer System): This claim describes a computer system featuring a processor, a cache memory, and a memory unit. The memory unit has multiple "indicator bits" per cache line.

  1. A first indicator bit for a cache line is set when the processor accesses it during a first instruction group's execution and cleared when that group finishes.
  2. A second indicator bit for the same cache line is set when the processor accesses it during a second instruction group (running in parallel) and cleared when that group finishes.
  3. If an external agent attempts to access the cache line, the system rolls back the first instruction group if its bit is set, and the second instruction group if its bit is set, before allowing the external agent's access. If neither bit is set, access is granted.
  4. Additionally, a subset of address bits of the cache line can be used to identify an entry in the memory unit, where an indicator bit of that entry is set when the cache line is accessed.

Litigation Status:
As of April 26, 2026, US Patent 8898395 is listed as "Active," with an adjusted expiration date of July 17, 2026. The patent family has been involved in litigation. Specifically:

• A PTAB case (IPR2025-00638) was filed and procedurally terminated.
• Two US district court cases were filed in the Texas Western District Court (case numbers 6:24-cv-00188 and 1:24-cv-00390).
• First worldwide family litigation has also been filed.
  No specific dockets for US patent 8898395 were found in the CAFC database for 2026 based on the current search.