Prior art

US Patent 8884373: Prior Art Analysis

US Patent 8884373, titled "Semiconductor device," was published on November 11, 2014, from an application filed on October 31, 2012, claiming priority from March 25, 2011. The patent introduces semiconductor devices with complementary metal-insulator-semiconductor (CMIS) dual-gate structures, particularly focusing on methods to mitigate issues related to variations in gate dimensions and impurity diffusion, especially in logic and SRAM areas.

The patent itself references the following Japanese patent publications as prior art:

1. Japanese Patent Publication No. H06-275788

   • Full Citation: Japanese Patent Publication No. H06-275788 A
   • Publication/Filing Date: Publication year is 1994 (Heisei 6). The precise month and day for this publication number were not readily available through general search.
   • Brief Description: This patent publication describes the general concept of a CMIS device with a dual-gate structure. It includes a polysilicon film doped with an n-type impurity for an n-channel metal-insulator-semiconductor field-effect transistor (NMISFET) gate electrode and a polysilicon film doped with a p-type impurity for a p-channel MISFET (PMISFET) gate electrode.
   • Potential Anticipated Claims (35 U.S.C. § 102): This reference broadly anticipates the fundamental structure of a CMIS device with dual-gate electrodes of different conductivity types, as generally described in the preamble portions of claims 1 and 16 of US8884373. For example, claim 1 begins by describing "a first dual-gate electrode... including a first gate electrode... having a first silicon film of a first conductivity type and a second gate electrode... having a first silicon film of a second conductivity type." However, this reference does not appear to teach the specific distinguishing features of US8884373, particularly the differential impurity concentrations between different dual-gate electrodes (e.g., logic vs. SRAM areas) or within parts of the same gate, which are central to the novelty of US8884373.

2. Japanese Patent Publication No. H08-17934

   • Full Citation: Japanese Patent Publication No. H08-17934 A
   • Publication/Filing Date: Publication year is 1996 (Heisei 8). The precise month and day for this publication number were not readily available through general search.
   • Brief Description: This prior art discloses a conventional method for forming n-type and p-type regions in polysilicon gate electrodes. The method involves implanting ions of impurities using a mask designed such that the boundary between the n-type and p-type regions is located on an isolation region between well regions. This technique aims to reduce the degradation of FET characteristics caused by mutual diffusion of impurities in the polysilicon gate electrode.
   • Potential Anticipated Claims (35 U.S.C. § 102): This reference directly anticipates the feature, recited in claims 1 and 16 of US8884373, that "the first active region and the second active region are isolated from each other with an isolation region interposed therebetween, the first gate electrode and the second gate electrode are connected to each other on the isolation region." While it teaches the placement of the PN boundary on an isolation region, it does not disclose the specific impurity concentration differences across different gate electrodes or regions that form the inventive step of US8884373.