Obviousness

Obviousness Analysis of US Patent 8,884,373 under 35 U.S.C. § 103

This analysis addresses the obviousness of US Patent 8,884,373, titled "Semiconductor device," by examining combinations of prior art references identified within the patent itself and assessing whether a person having ordinary skill in the art (PHOSITA) would have been motivated to combine them to arrive at the claimed invention. The relevant prior art cited in the patent includes Japanese Patent Publication No. H06-275788, Japanese Patent Publication No. H08-17934, and the conventional semiconductor device and fabrication method illustrated in FIGS. 15A-15D and FIGS. 16A-16B of US8884373, respectively.

1. Prior Art Teachings

• Japanese Patent Publication No. H06-275788: Describes a complementary metal insulator semiconductor (CMIS) device with a dual-gate structure. This device typically includes a polysilicon film doped with an n-type impurity for an n-channel metal insulator semiconductor field effect transistor (NMISFET) gate electrode and a p-type impurity for a p-channel metal insulator semiconductor field effect transistor (PMISFET) gate electrode. It also discusses the formation of a metal silicide layer on the polysilicon gate electrode to connect n-type and p-type polysilicon gate electrodes. Crucially, it highlights the problem of impurities diffusing from one region to another through the metal silicide layer or the polysilicon film, leading to changes in the work function of the gate electrode and variations in the threshold voltage of the FETs.
• Japanese Patent Publication No. H08-17934: Teaches a conventional method for forming n-type and p-type regions in a polysilicon film for gate electrodes. In this method, ions of impurities are implanted into the polysilicon film using a mask designed such that the boundary between the n-type and p-type regions is located on an isolation between well regions.
• FIGS. 15A-15D (Conventional Semiconductor Device): Illustrate a conventional semiconductor device featuring both logic and static random access memory (SRAM) areas. Each area includes NMIS and PMIS regions.
  • In the logic area, a dual-gate electrode (112L) is formed, comprising an n-type polysilicon film (104a) on an active region (100a) and a p-type polysilicon film (104b) on an active region (100b). These are connected at a PN boundary (113L) on an isolation region (101).
  • Similarly, in the SRAM area, a dual-gate electrode (112S) is formed with an n-type polysilicon film (104c) on an active region (100c) and a p-type polysilicon film (104d) on an active region (100d), connected at a PN boundary (113S) on an isolation region (101).
• FIGS. 16A-16B (Conventional Fabrication Method): Show the process of implanting p-type and n-type impurities into a polysilicon film (104) before gate patterning to form dual-gate electrodes.
  • For PMIS regions, p-type impurities are implanted using a mask (151) that covers the NMIS regions. This results in p-type polysilicon films (104b and 104d) in both logic and SRAM areas having "substantially the same concentration of the p-type impurity."
  • For NMIS regions, n-type impurities are implanted using a mask (152) that covers the PMIS regions. This results in n-type polysilicon films (104a and 104c) in both logic and SRAM areas having "substantially the same concentration of the n-type impurity."
  • The masks are designed to locate the PN boundaries on the isolation region (101) between active regions.

The '373 patent identifies problems with this conventional approach: the difference in etching speed between different dopants causes gate length variations, and despite placing PN boundaries on isolation regions, "a small width of the isolation region especially in a device such as an SRAM makes the influence of mutual diffusion of impurities... nonnegligible," leading to work function and threshold voltage variations.

2. Analysis of Independent Claims against Prior Art

Independent Claim 1:
Claim 1 describes a semiconductor device with a first dual-gate electrode (e.g., for a logic circuit) and a second dual-gate electrode (e.g., for an SRAM circuit). The key distinguishing feature is that "at least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region." Interpreting "first conductivity type" as p-type and "first silicon film" as logic gate material, and "second silicon film" as SRAM gate material, this means the logic PMIS gate has a higher p-type impurity concentration than the SRAM PMIS gate.

The combination of Japanese Patent Publication No. H06-275788 (CMIS dual-gate structure, impurity diffusion problem) with Japanese Patent Publication No. H08-17934 (PN boundary on isolation region) and the conventional structures and methods shown in FIGS. 15A-16B would yield a semiconductor device with both logic and SRAM dual-gate electrodes. However, FIGS. 16A-16B explicitly teach that in such a conventional device, the p-type polysilicon films for both logic (104b) and SRAM (104d) have "substantially the same concentration of the p-type impurity." This directly contradicts the distinguishing feature of Claim 1, which requires a higher concentration in the logic circuit's first conductivity type gate compared to the SRAM circuit's.

A PHOSITA, aware of the problems of impurity diffusion and threshold voltage variation in miniaturized devices, particularly SRAMs with narrow isolation regions, might be motivated to reduce these variations. However, the prior art offers no teaching or suggestion to specifically increase the impurity concentration in the logic PMIS gate while maintaining a lower concentration in the SRAM PMIS gate to solve this problem. In fact, the general teaching is towards uniform concentrations for gates of the same conductivity type across different circuit areas. Therefore, Claim 1 is not rendered obvious by the identified prior art.

Independent Claim 13:
Claim 13 outlines a method for fabricating the semiconductor device, including steps of (a) forming a silicon film, (b) introducing a first conductivity type impurity with a first mask pattern, (c) introducing a second conductivity type impurity with a second mask pattern, and (d) patterning the silicon film. While steps (a) and (d) are generally taught by FIGS. 16A-16B, which describe implanting impurities into a polysilicon film before gate patterning, the specific masking scheme in steps (b) and (c) for differential doping is key.

In Claim 13, the first mask covers portions over the second, third, and fourth active regions, exposing only the first active region for the first conductivity type. The second mask covers the first active region, exposing the second, third, and fourth active regions for the second conductivity type. This masking scheme, particularly when mapped to the embodiments (e.g., initial n-type doping of the SRAM PMIS region), allows for different impurity concentrations between the logic and SRAM gates.

The conventional method in FIGS. 16A-16B uses masks (151, 152) to dope all PMIS regions (logic and SRAM) with p-type impurity at substantially the same concentration, and all NMIS regions with n-type impurity at substantially the same concentration. The masking scheme of Claim 13 explicitly departs from this by enabling differential doping, which is not taught or suggested by the prior art aiming for uniform concentrations. The prior art's problem statement about diffusion in SRAMs does not motivate a PHOSITA to adopt this specific, non-uniform doping method. Thus, Claim 13 is not rendered obvious.

Independent Claim 14:
Claim 14 combines elements of Claim 1 with additional features: (1) the isolation width between the first and second active regions (logic) is larger than that between the third and fourth active regions (SRAM), and (2) at least a portion of the first silicon film of the second conductivity type (e.g., logic NMIS) has an impurity concentration substantially equal to that of a portion of the second silicon film of the second conductivity type (e.g., SRAM NMIS) located on the fourth active region.

The first additional feature, regarding the difference in isolation widths, is acknowledged as conventional in the patent's background, which notes the problem of "a small width of the isolation region especially in a device such as an SRAM." The second additional feature, concerning substantially equal n-type impurity concentrations, is directly taught by FIGS. 16A-16B, which state that n-type polysilicon films 104a (logic) and 104c (SRAM) have "substantially the same concentration of the n-type impurity."

However, Claim 14 still includes the distinguishing feature from Claim 1 regarding the higher concentration of the first conductivity type in the logic area compared to the SRAM area. As discussed for Claim 1, the prior art teaches against this specific differentiation. While some elements of Claim 14 are individually known in the prior art, their combination with the non-obvious differential doping for the first conductivity type remains non-obvious. There is no motivation to combine these known elements (differential isolation width, uniform n-type doping) with a specific, higher concentration of p-type doping in logic PMIS gates compared to SRAM PMIS gates.

Independent Claim 15:
Claim 15 further specifies the distinguishing feature of Claim 1, stating that "a portion of the first silicon film of the first conductivity type located on the first active region has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region." This merely refines the location of the differential impurity concentration to the active region itself. Since FIGS. 16A-16B teach "substantially the same concentration" for corresponding polysilicon films (104b and 104d), which would include the portions on the active regions (100b and 100d), the same reasoning for non-obviousness as in Claim 1 applies here. No prior art suggests this specific differential doping concentration on the active regions to solve the identified problems.

3. Motivation to Combine

A PHOSITA would undoubtedly be motivated to combine the general knowledge of CMIS dual-gate structures (H06-275788) with techniques for placing PN boundaries on isolation regions (H08-17934) and the conventional manufacturing processes illustrated in FIGS. 15A-16B. This combination, however, would only result in the conventional device and method that US8884373 explicitly identifies as suffering from unresolved problems, particularly mutual diffusion in narrow SRAM isolation regions and etching variations leading to threshold voltage variability.

The crux of the non-obviousness lies in the departure from uniform doping concentrations for the gates of the same conductivity type across different circuit areas (logic vs. SRAM). The prior art explicitly teaches that p-type polysilicon films in logic and SRAM areas (104b and 104d) have "substantially the same concentration." The invention's solution—specifically, making the first conductivity type (e.g., p-type) impurity concentration higher in the logic circuit's gate than in the SRAM circuit's gate—is directly contrary to this teaching. The identified problems in the prior art do not suggest this specific non-uniform doping scheme as a solution. There is no motivation in the prior art to differentiate the gate doping concentrations in this particular manner to mitigate the effects of etching speed differences or impurity diffusion.

Therefore, the specific combination of features defining the impurity concentration profiles in the claimed semiconductor device and the method to achieve them would not have been obvious to a PHOSITA at the time of the invention.