Derivative works

Defensive Disclosure: Variations on US Patent 8,884,373

Date: April 26, 2026

Patent Under Analysis: US Patent 8,884,373 - "Semiconductor device"

Objective: To expand the known prior art landscape surrounding the core inventive concepts of US Patent 8,884,373, rendering future incremental advancements by competitors obvious or non-novel. This document details several derivative variations based on key inventive principles from the patent's claims, specifically focusing on differential gate impurity concentrations and associated fabrication methods.

Core Inventive Principles from US Patent 8,884,373

The foundational innovation in US 8,884,373 involves a semiconductor device architecture and fabrication method that addresses challenges in miniaturized complementary metal-insulator-semiconductor (CMIS) devices, particularly the variation in threshold voltage due to gate length variations and impurity diffusion. This is achieved by:

1. Differentiated P-type Gate Doping: A portion of the first silicon film of the first conductivity type (e.g., p-type for PMISFETs) in a first dual-gate electrode (e.g., for logic circuits) has a higher impurity concentration than a corresponding portion of the second silicon film of the first conductivity type in a second dual-gate electrode (e.g., for SRAM circuits). This is a central feature of independent claims 1, 14, and 15.
2. Specific N-type Gate Doping: The impurity concentration of the second conductivity type (e.g., n-type for NMISFETs) may be "substantially equal" between the logic and SRAM dual-gate electrodes (as noted in claim 14).
3. Variable Isolation Width: The isolation region width between active regions for logic circuits is typically larger than that for SRAM circuits (as noted in claim 14), a conventional aspect further highlighted by the patent.
4. Fabrication Method for Differential Doping: A method utilizing distinct mask patterns during impurity introduction (ion implantation) into a silicon film before gate patterning, to selectively dope regions to achieve the desired differential concentrations. This is described in independent claim 13.

The following derivatives expand upon these principles, applying a structured framework to explore material substitutions, operational parameter expansions, cross-domain applications, integration with emerging technologies, and inverse/failure modes.

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Derivatives of Core Inventive Principles

The following derivatives focus on the core concept of differential gate impurity concentrations between different circuit blocks (e.g., logic vs. SRAM) and the methods for achieving them.

Derivative 1: Material & Component Substitution - High-K/Metal Gates with Work Function Engineering

• Enabling Description: Instead of solely relying on polysilicon doping, the gate electrodes in both logic and SRAM areas are fabricated using a high-k dielectric material (e.g., hafnium dioxide (HfO2), zirconium dioxide (ZrO2), or aluminum oxide (Al2O3)) as the gate insulator, combined with a metal gate stack. For the first conductivity type (p-channel), the logic circuit PMISFET gate employs a metal or metal alloy with a higher effective work function (e.g., platinum (Pt), iridium (Ir), ruthenium (Ru), or heavily nitrogen-implanted titanium nitride (TiN)) on the high-k dielectric, forming the equivalent of the higher p-type concentration. In contrast, the SRAM PMISFET gate utilizes a metal or metal alloy with a moderately lower effective work function (e.g., molybdenum (Mo), tantalum nitride (TaN), or a different stoichiometry of TiN) to represent the lower p-type concentration. The differential work function is achieved by varying the thickness of specific metal layers (e.g., a work function tuning layer of TiAlN or TiSiN) within a metal-inserted polysilicon stack (MIPS) structure, or by controlling the nitrogen content during TiN deposition, or by depositing entirely different metal gate electrode materials. This approach allows independent threshold voltage tuning for logic and SRAM PMISFETs, leveraging the physical properties of advanced gate materials rather than just polysilicon dopant activation.

classDiagram
    class SemiconductorDevice {
        +Substrate
        +IsolationRegion
        +ActiveRegion
    }
    class GateElectrode {
        +GateInsulatingFilm
        +GateMaterial
        +ConductivityType
        +ImpurityConcentration
    }
    class LogicGate(GateElectrode) {
        +HighKDielectric: HfO2
        +HighWorkFunctionMetal: Pt, Ir, Ru, heavily-N-doped TiN
        +P_Type_Analog_Higher_Conc
    }
    class SRAMGate(GateElectrode) {
        +HighKDielectric: HfO2
        +MediumWorkFunctionMetal: Mo, TaN, TiN_stoichiometry
        +P_Type_Analog_Lower_Conc
    }
    SemiconductorDevice "1" -- "2" GateElectrode : contains
    LogicGate --|> GateElectrode
    SRAMGate --|> GateElectrode

Derivative 2: Operational Parameter Expansion - Cryogenic Operation with Differentiated Gate Doping and Enhanced Carrier Mobility

• Enabling Description: The semiconductor device, incorporating the differentiated p-type gate doping scheme as described in US 8,884,373, is specifically engineered for stable and high-performance operation at cryogenic temperatures (e.g., 4 Kelvin to 77 Kelvin). At these extreme low temperatures, conventional dopant concentrations can lead to carrier freeze-out. To counteract this, the higher p-type impurity concentration in the logic PMIS gate (e.g., achieved with a boron implant at 5 keV, 8E15 cm⁻² dose, followed by a millisecond laser anneal) is optimized to ensure sufficient active carriers and maintain high drive current and low threshold voltage for logic operations. Concurrently, the lower p-type concentration in the SRAM PMIS gate (e.g., boron implant at 5 keV, 2E15 cm⁻² dose) is precisely controlled to minimize subthreshold leakage current, which becomes a dominant factor at cryogenic temperatures due to reduced thermal energy. The entire device is fabricated on a silicon-on-insulator (SOI) substrate to reduce parasitic capacitance and self-heating effects, further enhancing performance at cryogenic conditions.

stateDiagram
    [*] --> Off
    Off --> Cooling: Initiate
    Cooling --> CryogenicReady: T < 77K
    CryogenicReady --> LowPowerCryo: SRAM active
    CryogenicReady --> HighPerformanceCryo: Logic active
    LowPowerCryo --> HighPerformanceCryo: Logic workload
    HighPerformanceCryo --> LowPowerCryo: Standby
    LowPowerCryo --> Thawing: Shut down
    HighPerformanceCryo --> Thawing: Shut down
    Thawing --> Off: Return to ambient

Derivative 3: Cross-Domain Application - Automotive Radar Module with Integrated Processing Units

• Enabling Description: The semiconductor device, featuring the logic/SRAM differential gate doping as per US 8,884,373, is applied in a next-generation automotive radar system-on-chip (SoC). The logic area, which handles real-time radar signal processing (e.g., FFT, beamforming, object detection algorithms) and vehicle control unit (VCU) functions, requires maximum speed and is implemented with PMISFETs utilizing the higher p-type gate impurity concentration (e.g., using boron-doped polysilicon with a concentration of 5x10^20 atoms/cm^3). The integrated SRAM area, used for temporary storage of radar echoes, environmental maps, and lookup tables for autonomous driving, prioritizes low static power consumption and high density. Its PMISFETs are implemented with the lower p-type gate impurity concentration (e.g., 8x10^19 atoms/cm^3), reducing leakage currents. This precise tailoring of gate characteristics within a single SoC optimizes the trade-off between speed and power for critical automotive safety and performance functions.

componentDiagram
    [Radar SoC] --> [RF Transceiver]
    [Radar SoC] --> [ADC/DAC]
    [Radar SoC] --> [Logic Processing Unit (LPU)]
    [Radar SoC] --> [SRAM Memory Block (SMB)]
    [LPU] ..> [High-Conc P-Gate PMISFETs]
    [SMB] ..> [Low-Conc P-Gate PMISFETs]
    [RF Transceiver] -- Data --> [ADC/DAC]
    [ADC/DAC] -- Digital Signal --> [LPU]
    [LPU] -- Data Storage --> [SMB]
    [SMB] -- Read Data --> [LPU]
    [LPU] -- Control --> [Vehicle Control Unit]

Derivative 4: Integration with Emerging Tech - AI-Driven Real-Time Doping Profile Optimization with Blockchain Traceability

• Enabling Description: The fabrication method (Claim 13) is enhanced through integration with an AI-driven real-time optimization system and blockchain for immutable process data logging. During step (b) (introducing first conductivity type impurity) and step (c) (introducing second conductivity type impurity), in-situ process monitoring using advanced sensors (e.g., secondary ion mass spectrometry (SIMS) for real-time dopant profiling or optical emission spectroscopy for plasma composition) provides live data to a deep reinforcement learning (DRL) algorithm. This AI analyzes the observed impurity profiles against target specifications for logic (higher p-type concentration, e.g., 4E15 cm⁻² boron implant) and SRAM (lower p-type concentration, e.g., 1E15 cm⁻² boron implant), factoring in current fab conditions and yield data. The DRL system dynamically adjusts ion implanter parameters (e.g., beam current, scan speed, energy) or plasma doping parameters to correct deviations and maintain optimal differential concentrations. Each adjustment, sensor reading, and process state is securely recorded onto a distributed ledger (blockchain) for complete, auditable traceability from wafer to final product, enhancing quality control and supply chain integrity.

sequenceDiagram
    participant AI as AI/DRL Optimizer
    participant Sensors as In-situ Sensors (SIMS, OES)
    participant Implanter as Ion Implanter / Plasma Doper
    participant Blockchain as Blockchain Ledger

    loop Fabrication Cycle
        Implanter->>Sensors: Apply Doping (Logic/SRAM)
        Sensors->>AI: Real-time Data (Conc. Profile)
        AI->>AI: Analyze vs. Target & Yield Models
        alt Deviation Detected
            AI->>Implanter: Adjust Parameters (Beam Current, Dose)
            Implanter->>Blockchain: Log Adjustment
        else Within Tolerance
            AI->>Blockchain: Log Process State
        end
        Implanter->>Blockchain: Log Final Doping Step
    end

Derivative 5: The "Inverse" or Failure Mode - Low-Power/Limited-Functionality Mode with Deliberate Gate Depletion

• Enabling Description: A semiconductor device incorporating the gate structures of US 8,884,373 is designed with a specific "limited-functionality" or "safe-failure" mode. In this mode, logic PMISFETs that typically have a higher p-type gate impurity concentration (e.g., boron-doped polysilicon) are subjected to a deliberate, controlled reduction in their effective channel doping or an increase in their gate work function during fabrication for specific non-critical logic blocks. This can be achieved by a localized, slightly lighter p-type implant dose (e.g., 2E15 cm⁻² instead of 4E15 cm⁻²) or by applying an additional, very shallow n-type blanket implant post-p-type doping, which partially compensates the p-type gate. This raises the threshold voltage (Vt) of these specific logic PMISFETs, significantly reducing their drive current and static leakage. While their performance is degraded, they consume substantially less power and are more resistant to soft errors, making them suitable for essential supervisory or fail-safe logic functions in a power-constrained or degraded operating environment. Normal high-performance logic PMISFETs retain their higher p-type doping.

stateDiagram
    [*] --> Full_Power_Mode
    Full_Power_Mode --> Low_Power_Standby: Idle / Battery Save
    Low_Power_Standby --> Limited_Functionality_Mode: Critical Event / Low Battery
    Limited_Functionality_Mode --> Full_Power_Mode: Conditions Restore
    Full_Power_Mode --> Safety_Shutdown: Critical Failure
    Limited_Functionality_Mode --> Safety_Shutdown: Imminent Failure

    state Full_Power_Mode {
        High_P_Conc_Logic --> Normal_Operation
        Low_P_Conc_SRAM --> Normal_Operation
    }

    state Limited_Functionality_Mode {
        Reduced_P_Conc_Logic --> Essential_Functions_Only
        Low_P_Conc_SRAM --> Normal_Operation
    }

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Combination Prior Art Scenarios

Here are three scenarios where the teachings of US Patent 8,884,373 are combined with existing open-source standards to create additional prior art.

1. Combination with Open-Source Process Design Kits (PDKs):

   • Scenario: An open-source Process Design Kit (PDK), such as those developed by university consortia or commercial foundries for community use (e.g., SkyWater Technology's 130nm or Google's 180nm open-source PDKs), is augmented to include design rules and process layer definitions for the differential gate doping described in US 8,884,373.
   • Disclosure: The PDK's technology files (.tf) would define new mask layers for "P-type Gate Implant - Logic" and "P-type Gate Implant - SRAM," each associated with specific ion implantation parameters (e.g., dose, energy, tilt angle) and anneal conditions (e.g., RTA temperature and time, or millisecond laser anneal recipes) that yield the higher impurity concentration for logic and lower for SRAM PMISFETs, as disclosed in US 8,884,373. The PDK would also include device models (e.g., SPICE models) reflecting the distinct threshold voltages and performance characteristics of these differentially doped gates, enabling designers to precisely model and leverage the patent's teachings in open-source EDA tools.

   graph TD
       A[US8884373 - Differential Gate Doping] --> B{Open-Source PDK Standard};
       B -- Specifies Layer Definitions (e.g., `IMPLANT_P_LOGIC_HIGH`, `IMPLANT_P_SRAM_LOW`) --> C[PDK Tech Files (.tf)];
       C -- Includes Device Models --> D[SPICE Models for Differentiated Gates];
       D --> E[Open-Source Chip Design Flow];
       E -- Enables Design of --> F[Optimized Logic/SRAM Circuits];
   

2. Combination with Open-Source Electronic Design Automation (EDA) Layout Tools:

   • Scenario: The fabrication method of US 8,884,373 (Claim 13), detailing the use of specific mask patterns for differential impurity introduction, is integrated into an open-source EDA layout tool, such as KLayout or Magic.
   • Disclosure: Custom Python scripts (for KLayout) or Tcl/Tk scripts (for Magic) are developed and released under an open-source license. These scripts allow a layout designer to designate specific polysilicon gate regions as "Logic PMIS Gate" or "SRAM PMIS Gate." Upon execution, the script automatically generates the necessary FIRST_MASK_PATTERN and SECOND_MASK_PATTERN (as defined in Claim 13) layers, ensuring the correct spatial differentiation for impurity implantation. The script would also verify that the generated mask patterns comply with manufacturing design rules, especially concerning the PN boundary placement on isolation regions. This provides a software implementation of the patent's masking methodology, making it accessible for open-source chip development.

   graph TD
       A[US8884373 - Fabrication Method (Claim 13)] --> B{Open-Source EDA Tool (KLayout/Magic)};
       B -- Integrates Custom Scripts (Python/Tcl) --> C[Automated Mask Pattern Generation];
       C -- Defines `FIRST_MASK_PATTERN` & `SECOND_MASK_PATTERN` --> D[Layout Design Files (.gds)];
       D -- Guides --> E[Manufacturing Process for Patent-Claimed Devices];
   

3. Combination with Open-Source High-Level Synthesis (HLS) Frameworks:

   • Scenario: An open-source High-Level Synthesis (HLS) framework (e.g., tools based on LLVM or those used in academic research for hardware compilation) is extended to support architectural synthesis leveraging the device characteristics disclosed in US 8,884,373.
   • Disclosure: The HLS framework is equipped with a technology library that includes parameterized device models derived from US 8,884,373, representing PMISFETs with higher p-type gate concentrations (for logic) and lower p-type gate concentrations (for SRAM). When a designer specifies architectural blocks as "high-performance/high-power" (e.g., a critical path in a CPU) or "low-power/high-density" (e.g., on-chip cache memory), the HLS tool automatically maps these specifications to the corresponding gate types. This means the HLS tool's output (e.g., RTL code or gate-level netlist) will implicitly demand the fabrication process outlined in US 8,884,373 for optimal implementation, guiding subsequent logic synthesis and physical design stages to utilize the differentiated gates effectively.

   graph TD
       A[US8884373 - Differentiated Logic/SRAM Devices] --> B{Open-Source HLS Framework};
       B -- Integrates Tech Library with Device Models --> C[High-Level Design Specification];
       C -- Automates Mapping of Performance/Power Goals --> D[Synthesized Netlist with Optimized Gate Types];
       D -- Facilitates --> E[Fabrication of High-Performance/Low-Power SoCs];