US 8686562

Here is a concise summary of US patent 8686562:

Title: Refractory metal nitride capped electrical contact and method for fabricating same

Assignee: Infineon Technologies North America Corp (Current Assignee), originally International Rectifier Corp USA

Inventors: Sadiki Jordan

Filing Date: 2009-08-25

Issue Date: 2014-04-01

Abstract: According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device.

Independent Claims Overview:

• Claim 1 (Electrical Contact): This claim describes an electrical contact for a semiconductor device. The contact has an electrode stack with several metal layers and a capping layer on top of these metal layers. This capping layer consists only of a refractory metal nitride, which forms the very top of the electrical contact. Importantly, this refractory metal nitride capping layer must be thicker than the bottommost metal layer in the stack.
• Claim 13 (Electrical Contact for Group III-V Semiconductor): This claim is similar to Claim 1 but specifically for use on a Group III-V semiconductor device. The electrical contact includes an electrode stack with multiple metal layers and a capping layer formed over them. The capping layer consists only of a metal chosen from titanium nitride (TiN) and tantalum nitride (TaN). This selected metal forms the top of the electrical contact and has a thickness greater than that of the bottommost layer of the plurality of metal layers.

CAFC 2026 Dockets:
Based on the provided patent text, there is no explicit mention of cases filed in the CAFC in 2026. However, the patent family does have litigation, including an IPR (IPR2025-00175) filed on 2025-02-04, a US case filed in the International Trade Commission (337-TA-1414), and a US case filed in the California Northern District Court (4:24-cv-01553). These are ongoing, but no specific CAFC 2026 dockets are identified in the provided information. I do not have authoritative information on specific CAFC 2026 dockets for US8686562 at this time.The patent text provided already contains all the requested information about US8686562, except for specific CAFC 2026 dockets.

Here is a concise summary of US patent 8686562:

Title: Refractory metal nitride capped electrical contact and method for fabricating same

Assignee: Infineon Technologies North America Corp (Current Assignee), originally International Rectifier Corp USA

Inventors: Sadiki Jordan

Filing Date: 2009-08-25

Issue Date: 2014-04-01

Abstract: According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device.

Independent Claims Overview:

• Claim 1 (Electrical Contact): This claim describes an electrical contact for a semiconductor device. The contact has an electrode stack that includes multiple metal layers and a capping layer positioned over these metal layers. This capping layer consists only of a refractory metal nitride, and this refractory metal nitride forms the top surface of the electrical contact. Furthermore, the thickness of this capping layer must be greater than the thickness of the bottommost layer among the plurality of metal layers.
• Claim 13 (Electrical Contact for Group III-V Semiconductor): This claim defines an electrical contact specifically designed for use on a group III-V semiconductor device. The contact comprises an electrode stack with a plurality of metal layers and a capping layer formed over them. The capping layer consists only of a metal chosen from titanium nitride (TiN) and tantalum nitride (TaN). This selected metal forms the top of the electrical contact and has a thickness greater than that of the bottommost layer of the plurality of metal layers.

CAFC 2026 Dockets:
Based on the provided patent text and my search, there is no explicit mention of cases filed in the U.S. Court of Appeals for the Federal Circuit (CAFC) specifically in 2026 for US patent 8686562. The provided patent text does indicate that the patent family has litigation, including an Inter Partes Review (IPR2025-00175) filed in 2025, a US case filed in the International Trade Commission (337-TA-1414), and a US case filed in the California Northern District Court (4:24-cv-01553). While these are ongoing legal actions, they are not identified as CAFC dockets for 2026. My search for "CAFC 2026 dockets US8686562" did not yield any specific CAFC dockets for this patent for the year 2026. Therefore, I do not have authoritative information on specific CAFC 2026 dockets for US8686562 at this time.

Here is a list of known litigation involving US Patent 8,686,562:

1. Inter Partes Review (IPR) before the Patent Trial and Appeal Board (PTAB)

• Case Number: IPR2025-00175
• Plaintiff(s): Unified Patents
• Defendant(s): Innoscience America, Inc., Innoscience (Zhuhai) Technology Company, Ltd., and Innoscience (Suzhou) Technology Holding Company, Ltd. (Opponents to Unified Patents, but the patent owner is Infineon Technologies North America Corp.)
• Jurisdiction: Patent Trial and Appeal Board (PTAB)
• Filing Date: November 18, 2024 (effective date)
• Current Status: Pending - Instituted

2. U.S. International Trade Commission (ITC) Investigation

• Case Number: 337-TA-1414
• Plaintiff(s): Infineon Technologies Americas Corp. and Infineon Technologies Austria AG
• Defendant(s): Innoscience (Suzhou) Technology Company, Ltd., Innoscience (Suzhou) Semiconductor Co., Ltd., Innoscience (Zhuhai) Technology Company, Ltd., and Innoscience America, Inc.
• Jurisdiction: U.S. International Trade Commission (USITC)
• Filing Date: July 26, 2024 (complaint filed), investigation instituted on August 30, 2024
• Outcome/Current Status: The Commission determined not to review an initial determination granting Complainants' unopposed motion to terminate the investigation as to all asserted claims of the '562 patent on May 20, 2025. This means that US Patent 8,686,562 is no longer part of this specific ITC investigation. The overall investigation continued for other patents.

3. U.S. District Court for the Northern District of California

• Case Number: 4:24-cv-01553-YGR
• Plaintiff(s): Infineon Technologies Austria AG and Infineon Technologies Americas Corp.
• Defendant(s): Innoscience (Suzhou) Technology Company, Ltd., Innoscience (Zhuhai) Technology Company, Ltd., and Innoscience America, Inc.
• Jurisdiction: California Northern District Court
• Filing Date: March 13, 2024
• Outcome/Current Status: The case was stayed and administratively closed for statistical purposes on August 30, 2024, pending the resolution of the parallel ITC investigation (337-TA-1414), which involved the same patents. The court did not reach a merits determination, and no damages or injunctive relief were issued at this stage.

Proceedings overview

There is 1 AIA trial proceeding on file for US Patent 8,686,562, which is currently in "Final Written Decision" status. This gives a defendant some defensive posture as the claims challenged in this IPR may have been invalidated.

IPR2025-00175 — Innoscience America, Inc. et al. v. Infineon Technologies Americas Corp.

• Type: Inter Partes Review
• Filed: 2024-11-18
• Status: Final Written Decision
• Judge panel: Not publicly available in the provided text.
• Petition grounds: Not publicly available in the provided text.
• Institution decision: The institution decision for IPR2025-00175 is not explicitly detailed in the provided text. However, a source mentions that the projected final written decision on August 12, 2026, was well in advance of a district court trial date scheduled for March 22, 2027, and that there appeared to be little investment in the district court proceeding, suggesting factors that generally favor institution under the Fintiv factors. It also notes that the standard Fintiv factors were against a discretionary denial, further implying institution.
• Final Written Decision (if issued): The provided information states the proceeding is in "Final Written Decision" status, but the details of the verdict at a claim-level granularity are not available.
• Settlement / termination: The provided text indicates that the IPR is in "Final Written Decision" status, not settled or terminated prior to a decision.
• Appeal: No information regarding an appeal to the Federal Circuit is available in the provided text.
• Defensive value: The impact on defensive value cannot be fully assessed without the specific outcomes of the Final Written Decision, i.e., which claims were canceled or sustained.

Strategic summary

Currently, there is one IPR proceeding (IPR2025-00175) that has reached the "Final Written Decision" stage. Without the details of the Final Written Decision, it is not possible to definitively state which claims of US8686562 are canceled, sustained, or remain untested. The petitioner in this case is Innoscience America, Inc. et al., and the patent owner is Infineon Technologies Americas Corp. This IPR is part of a broader litigation landscape involving these parties, including a case in the California Northern District Court (4:24-cv-01553) which was stayed pending the resolution of a parallel ITC investigation (337-TA-1414). The ITC investigation regarding US Patent 8,686,562 was terminated as to this patent in May 2025, meaning it is no longer being considered there.

The estoppel landscape will depend on the outcome of the Final Written Decision in IPR2025-00175. If claims are invalidated, the petitioner (Innoscience America, Inc. et al.) and their privies would be estopped under 35 U.S.C. § 315(e)(2) from asserting any ground they raised or reasonably could have raised during the IPR. Given that Innoscience is also a defendant in district court litigation concerning this patent, any invalidated claims could significantly narrow the scope of the patent for assertion against them.

The involvement of Innoscience America, Inc. as the petitioner in the IPR, and as a defendant in parallel district court litigation, suggests a coordinated defensive strategy. The initial institution analysis in IPR2025-00175 appears to have considered Fintiv factors, with a projected final written decision date well before a district court trial, which generally favors institution. This indicates that the PTAB likely proceeded to a merits review, aiming for an efficient resolution prior to any potential district court trial.

Recommended next steps

Since IPR2025-00175 has reached the "Final Written Decision" status, the critical next step is to obtain and review the full Final Written Decision from the USPTO PTAB Decisions database. This document will explicitly detail the patentability of each challenged claim (canceled, sustained, or otherwise).

• Review the Final Written Decision for IPR2025-00175: Locate the Final Written Decision for IPR2025-00175 on the USPTO PTAB Decisions portal. This decision will be crucial to understand the exact scope of surviving claims. Pay close attention to the disposition for each independent and dependent claim that was challenged.
• Identify Canceled Claims: If any claims of US8686562 were canceled in the Final Written Decision, explicitly note their numbers and the reasoning provided by the PTAB panel. This will immediately inform any infringement theories or demand letters built upon those claims, as they would be rendered invalid.
• Assess Surviving Claims: For any claims that were upheld as patentable, analyze the PTAB's reasoning. This information can help to harden defenses against future assertions of these claims.
• Check for Federal Circuit Appeal: While not explicitly mentioned in the provided text, it is important to check if the Final Written Decision for IPR2025-00175 has been appealed to the Federal Circuit. This can be done by searching the Federal Circuit's docket or CourtListener for "IPR2025-00175" or "US8686562".

Inventors

• Sadiki Jordan (International Rectifier Corp USA at the time of filing)

Original assignee

The original assignee, International Rectifier Corp USA, was a manufacturer of power management semiconductors. They produced products embodying the claims of the patent. International Rectifier Corp USA was acquired by Infineon Technologies in 2015.

Assignment timeline

• 2010-01-21 (executed) / recorded 2010-01-21 — Reel 023829/0191

  • Conveyance: Assignment
  • Assignor: Sadiki Jordan
  • Assignee: International Rectifier Corporation
  • Correspondent: N/A
  • Context: Inventor assignment to the original assignee

• 2015-10-01 (executed) / recorded 2018-07-23 — Reel 046612/0968

  • Conveyance: Change of Name
  • Assignor: International Rectifier Corporation
  • Assignee: Infineon Technologies Americas Corp.
  • Correspondent: N/A
  • Context: Name change reflecting the acquisition of International Rectifier by Infineon Technologies.

Timeline diagram

timeline
    title Ownership of US 8686562
    2009 : Filed by International Rectifier
    2010 : Assigned to International Rectifier
    2014 : Issued
    2015 : Intl Rectifier acquired by Infineon
    2018 : Name change to Infineon Tech Americas Corp
    2024 : District court case filed
         : ITC case filed
    2025 : IPR filed

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The assignees are known operating companies (International Rectifier and Infineon Technologies Americas Corp.).
2. Known asserter in the chain — not present. None of the recorded assignees (International Rectifier, Infineon Technologies Americas Corp.) are on public NPE lists.
3. Repeat correspondent across the chain — unclear. Correspondent information was not available for the 2010-01-21 and 2018-07-23 assignments in the provided text.
4. Cascading transfers — not present. There are only two recorded assignments, spread across several years.
5. Pre-litigation transfer — not present. The last assignment (change of name) was recorded in 2018, significantly before the district court case filing in March 2024 and the ITC case filing in July 2024.
6. Bankruptcy fire-sale — not present. The transfer to Infineon was an acquisition, not a bankruptcy sale.
7. Privateering — unclear. While Infineon Technologies Americas Corp. is a known operating company and is asserting the patent in litigation, the context of whether this constitutes privateering (e.g., asserting on behalf of another entity) is not provided in the given information.
8. Defensive aggregator (anti-NPE) — not present. The patent is currently owned by Infineon Technologies Americas Corp., an operating company.

Verdict

Operating-company assertion. The patent has been consistently held by operating companies (International Rectifier Corporation and subsequently Infineon Technologies Americas Corp.) that produce semiconductor devices. The current assignee, Infineon Technologies Americas Corp., is actively asserting the patent in district court (4:24-cv-01553) and previously in an ITC investigation (337-TA-1414) against alleged competitors, Innoscience entities.

(Verification: https://assignmentcenter.uspto.gov/)

I will now identify the most relevant prior art for US patent 8686562 based on the provided patent text and a USPTO search.

Most Relevant Prior Art for US Patent 8,686,562

The Google Patents page for US8686562B2 lists "Patent Citations (11)". I will go through the four explicitly listed US patent citations from that section to provide the requested details.

1. US5902129A

• Full Citation: US5902129A, "Process for forming improved cobalt silicide layer on integrated circuit structure using two capping layers"
• Publication/Filing Date: Publication date: 1999-05-11; Priority date: 1997-04-07
• Brief Description: This patent describes a process for forming an improved cobalt silicide layer on an integrated circuit structure using two capping layers. This involves depositing a cobalt layer, a first titanium nitride capping layer, and a second capping layer (e.g., TEOS oxide) over the cobalt. The structure is then annealed to form cobalt silicide, and the capping layers are removed. The first titanium nitride layer acts as a nitrogen diffusion barrier during the silicidation anneal.
• Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates aspects of Claims 1 and 13 of US8686562 related to the use of a refractory metal nitride (specifically TiN) as a capping layer in an electrical contact structure. While US5902129A focuses on silicide formation and different underlying layers, the fundamental concept of using TiN as a capping layer in a semiconductor device fabrication process could be considered. However, US5902129A does not specify the refractory metal nitride forming the top of the electrical contact, nor does it necessarily teach the specific thickness requirements relative to a bottommost layer as claimed in US8686562.

2. US20060027840A1

• Full Citation: US20060027840A1, "Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same"
• Publication/Filing Date: Publication date: 2006-02-09; Priority date: 2003-11-24
• Brief Description: This patent application describes monolithic integrated enhancement mode and depletion mode field-effect transistors (FETs) and methods for making them. The abstract indicates a focus on structures that include both types of FETs, often utilizing different gate stack designs for each.
• Potential Anticipation (35 U.S.C. § 102): This reference appears more focused on the integration of different FET types and their respective gate structures, rather than the specific material composition and arrangement of a refractory metal nitride capped electrical contact as claimed in US8686562. It may generally relate to semiconductor device fabrication and electrical contacts within that context, but it doesn't immediately suggest anticipation of the specific capping layer structure and material defined in Claims 1 and 13 of US8686562. Without a more detailed review of its content, it's difficult to pinpoint direct anticipation of the specific claims of US8686562 related to the refractory metal nitride capping.

3. US20090309228A1

• Full Citation: US20090309228A1, "Method for forming self-aligned metal silicide contacts"
• Publication/Filing Date: Publication date: 2009-12-17; Priority date: 2006-05-01
• Brief Description: This patent application describes methods for forming self-aligned metal silicide contacts. The processes involve depositing a layer of refractory metal or alloy over exposed semiconductor regions, followed by a reaction to form self-aligned silicide. The abstract also mentions using an intermetallic layer as a silicide-forming material and subsequent selective etching.
• Potential Anticipation (35 U.S.C. § 102): Similar to US5902129A, this reference is focused on the formation of self-aligned metal silicide contacts. While it involves refractory metals, the core inventive concept of US8686562 revolves around a refractory metal nitride capping layer specifically and its characteristics. This reference might touch upon general refractory metal usage in contacts, but it does not appear to directly disclose an electrode stack with a capping layer consisting only of a refractory metal nitride forming the top of the contact, with the specific thickness requirement as outlined in Claims 1 and 13 of US8686562.

4. US20100258912A1

• Full Citation: US20100258912A1, "DOPANT DIFFUSION MODULATION IN GaN BUFFER LAYERS"
• Publication/Filing Date: Publication date: 2010-10-14; Priority date: 2009-04-08
• Brief Description: This patent application describes methods for modulating dopant diffusion in GaN buffer layers. It focuses on controlling dopant distribution within GaN-based semiconductor structures, particularly for devices like HEMTs.
• Potential Anticipation (35 U.S.C. § 102): This reference appears to be primarily concerned with the doping profiles and buffer layers within GaN semiconductor devices. It is less directly related to the specific structure and materials of electrical contacts themselves, particularly the refractory metal nitride capping layer as defined in US8686562. Therefore, it is unlikely to directly anticipate Claims 1 or 13 of US8686562.

The analysis above focuses on the explicit US patent citations provided. For a comprehensive prior art analysis, one would typically examine all cited references (including foreign patents and non-patent literature) and perform broader searches for similar technologies. The prompt specifically asked for citations for 8686562, and the Google Patents result clearly lists these under "Patent Citations".

The search results provide more details on the cited prior art.

1. US6844258B1 (Novellus Systems, Inc.) - "Selective refractory metal and nitride capping"

• This patent is explicitly cited within the US8666562 patent family as relevant to "Selective refractory metal and nitride capping".
• The snippets from the search results (specifically related to US6844258B1) do not directly provide its detailed description in a way that fully addresses its content in relation to the claims of US8686562. However, the title itself is highly suggestive. The phrase "refractory metal and nitride capping" indicates that this patent likely deals with capping layers made of refractory metals and nitrides. Without the full text, it's difficult to ascertain if it describes a refractory metal nitride as the topmost layer of an electrical contact stack for III-V semiconductor devices specifically to prevent contamination of silicon fabrication processes, and the thickness requirement.
• However, other related patents (e.g., US20160190008A1 and US12002679B2, which also cite US6844258B1) discuss tungsten deposition, tungsten-containing materials, titanium nitride (TiN) as under-layers, and fill materials for features like vias and contacts in semiconductor fabrication. US20160190008A1 mentions that examples of under-layers for tungsten include titanium (Ti), titanium nitride (TiN), and tungsten nitride (WN). This confirms that refractory metal nitrides like TiN and WN were known as layers in contact structures.

2. US5514908A (Sgs-Thomson Microelectronics, Inc.) - "Integrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundaries"

• This patent describes a "titanium nitride contact barrier". While it uses TiN, it's primarily as a barrier layer, often placed underneath the primary metal interconnect to prevent diffusion. The '562 patent specifies the refractory metal nitride as a capping layer forming the top of the electrical contact. The roles are distinct: a barrier layer generally mediates interaction between layers or between a contact and a semiconductor, while a capping layer is typically the outermost layer, often for protection from the environment or subsequent processing steps.

3. US7719030B2 (International Rectifier Corporation) - "Aluminum alloys for low resistance, ohmic contacts to III-nitride or compound semiconductor"

• This patent, from the original assignee of '562, directly addresses "Aluminum alloys for low resistance, ohmic contacts to III-nitride or compound semiconductor". This reference clearly teaches the formation of ohmic contacts to III-nitride (a type of Group III-V) semiconductors using aluminum alloys as part of an electrode stack, which are key components of claims 1 and 13. This fulfills the "plurality of metal layers" (at least including Al) on a "group III-V semiconductor device" (III-nitride). It would represent the "conventional approach" of forming electrode stacks on III-nitride devices prior to the '562 invention.

Obviousness Analysis under 35 U.S.C. § 103

A claim is obvious if "the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art." This requires identifying:

1. The scope and content of the prior art.
2. The differences between the prior art and the claims.
3. The level of ordinary skill in the pertinent art.
4. Secondary considerations (e.g., commercial success, long-felt but unsolved needs, failure of others).

Level of Ordinary Skill in the Art (POSITA): A POSITA in this field would likely have a master's degree in electrical engineering, materials science, or a related field, with several years of experience in semiconductor device fabrication, particularly with compound semiconductors and metallization processes. They would be familiar with different deposition techniques (sputtering, CVD, e-beam), contact formation on III-V devices, and common issues like material diffusion and contamination.

Problem Addressed by US8686562: The '562 patent explicitly states the drawbacks of conventional gold capping layers on III-nitride devices: cost, gold diffusion into the electrode stack and semiconductor, and contamination risk to silicon fabrication processes, making monolithic integration challenging. The invention aims to solve this by providing a contact that reduces contamination risk to silicon process flows, making integration more efficient and cost-effective.

Combination 1: US7719030B2 in view of the Background Art (conventional Ti/Al/Ni/Au stack) and US6844258B1 (or general knowledge of refractory metal nitrides as barrier/capping layers).

• US7719030B2 teaches electrical contacts, including aluminum alloys, for low resistance ohmic contacts to III-nitride semiconductors. This reference directly provides the context of forming contacts on Group III-V semiconductor devices with metal layers (at least including Al). It represents the "plurality of metal layers" aspect of the claims, especially for III-V devices.
• The Background Art of US8686562 explicitly describes the conventional practice of using an "electrical contact stack comprising pure films of titanium, aluminum, and nickel, capped with gold" on III-nitride devices. This confirms the "plurality of metal layers" (e.g., Ti, Al, Ni) and the concept of a "capping layer formed over said plurality of metal layers."
• US6844258B1 (Novellus Systems, Inc.) is titled "Selective refractory metal and nitride capping". While the full text is not provided, the title strongly suggests that refractory metal nitrides were known as capping materials. Furthermore, other related patents (US20160190008A1) explicitly mention TiN and WN as under-layers for tungsten, indicating their use in contact structures. A POSITA would be aware that refractory metal nitrides like TiN are used as diffusion barriers and protective layers in semiconductor manufacturing.

Differences & Motivation to Combine:
The primary difference between the conventional art (as described in the '562 background, including the concepts of US7719030B2) and the claims of '562 is the replacement of the noble metal (e.g., gold) capping layer with a refractory metal nitride capping layer (e.g., TiN or TaN) that consists only of that nitride and forms the top of the electrical contact, and has a greater thickness than the bottommost layer.

A POSITA, confronted with the well-known problems of gold contamination in silicon fabrication processes (explicitly stated in the '562 background as a significant drawback to monolithic integration of III-V and Si devices), would have been motivated to seek alternative capping materials that do not suffer from these drawbacks. Refractory metal nitrides like TiN were known in the art as robust, high-temperature stable, and electrically conductive materials, often used as diffusion barriers or protective coatings in semiconductor devices (e.g., US5514908A teaches TiN as a contact barrier).

The motivation to replace gold with a refractory metal nitride like TiN as the topmost capping layer would be driven by:

1. Eliminating Gold Contamination: This is the explicit problem articulated by '562. Replacing gold with a gold-free material would directly address this.
2. Cost Reduction: Gold is expensive. Refractory metal nitrides are generally less costly.
3. Improved Thermal Stability/Diffusion Prevention: Refractory metal nitrides are known for their high thermal stability and barrier properties, which would prevent unwanted diffusion of underlying metals (or the capping layer itself) into the semiconductor or adjacent device regions during subsequent high-temperature processing or device operation. While US5514908A teaches TiN as a contact barrier, its known properties (stability, barrier function) would suggest its suitability for a capping role if diffusion is a concern.

Considering the knowledge that TiN (a refractory metal nitride) acts as a diffusion barrier (US5514908A) and that gold causes contamination and diffusion issues in conventional III-V contacts (US8686562 Background Art), a POSITA would have found it obvious to replace the problematic gold capping layer with a refractory metal nitride capping layer. The general concept of "refractory metal and nitride capping" (US6844258B1) would further guide this choice.

Regarding the specific limitation that the "capping layer consists only of a refractory metal nitride" and forms the "top of said electrical contact": If the purpose is to prevent contamination from the capping layer and to external process flows, then making it only of the non-contaminating material, and placing it at the top, is a logical design choice. Adding other materials would reintroduce the risk of contamination or negate the benefit.

Regarding the "thickness greater than that of a bottommost layer of said plurality of metal layers": The '562 patent specifies approximate thicknesses: first Ti layer (bottommost) ~100Å, Al layer ~1300Å, second Ti layer ~680Å, and TiN capping layer ~600Å. In this specific embodiment, 600Å is indeed greater than 100Å. This specific thickness ratio, however, appears to be an optimization rather than a fundamental inventive step. Given that capping layers are for protection, making them sufficiently thick for robustness is a matter of routine engineering optimization, especially when replacing a material like gold (which has different physical properties) with a new material like TiN. A POSITA would be motivated to optimize layer thicknesses for performance and reliability, including barrier effectiveness.

Conclusion for Obviousness (Combination 1):
A combination of US7719030B2 (for III-V ohmic contacts and aluminum alloys), the Background Art of US8686562 (for the conventional Ti/Al/Ni/Au stack on III-nitride devices and the problem of gold contamination), and the general knowledge of refractory metal nitrides as barrier/capping layers (informed by US5514908A and the suggestive title of US6844258B1) would have rendered claims 1 and 13 obvious to a POSITA. The motivation would be to overcome the known problems of gold contamination and cost in III-V semiconductor fabrication, by replacing the gold capping layer with a functionally equivalent (or superior, in terms of contamination) refractory metal nitride layer, and optimizing its thickness for protective purposes.

Specifically for Claim 13, which narrows the capping layer to "consisting only of a metal selected from the group consisting of titanium nitride (TiN) and tantalum nitride (TaN)", this would also be obvious. TiN is explicitly taught as a barrier layer in US5514908A. TaN shares similar refractory and barrier properties with TiN, and selecting between known refractory metal nitrides for specific applications based on compatibility and performance is a routine choice for a POSITA. The '562 patent itself lists several refractory metal nitrides (TiN, TaN, ZrN, VN, NbN, MoN, WN2) as possible options.The obviousness of US patent 8686562 under 35 U.S.C. § 103 can be analyzed by considering combinations of prior art references that would have motivated a person having ordinary skill in the art (POSITA) to arrive at the claimed invention. The claimed invention, as defined by independent claims 1 and 13, focuses on an electrical contact for a semiconductor device comprising an electrode stack with metal layers capped by a refractory metal nitride, where this capping layer consists only of the refractory metal nitride, forms the top of the contact, and has a thickness greater than the bottommost metal layer. Claim 13 specifically applies this to Group III-V semiconductor devices, with the capping layer limited to titanium nitride (TiN) or tantalum nitride (TaN).

Level of Ordinary Skill in the Art (POSITA):
A POSITA in this field would typically possess a master's degree in electrical engineering, materials science, or a related discipline, coupled with several years of experience in semiconductor device fabrication, particularly concerning compound semiconductors, metallization processes, and addressing issues like material diffusion and contamination.

Problem Addressed by US8686562:
The patent explicitly identifies significant drawbacks of conventional electrical contacts for III-nitride devices that utilize aluminum in an electrode stack and a gold capping layer. These drawbacks include the high cost of gold, its diffusion into the electrode stack and semiconductor body, and its propensity to contaminate silicon fabrication process flows, thereby hindering the monolithic integration of Group III-V and Group IV semiconductor devices. The disclosed invention aims to overcome these issues by providing a contact that reduces contamination risk to silicon processes, leading to more efficient and cost-effective integration.

Combination of Prior Art for Obviousness:
A compelling argument for obviousness can be made by combining the teachings of US7719030B2, the Background Art described in US8686562, and the general knowledge of refractory metal nitrides as barrier or capping layers (as exemplified by US5514908A and the suggestive title of US6844258B1).

1. US7719030B2 (International Rectifier Corporation): This patent, from the original assignee of US8686562, teaches "Aluminum alloys for low resistance, ohmic contacts to III-nitride or compound semiconductor". This directly addresses the formation of electrical contacts on Group III-V (III-nitride) semiconductor devices using aluminum-containing metal layers, which aligns with the "plurality of metal layers" aspect of the independent claims. This reference effectively represents the state of the art for forming ohmic contacts on III-V devices.

2. Background Art of US8686562: The patent's own background section describes the widely used conventional approach: "an electrical contact stack comprising pure films of titanium, aluminum, and nickel, capped with gold" on III-nitride devices. This explicitly discloses the "plurality of metal layers" (e.g., Ti, Al, Ni) and a "capping layer formed over said plurality of metal layers," forming a conventional electrode stack. Crucially, it also highlights the critical problem of gold contamination and diffusion in integrated III-V/Group IV manufacturing.

3. General Knowledge of Refractory Metal Nitrides as Barrier/Capping Layers (e.g., US5514908A and US6844258B1):

   • US5514908A (Sgs-Thomson Microelectronics, Inc.) describes an "Integrated circuit with a titanium nitride contact barrier". This demonstrates that TiN, a refractory metal nitride, was known in the art for its barrier properties within semiconductor contact structures, typically to prevent diffusion.
   • US6844258B1 (Novellus Systems, Inc.) is titled "Selective refractory metal and nitride capping". While the full text is not provided, the title strongly indicates that the use of refractory metals and nitrides as capping layers was known. Furthermore, other related patents (e.g., US20160190008A1) refer to titanium (Ti), titanium nitride (TiN), and tungsten nitride (WN) as under-layers for tungsten, confirming the awareness and use of refractory metal nitrides in various roles within contact structures.

Motivation to Combine and Obviousness:

A POSITA, armed with the knowledge from US7719030B2 regarding ohmic contacts to III-nitride devices, and acutely aware of the explicit problems detailed in the background of US8686562 regarding gold capping layers (cost, diffusion, and silicon process contamination), would have been strongly motivated to seek an alternative capping material. Refractory metal nitrides, such as TiN, were well-known in the semiconductor industry for their high thermal stability, electrical conductivity, and diffusion barrier properties (as shown by US5514908A).

The motivation to replace the problematic gold capping layer with a refractory metal nitride like TiN or TaN would stem from:

• Solving the Gold Contamination Problem: This is the most direct and explicitly stated problem that the invention seeks to overcome. Replacing gold with a gold-free, non-contaminating material is a logical solution.
• Reducing Cost: Refractory metal nitrides are generally less expensive than noble metals like gold.
• Leveraging Known Properties: The robust barrier properties and thermal stability of refractory metal nitrides would make them a natural choice for a protective capping layer, especially when diffusion is a concern. The general concept of "refractory metal and nitride capping" from US6844258B1 further supports this direction.

The features of the claims specifying that the "capping layer consists only of a refractory metal nitride" and "forms a top of said electrical contact" would also be an obvious design choice. To effectively prevent contamination from the capping layer itself and to external process flows, making it purely of the desired non-contaminating material and placing it as the outermost layer is a straightforward engineering decision.

Regarding the specific thickness requirement ("thickness greater than that of a bottommost layer of said plurality of metal layers"), the patent describes a first Ti layer (bottommost) of ~100Å and a TiN capping layer of ~600Å in one embodiment. While a specific ratio, ensuring a sufficient thickness for a protective capping layer to be effective, especially when replacing a material with different physical properties (gold vs. TiN), falls within the realm of routine optimization for a POSITA.

Conclusion for Obviousness:
Therefore, the combination of US7719030B2, the explicit problems identified in the Background Art of US8686562 (i.e., gold contamination and cost in III-V device fabrication), and the known use and properties of refractory metal nitrides as barrier or capping layers (as taught by US5514908A and the general knowledge reflected in US6844258B1), would have rendered claims 1 and 13 of US8686562 obvious to a person having ordinary skill in the art at the time of the invention. The motivation for such a combination would be to solve the well-recognized issues associated with gold-capped electrical contacts, particularly in the context of integrating III-V and silicon semiconductor devices.