Invalidity dossier
US 8669167
Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices
Current assignee: GlobalFoundries US Inc
Added 9/23/2026, 7:51:35 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview: US8669167B1
Title: Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices
Assignee/Applicant: Originally assigned to International Business Machines Corporation (IBM); current assignee listed as GlobalFoundries US Inc.
Key Dates:
- Priority/filing date: 2012-08-28
- Publication date: 2014-03-11
- Anticipated expiration: 2032-08-28
- Legal status: Expired – Fee Related
Inventor(s): Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
Purpose:
The invention addresses threshold voltage (Vt) engineering in FIN field-effect transistor (FINFET) devices. Rather than doping fins—which introduces random dopant fluctuation (RDF) problems in aggressively scaled devices—it uses a work function setting material, deposited in an amount proportional to fin pitch, to enable multiple threshold voltage devices.
Plain-Language Scope:
The patent covers a method of fabricating a FINFET device and the resulting device. A semiconductor-on-insulator (SOI) wafer with an SOI layer over a buried oxide (BOX) is provided; an oxide layer and fins are patterned; an interfacial oxide is formed on the fins; and a conformal gate dielectric, conformal gate metal layer, and conformal work function setting material layer are deposited to form at least one gate stack. The volume of the gate metal and work function setting material is proportional to fin pitch. The patent describes fabricating multiple FINFETs with varying fin pitch (e.g., tight, medium, wide) and notes that an angled deposition process can deposit less work function material at tighter fin pitch. Fin patterning may use sidewall image transfer (SIT).
Source: https://patents.google.com/patent/[US8669167](/patent/US8669167)/en
What the excerpt does not establish:
The excerpted text does not establish the full claim set, prosecution history, or the complete detailed description (e.g., specific materials, thicknesses, or the referenced U.S. patent for gate-last fin-last approaches). It also does not establish the legal status as a fact—the provided status is expressly an assumption, not a legal conclusion. Independent claim language and claim scope limitations beyond the summary descriptions above are not fully verifiable from the excerpt alone.
Generated 10/1/2026, 9:41:46 PM
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Litigation summary
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Proceedings on file (0)
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PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
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Obviousness
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Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.