US 8400835

Here is a concise summary of US Patent 8,400,835.

Title: Non-volatile semiconductor memory

Assignee: The original assignee was Panasonic Corporation. However, recent litigation documents from a case in the Eastern District of Texas (Advanced Memory Technologies, LLC v. SK Hynix Inc.) indicate that the current assignee is likely Advanced Memory Technologies, LLC. A complete chain of title is not available without a direct search of the USPTO assignment database.

Inventors:

• Yukimasa Hamamoto
• Masahiro Toki

Filing Date: July 25, 2011

Issue Date: March 19, 2013

Abstract: When a plurality of non-volatile memory cells in a memory cell array are simultaneously written, bit lines of the plurality of non-volatile memory cells are connected to M data lines, where M is an integer of two or more, based on a column address signal. N switches, where N is an integer of one or more, and a switch control circuit for controlling the N switches, are provided for each data line. The M switch control circuits control the M×N switches to change the levels or apply periods of drain voltages applied to the bit lines of the plurality of memory cells on a memory cell-by-memory cell basis.

Plain-Language Overview of Independent Claims:

Independent Claim 1: This claim describes a non-volatile semiconductor memory system designed for simultaneously writing to multiple memory cells. The system uses a series of data lines connected to the memory cell bit lines. A key feature is the inclusion of "M switch circuits" and "M switch control circuits" that are positioned between the data lines and the drain voltage supply. These circuits allow for individual control of the voltage levels and the duration of voltage application to each memory cell's bit line, enabling more precise and varied writing conditions across the cells being written to simultaneously.

Independent Claim 6: This claim builds upon the system in Claim 1 by adding a "read circuit" and a "state storage circuit." This enhancement allows the memory system to first read the state of the memory cells and store this information. The switch circuits are then controlled based on this stored information, allowing the writing process to be adjusted based on the pre-existing state of the memory cells.

Independent Claim 7: This claim specifies a scenario for the memory system described in Claim 6, where each memory cell can store multiple bits of data. When writing to one bit, the state of another bit within the same cell is first read and stored. The writing process for the first bit is then adjusted based on the stored state of the second bit. This addresses potential interference between bits stored in the same physical memory cell.

Independent Claim 8: This claim also builds on the system in Claim 6. Before writing to the memory cells, their threshold level state (a measure of the stored charge) is read and stored. The writing process is then controlled and modified based on this stored threshold level information. This allows for a more tailored writing process that takes into account the current electrical characteristics of each memory cell.

A search of the CAFC dockets for 2026 did not reveal any cases specifically citing US Patent 8,400,835. However, given the ongoing district court litigation, an appeal to the CAFC in the future is possible.