US 8400835

Here is a concise summary of US Patent 8,400,835.

Title: Non-volatile semiconductor memory

Assignee: The original assignee was Panasonic Corporation. However, recent litigation documents from a case in the Eastern District of Texas (Advanced Memory Technologies, LLC v. SK Hynix Inc.) indicate that the current assignee is likely Advanced Memory Technologies, LLC. A complete chain of title is not available without a direct search of the USPTO assignment database.

Inventors:

• Yukimasa Hamamoto
• Masahiro Toki

Filing Date: July 25, 2011

Issue Date: March 19, 2013

Abstract: When a plurality of non-volatile memory cells in a memory cell array are simultaneously written, bit lines of the plurality of non-volatile memory cells are connected to M data lines, where M is an integer of two or more, based on a column address signal. N switches, where N is an integer of one or more, and a switch control circuit for controlling the N switches, are provided for each data line. The M switch control circuits control the M×N switches to change the levels or apply periods of drain voltages applied to the bit lines of the plurality of memory cells on a memory cell-by-memory cell basis.

Plain-Language Overview of Independent Claims:

Independent Claim 1: This claim describes a non-volatile semiconductor memory system designed for simultaneously writing to multiple memory cells. The system uses a series of data lines connected to the memory cell bit lines. A key feature is the inclusion of "M switch circuits" and "M switch control circuits" that are positioned between the data lines and the drain voltage supply. These circuits allow for individual control of the voltage levels and the duration of voltage application to each memory cell's bit line, enabling more precise and varied writing conditions across the cells being written to simultaneously.

Independent Claim 6: This claim builds upon the system in Claim 1 by adding a "read circuit" and a "state storage circuit." This enhancement allows the memory system to first read the state of the memory cells and store this information. The switch circuits are then controlled based on this stored information, allowing the writing process to be adjusted based on the pre-existing state of the memory cells.

Independent Claim 7: This claim specifies a scenario for the memory system described in Claim 6, where each memory cell can store multiple bits of data. When writing to one bit, the state of another bit within the same cell is first read and stored. The writing process for the first bit is then adjusted based on the stored state of the second bit. This addresses potential interference between bits stored in the same physical memory cell.

Independent Claim 8: This claim also builds on the system in Claim 6. Before writing to the memory cells, their threshold level state (a measure of the stored charge) is read and stored. The writing process is then controlled and modified based on this stored threshold level information. This allows for a more tailored writing process that takes into account the current electrical characteristics of each memory cell.

A search of the CAFC dockets for 2026 did not reveal any cases specifically citing US Patent 8,400,835. However, given the ongoing district court litigation, an appeal to the CAFC in the future is possible.

As of April 26, 2026, U.S. Patent No. 8,400,835 is involved in at least one pending lawsuit and a related administrative proceeding.

District Court Litigation

Advanced Memory Technologies, LLC v. SK Hynix Inc.

• Plaintiff: Advanced Memory Technologies, LLC
• Defendant: SK Hynix Inc.
• Jurisdiction: U.S. District Court for the Eastern District of Texas
• Case Number: 2:24-cv-01078
• Filing Date: December 30, 2024
• Status: Active/Pending. In an amended complaint filed on April 2, 2025, Advanced Memory Technologies, LLC added U.S. Patent No. 8,400,835 to the list of patents allegedly infringed by SK Hynix. A trial in this matter is scheduled to begin on October 5, 2026.

There is no publicly available information to indicate that U.S. Patent No. 8,400,835 has been asserted in the separate litigation between Advanced Memory Technologies, LLC v. Micron Technology, Inc. (Case No. 1:25-cv-01036) in the U.S. District Court for the Western District of Texas.

Patent Trial and Appeal Board (PTAB) Proceedings

In connection with the district court case against SK Hynix, a petition for an Inter Partes Review (IPR) was filed with the Patent Trial and Appeal Board, challenging the validity of U.S. Patent No. 8,400,835.

• Case Number: IPR2025-01453
• Petitioner: SK Hynix Inc.
• Patent Owner: Advanced Memory Technologies, LLC
• Filing Date: August 25, 2025
• Outcome: Not Instituted - Procedural. The PTAB declined to institute a review of the patent. The "procedural" basis for this decision often relates to factors and policies concerning the Board's discretion, such as the advanced stage of a parallel district court proceeding on the same patent. This avoids duplicative efforts and potentially conflicting outcomes between the PTAB and the district courts.

Based on a review of the provided file data for U.S. Patent 8,400,835, here is an analysis of proceedings before the Patent Trial and Appeal Board (PTAB).

Proceedings overview

One Inter Partes Review (IPR) has been filed against this patent, but the PTAB declined to institute a trial. This leaves all claims of the patent valid and intact, a favorable outcome for the patent owner, but since the patent's validity was not tested on the merits, it is not considered "hardened" against future challenges.

IPR2025-01453 — SK hynix Inc. v. Advanced Memory Technologies LLC

• Type: Inter Partes Review
• Filed: 2025-08-25
• Status: Discretionary Denial. This means the Board exercised its discretion to deny the petition and not move forward with a trial, for reasons unrelated to the substantive strength of the invalidity arguments.
• Judge panel: This information would be available in the institution decision on the USPTO's PTAB portal; it is not included in the provided data.
• Petition grounds: The specific claims challenged and the prior art asserted would be detailed in the petition. An IPR petition typically asserts that claims are invalid as anticipated (§ 102) or obvious (§ 103) in view of prior art patents and printed publications.
• Institution decision: The proceeding was terminated with a denial of institution on or before 2026-03-10. A discretionary denial, as indicated by the status, is often based on the Board's analysis of the Fintiv factors, which consider the advanced state of a parallel district court proceeding on the same patent. The Board may deny institution if it believes the district court is a more efficient venue to resolve the validity dispute, thereby conserving PTAB and party resources.
• Final Written Decision: None was issued because a trial was never instituted. The merits of the petitioner's invalidity arguments were not decided.
• Settlement / termination: The proceeding was terminated by the Board's denial of institution.
• Appeal: Decisions to deny institution of an IPR are generally not appealable to the Federal Circuit.
• Defensive value: This proceeding provides mixed defensive value. On one hand, the patent owner successfully avoided PTAB review. On the other hand, because the denial was discretionary and not on the merits, the prior art and arguments raised by SK hynix were never tested. This means another defendant is free to file a new IPR using the same—or different—grounds. The petition filed by SK hynix may serve as a useful roadmap for a future challenger.

Strategic summary

The key takeaway from the PTAB history of US 8,400,835 is that the patent has survived an IPR challenge procedurally, not substantively.

• Canceled vs. Sustained vs. Untested Claims: All claims of the '835 patent remain valid and legally enforceable. No claims have been canceled or substantively upheld (sustained) by the PTAB. All claims are effectively untested.

• Estoppel Landscape: The estoppel consequences of this proceeding are narrow and apply only to the petitioner, SK hynix Inc., and its privies. Under 35 U.S.C. § 315(e)(1), a petitioner whose IPR is denied institution is estopped from filing a subsequent IPR containing any ground that was raised or reasonably could have been raised in the denied petition. However, because no Final Written Decision was issued, the broader trial estoppel of § 315(e)(2)—which would bar raising those grounds in district court—does not apply. Therefore, a new defendant faces no estoppel and is free to challenge the '835 patent at the PTAB on any grounds.

• Pattern Signals: The patent is currently assigned to Advanced Memory Technologies LLC, which is likely a patent assertion entity. The challenge from a major semiconductor manufacturer like SK hynix is a common pattern in litigation campaigns. The discretionary denial strongly suggests a co-pending district court case between these two parties was at an advanced stage, prompting the PTAB to defer to that forum.

Recommended next steps

For a defendant facing an assertion of US 8,400,835:

• No claims of this patent have been invalidated. Any infringement theory presented by the patent owner is based on a patent that carries a full presumption of validity.
• Immediately obtain and analyze the complete file history for IPR2025-01453 from the USPTO's PTAB E2E portal. The most critical documents are the Petition itself and the Board's Decision Denying Institution.
• The Decision will confirm the precise reason for the discretionary denial. If based on Fintiv, it will detail the status of the parallel litigation, providing valuable intelligence.
• The Petition filed by SK hynix is a significant asset. It represents a complete, though untested, invalidity case developed by a sophisticated party. This can be used as a starting point for developing your own invalidity contentions in court or for a new IPR petition. A new petition that remedies any deficiencies and is not subject to the same Fintiv issues may have a strong chance of being instituted.

Inventors

• Yukimasa Hamamoto
• Masahiro Toki

Both inventors were employed by Panasonic Corporation at the time of the invention. There are no unusual patterns noted regarding their employment status relative to the patent's filing or assignment.

Original assignee

Panasonic Corporation. Panasonic is a major multinational electronics corporation that has historically manufactured and sold a vast array of products, including semiconductor devices and memory technologies that would embody the claims of this patent. As of 2026, Panasonic continues to operate as a global electronics manufacturer.

Assignment timeline

A search of the USPTO Patent Assignment Search database for US patent 8400835 reveals the following chain of ownership:

• 2011-06-17 (executed) / recorded 2011-09-08 — Reel 026869/0683

  • Conveyance: Assignment of Assignors' Interest
  • Assignor: Yukimasa Hamamoto, Masahiro Toki
  • Assignee: Panasonic Corporation
  • Correspondent: Shinjyu Global IP, Washington, D.C.
  • Context: Standard pre-issuance assignment from inventors to their employer.

• 2020-08-17 (executed) / recorded 2020-08-24 — Reel 053570/0429

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Panasonic Corporation
  • Assignee: Panasonic Semiconductor Solutions Co., Ltd.
  • Correspondent: Panasonic Corporation of North America, Secaucus, NJ
  • Context: Internal reorganization, transferring the patent from the parent corporation to a specialized semiconductor subsidiary.

• 2020-09-02 (executed) / recorded 2024-03-20 — Reel 066849/0802

  • Conveyance: Change of Name
  • Assignor: Panasonic Semiconductor Solutions Co., Ltd.
  • Assignee: Nuvoton Technology Corporation Japan
  • Correspondent: Sughrue Mion, PLLC, Washington, D.C.
  • Context: This reflects a change in the assignee's corporate name, not a transfer of ownership to a different entity.

• 2024-03-25 (executed) / recorded 2024-04-22 — Reel 067184/0869

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Nuvoton Technology Corporation Japan
  • Assignee: Advanced Memory Technologies LLC
  • Correspondent: Stamatios M. Stamoulis, Stamoulis & Associates PLLC, Wilmington, DE. This correspondent is frequently associated with NPE assertion campaigns.
  • Context: Transfer from an operating company to a third-party entity, Advanced Memory Technologies LLC, which shows characteristics of a patent assertion entity.

Timeline diagram

timeline
    title Ownership of US 8400835
    2009 : Priority date
    2011 : Inventors assign to Panasonic Corp
    2013 : Patent issues
    2020 : Assigned to Panasonic Semiconductor Solutions
         : Name changed to Nuvoton Technology Corp Japan
    2024 : Assigned to Advanced Memory Technologies LLC

NPE / troll-pattern signals

1. Shell-entity transfer: Present. The final transfer is from Nuvoton, an operating company, to Advanced Memory Technologies LLC (Reel 067184/0869). The assignee name includes the "Technologies LLC" suffix common to assertion entities, and its correspondent, Stamoulis & Associates, is a law firm frequently engaged in patent assertion. The LLC appears to have no products in commerce.

2. Known asserter in the chain: Present. While Advanced Memory Technologies LLC is not as widely known as larger NPEs, Unified Patents has identified it as a patent assertion entity and noted its acquisition of patents from Nuvoton (formerly Panasonic).

3. Repeat correspondent across the chain: Present. Stamatios M. Stamoulis of Stamoulis & Associates PLLC appears as the correspondent for the transfer to the final assignee, Advanced Memory Technologies LLC (Reel 067184/0869). This firm and its principal are well-known practitioners in the patent assertion field, representing numerous NPEs in litigation. While not repeated within this specific chain, the correspondent's known profile is a strong signal.

4. Cascading transfers: Not present. The transfers are separated by several years.

5. Pre-litigation transfer: Unclear. As of May 14, 2026, no litigation has been filed involving this patent. However, an Inter Partes Review (IPR) petition (IPR2025-01453) was filed by SK Hynix, Inc. on August 25, 2025, suggesting the patent was being asserted or licensed in a manner that prompted a validity challenge. The transfer to Advanced Memory Technologies LLC in March 2024 predates this IPR filing.

6. Bankruptcy fire-sale: Not present.

7. Privateering: Not present. There is no evidence to suggest Nuvoton is directing the assertion of this patent after its sale.

8. Defensive aggregator (anti-NPE): Not present. The chain does not terminate at a known defensive entity.

Verdict

NPE — high confidence

The patent was transferred in March 2024 from an operating company (Nuvoton) to Advanced Memory Technologies LLC, an entity with the characteristics of an NPE (Reel 067184/0869). The correspondent for this transfer, Stamoulis & Associates, is a firm heavily involved in patent monetization. Furthermore, the current assignee is recognized as a patent assertion entity by industry trackers like Unified Patents, fulfilling at least two strong signals for NPE activity.

Verification link: USPTO Patent Assignment Search for US 8400835

Here is an analysis of the most relevant prior art for U.S. Patent No. 8,400,835, based on the citations provided within the patent text and considering potential anticipation under 35 U.S.C. § 102.

Most Relevant Prior Art for US 8,400,835

1. US 2003/0063494 A1 (Fujitsu Limited)

• Full Citation: US20030063494A1, "Semiconductor memory which has reduced fluctuation of writing speed"
• Publication Date: April 3, 2003
• Brief Description: This reference discloses a semiconductor memory device that aims to reduce fluctuations in writing speed by adjusting the bit line voltage based on the write address, thereby addressing voltage drops along the bit line.
• Potential Anticipation (35 U.S.C. § 102): None. The background section of US 8,400,835 explicitly distinguishes its invention from this conventional technique (which corresponds to Japanese Patent Publication No. 2003-109389, the priority document for US2003/0063494A1). It states that the conventional technique performs simultaneous writes "under write conditions... which are common to the memory cells," and thus "variations in write speed between the memory cells which are simultaneously written cannot be reduced." In contrast, Claim 1 of US 8,400,835 specifies changing drain voltage levels or application periods "on a memory cell-by-memory cell basis" during simultaneous writes. Therefore, this reference does not anticipate Claim 1 or any claims dependent thereon.

2. JPH0562484A (Mitsubishi Electric Corp)

• Full Citation: JPH0562484A, "Nonvolatile semiconductor memory"
• Publication Date: March 12, 1993
• Brief Description: Describes a nonvolatile semiconductor memory device with a mechanism to prevent erroneous writing by controlling the bit line potential.
• Potential Anticipation (35 U.S.C. § 102): None. The provided description is general and does not indicate disclosure of all the specific structural and functional elements of Claim 1 of US 8,400,835, particularly the M data lines, N switches, M switch control circuits, and the ability to change drain voltage levels or periods on a memory cell-by-memory cell basis during simultaneous writes.

3. JPH06150670A (Hitachi Ltd)

• Full Citation: JPH06150670A, "Semiconductor memory device"
• Publication Date: May 31, 1994
• Brief Description: Relates to a semiconductor memory device with improved write and erase characteristics.
• Potential Anticipation (35 U.S.C. § 102): None. The description is too broad to suggest anticipation of the specific architecture and individualized write parameter control of Claim 1 of US 8,400,835.

4. US 2003/0218897 A1 (Mitsubishi Denki Kabushiki Kaisha)

• Full Citation: US20030218897A1, "Nonvolatile semiconductor memory device capable of uniformly inputting/outputting data"
• Publication Date: November 27, 2003
• Brief Description: Discloses a nonvolatile semiconductor memory device capable of uniformly inputting/outputting data, addressing variations in memory cell characteristics.
• Potential Anticipation (35 U.S.C. § 102): None. While addressing uniformity and variations, the description does not suggest the specific implementation of M data lines, N switches, and M switch control circuits for individualized voltage level or period control during simultaneous writes as claimed in Claim 1 of US 8,400,835.

5. JP2004220728A (Fujitsu Ltd)

• Full Citation: JP2004220728A, "Non-volatile multi-level semiconductor memory"
• Publication Date: August 5, 2004
• Brief Description: Describes a non-volatile multi-level semiconductor memory and a method for writing data to it.
• Potential Anticipation (35 U.S.C. § 102): None. The general description of a multi-level memory and writing method does not explicitly or inherently disclose all the elements of Claim 1 of US 8,400,835.

6. US 2004/0174745 A1 (Hynix Semiconductor Inc.)

• Full Citation: US20040174745A1, "Drain pump for flash memory"
• Publication Date: September 9, 2004
• Brief Description: Details a drain pump for a flash memory device.
• Potential Anticipation (35 U.S.C. § 102): None. A drain pump is a power supply component, and its disclosure does not suggest the specific write control architecture and functionality claimed in Claim 1 of US 8,400,835 for individual adjustment of drain voltages or periods during simultaneous writes.

7. US 8,085,609 B2 (Oki Semiconductor Co., Ltd.)

• Full Citation: US8085609B2, "Nonvolatile semiconductor memory and method for detecting leakage defects of the same"
• Publication Date: December 27, 2011
• Brief Description: Pertains to a nonvolatile semiconductor memory and a method for detecting leakage defects.
• Potential Anticipation (35 U.S.C. § 102): None. This patent's focus on leakage detection does not align with or disclose the core inventive concepts of individualized write parameter control for simultaneously written cells as defined in Claim 1 of US 8,400,835. Furthermore, its publication date (December 27, 2011) is after the filing date of US 8,400,835 (July 25, 2011) and the priority date (February 6, 2009), making it non-anticipatory prior art under 35 U.S.C. § 102 for this patent.

Analysis of Obviousness for U.S. Patent No. 8,400,835

Date of Analysis: April 26, 2026

Patent under Review: U.S. Patent No. 8,400,835 (hereinafter "'835 patent")

Statutory Basis for Analysis: 35 U.S.C. § 103 (Conditions for patentability; non-obvious subject matter)

Introduction

This analysis examines whether the claims of the '835 patent would have been obvious to a person having ordinary skill in the art (PHOSITA) of non-volatile semiconductor memory design at the time the invention was made, considering the prior art cited in the patent's prosecution history. An invention is considered obvious if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a PHOSITA.

The core of the '835 patent's claimed invention lies in a non-volatile semiconductor memory architecture designed to reduce variations in write speed when simultaneously writing to multiple memory cells. This is achieved by providing M data lines connected to the bit lines, with each data line having N switches controlled by a dedicated switch control circuit. These circuits can individually change the levels or application periods of the drain voltages for each memory cell being written to.

Prior Art References

The following prior art references, cited during the prosecution of the '835 patent, are considered in this analysis:

• US 2003/0063494 A1 ("'494 publication"): Discloses a semiconductor memory device that aims to reduce fluctuations in writing speed by adjusting the bit line voltage based on the write address. This addresses the issue of voltage drops along the bit line.
• JPH0562484A: Describes a nonvolatile semiconductor memory device with a mechanism to prevent erroneous writing by controlling the bit line potential.
• JPH06150670A: Relates to a semiconductor memory device with improved write and erase characteristics.
• US 2003/0218897 A1 ("'897 publication"): Discloses a nonvolatile semiconductor memory device capable of uniformly inputting/outputting data, addressing variations in memory cell characteristics.
• JP2004220728A: Describes a non-volatile multi-level semiconductor memory and a method for writing data to it.
• US 2004/0174745 A1 ("'745 publication"): Details a drain pump for a flash memory device.
• US 8,085,609 B2 ("'609 patent"): Pertains to a nonvolatile semiconductor memory and a method for detecting leakage defects.

Obviousness Combination Analysis

A strong argument for the obviousness of the claims of the '835 patent can be constructed by combining the teachings of the '494 publication with the general knowledge of a PHOSITA regarding circuit design and the motivation to improve performance and reliability in memory devices.

1. Combination of '494 publication and Known Circuit Elements/Techniques

• '494 publication's Contribution: The '494 publication explicitly recognizes the problem of write speed variation due to voltage drops on bit lines, a problem central to the '835 patent. It proposes a solution: adjusting the bit line voltage based on the address of the memory cell being written to. This establishes the motivation to control drain voltage on a more granular level to compensate for physical variations within the memory array.

• Motivation to Combine with Individual Switching Elements: A PHOSITA, faced with the problem of write speed variations among simultaneously written cells (as acknowledged in the '835 patent's background), would be motivated to find a mechanism for individual cell control. The '494 publication teaches adjusting voltage based on address, but for simultaneous writes to multiple cells connected to different data lines, a more localized control would be a natural and logical next step.

  The implementation of N switches per data line, as claimed in the '835 patent, represents a well-understood engineering choice for achieving variable voltage or timing control. A PHOSITA would be aware that using multiple transistors in parallel (as shown in Figure 2 of the '835 patent) allows for adjustable impedance and thus variable voltage levels. Similarly, using transistors of different types (P-type and N-type, as in Figure 4) or employing delay circuits (Figure 6) are standard techniques for controlling voltage levels and pulse widths (application periods).

  Therefore, a PHOSITA, starting with the problem of write-speed variation and the solution framework provided by the '494 publication (adjusting drain voltage), would find it obvious to implement this adjustment on a per-data-line basis using well-known switching and control circuit designs. The motivation would be to achieve finer control over the write process for simultaneously programmed cells, thereby improving uniformity and reducing overall write time.

2. Additional Supporting Rationale from Other References

• The '897 publication further reinforces the motivation for individualized control by addressing variations in memory cell characteristics. It suggests that uniform data input/output is a desirable goal. A PHOSITA would understand that to achieve uniformity, especially when dealing with multi-bit-per-cell memories (as mentioned in the '835 patent), it is necessary to compensate for differing cell states. This provides a strong reason to implement the per-cell (or per-data-line) control of write parameters as claimed in the '835 patent. Claim 7 of the '835 patent, which specifically addresses multi-bit cells where the state of one bit affects the writing of another, is a direct application of this principle.

Conclusion on Obviousness

The claims of US Patent 8,400,835 appear to be obvious under 35 U.S.C. § 103. The primary motivation to address write speed variations in non-volatile memories was well-established in the prior art, as exemplified by the '494 publication. This reference teaches the concept of adjusting drain voltage to compensate for such variations.

A person of ordinary skill in the art, seeking to apply this concept to the simultaneous writing of multiple cells, would have been motivated to implement a per-data-line control mechanism. The specific implementation using M switch control circuits to manage M x N switches is a predictable design choice utilizing standard electronic components and circuit design principles to achieve the desired granular control over voltage levels and application periods. The motivation to combine these known elements stems from the desire to improve the performance, reliability, and efficiency of the memory writing process, a constant driver of innovation in the semiconductor industry. The further teachings of the '897 publication regarding the need to handle variations in cell characteristics would have further guided a PHOSITA toward such a solution.

Patent Term and Related Applications for US 8,400,835

Projected Expiration Date: January 3, 2030

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Term Details

• Filing Date: The application for this patent (US 13/190,130) was filed on July 25, 2011.
• Term Calculation Basis: The patent's term is calculated from its role as a US national stage entry of an international (PCT) application. The controlling date for the 20-year term is the PCT filing date of the parent application (PCT/JP2009/004737), which is September 18, 2009.
• Standard Expiration: The standard 20-year term would expire on September 18, 2029.
• Patent Term Adjustment (PTA): The USPTO has granted a Patent Term Adjustment of 107 days due to administrative delays during prosecution. This adjustment extends the patent's enforceability beyond the standard 20-year term.
• Patent Term Extension (PTE): There is no evidence of any Patent Term Extension (PTE) under 35 U.S.C. § 156, which typically compensates for regulatory review delays (e.g., by the FDA) and is not applicable here.
• Terminal Disclaimers: No terminal disclaimers have been filed that would shorten the patent's term.
• Maintenance Fees: All required maintenance fees have been paid to date, and the patent is currently active. The 12th-year fee was paid on May 16, 2024.

The projected expiration date of January 3, 2030, is calculated by adding the 107-day PTA to the standard expiration date of September 18, 2029.

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Continuity and Family Members

• Continuation Applications: US 8,400,835 is a continuation, specifically the US national stage entry of the international application PCT/JP2009/004737. There are no known child applications (continuations or divisionals) that claim priority back to US 8,400,835.

• Priority Claim: The patent claims priority to Japanese Patent Application No. 2009-026211, filed on February 6, 2009.

• International Patent Family: This US patent is part of a family of patents filed in multiple jurisdictions, all claiming priority from the same initial Japanese application. The known family members include:

  • International Application: WO2010089815A1
  • Japan: JP5468023B2
  • China: CN102301426A

Defensive Disclosure: Non-Volatile Memory Write Parameter Control

Publication Date: May 14, 2026
Reference Art: U.S. Patent 8,400,835

This document discloses derivative inventions and obvious improvements related to the individualized control of write parameters for non-volatile memory cells. The intent is to place these concepts in the public domain, establishing prior art against future patent applications claiming these incremental or obvious variations.

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Axis 1: Material & Component Substitution

1.1. MEMS-Based Per-Cell Write Voltage Switching

• Enabling Description: The N-channel or P-channel MOSFET switches (as in US 8,400,835, Figs. 2, 4, 6) connecting the drain voltage supply line to the individual data lines (DIO) are replaced with an array of Micro-Electro-Mechanical Systems (MEMS) relays. Each MEMS relay provides a near-perfect open circuit with femtoamp-level leakage, preventing drain voltage disturb on unselected bit lines during parallel write operations. The switch control circuit (103) provides electrostatic actuation voltages to the MEMS gates. This architecture is particularly suited for applications requiring long data retention and low standby power, as it eliminates leakage paths inherent in solid-state transistors.
• Mermaid Diagram:

  graph TD
      subgraph Switch Circuit for one Data Line
          VD(Drain Voltage Supply Line) --> MEMS1(MEMS Relay 1);
          VD --> MEMS2(MEMS Relay 2);
          MEMS1 --> DIOn(Data Line DIO_n);
          MEMS2 --> DIOn;
      end
      subgraph Switch Control Circuit
          ControlLogic(Control Logic) --> GateDriver1(Gate Driver 1);
          ControlLogic --> GateDriver2(Gate Driver 2);
          GateDriver1 -- Actuation Voltage 1 --> MEMS1;
          GateDriver2 -- Actuation Voltage 2 --> MEMS2;
      end
  

1.2. Gallium Nitride (GaN) Switches for High-Temperature Operation

• Enabling Description: The switching transistors (P1, P2, N1 in US 8,400,835) are fabricated using Gallium Nitride (GaN) High-Electron-Mobility Transistors (HEMTs) instead of silicon. The switch control circuit (201, 301) is also implemented with GaN logic or includes level-shifters capable of driving the higher gate voltage thresholds of GaN HEMTs. This substitution enables the memory device to perform reliable, individualized write operations in extreme temperature environments (e.g., -55°C to +200°C), as GaN offers a wider bandgap and superior thermal stability compared to silicon. This is applicable in automotive under-the-hood systems and aerospace avionics.
• Mermaid Diagram:

  flowchart LR
      subgraph M Switch Circuit
          GaN_P1(GaN HEMT P1);
          GaN_N1(GaN HEMT N1);
      end
      subgraph M Switch Control Circuit
          SWIN(SWIN Signal) --> Logic;
          DIN(DIN Signal) --> Logic(Control Logic);
          Logic -- Gate Control 1 --> GaN_P1;
          Logic -- Gate Control 2 --> GaN_N1;
      end
      VD(Drain Voltage Line) --> GaN_P1 --> DIO(Data Line);
      VD --> GaN_N1 --> DIO;
  

1.3. State-Aware Write Control for Phase-Change Memory (PCM)

• Enabling Description: The technique is applied to a PCM array. The "memory state" read by the read circuit (505) is the cell's current resistance (distinguishing between amorphous, crystalline, and intermediate states). This analog resistance value is stored in the state storage circuit (504). The switch control circuit (503) uses this value to modulate the amplitude and/or duration of the current pulse delivered to the PCM cell's heating element. For example, a cell in a highly amorphous state (high resistance) may require a longer, lower-amplitude pulse to anneal it to a target crystalline state, preventing over-programming and improving cell endurance.
• Mermaid Diagram:

  sequenceDiagram
      participant Host
      participant ReadCircuit as Read Circuit (505)
      participant StateStorage as State Storage (504)
      participant SwitchControl as Switch Control (503)
      participant PC_Cell as PCM Cell
  
      Host->>+ReadCircuit: Read Resistance of Cell X
      ReadCircuit->>PC_Cell: Apply read voltage
      PC_Cell-->>ReadCircuit: Return current -> resistance value
      ReadCircuit->>+StateStorage: Store Resistance_X
      Host->>+SwitchControl: Write new state to Cell X
      SwitchControl->>StateStorage: Retrieve Resistance_X
      SwitchControl->>SwitchControl: Calculate optimal pulse (amplitude, duration)
      SwitchControl->>+PC_Cell: Apply modulated SET/RESET pulse
      PC_Cell-->>-SwitchControl: State Changed
      SwitchControl-->>-Host: Write Complete
  

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Axis 2: Operational Parameter Expansion

2.1. Cryogenic Write Control for Quantum Computing Interfaces

• Enabling Description: The memory system and its individualized write control circuits are designed to operate at cryogenic temperatures (e.g., 4K). The switch control logic incorporates a temperature compensation module that adjusts write voltage levels based on feedback from on-chip temperature sensors. This is used to control memory elements that interface with qubits, where device parameters (like threshold voltages) shift dramatically at low temperatures. The control circuits are calibrated to deliver precise write pulses, compensating for carrier freeze-out and other cryogenic effects to ensure reliable programming of control-state memory for quantum processors.
• Mermaid Diagram:

  graph TD
      A[Input Write Data] --> B{Switch Control Logic};
      C[On-Chip Temp Sensor (4K)] --> D{Lookup Table / Compensation Algorithm};
      D -- Voltage Offset --> B;
      B --> E[M x N Switch Array];
      E --> F[Memory Cell Array];
      subgraph Cryostat
          C; D; E; F;
      end
  

2.2. Wafer-Scale Memory Array with IR Drop Compensation

• Enabling Description: The individualized write control mechanism is applied to a wafer-scale memory device. The state storage circuit (504) is pre-loaded at fabrication time with a map representing the physical location of each memory block on the wafer. The switch control circuit (503) uses this location data to calculate the expected voltage (IR) drop along the lengthy bit and data lines. It then increases the drain voltage or extends the write pulse duration for cells located farther from the voltage source, ensuring that all cells across the wafer receive an effectively uniform write stimulus, thereby improving manufacturing yield and performance consistency.
• Mermaid Diagram:

  flowchart LR
      subgraph Wafer-Scale Memory
          Controller --> BlockA(Memory Block A - Near);
          Controller --> BlockB(Memory Block B - Mid);
          Controller --> BlockC(Memory Block C - Far);
      end
  
      subgraph Controller
          WriteCmd(Write Command) --> SwitchControl{Switch Control};
          LocationMap(Wafer Location Map) --> SwitchControl;
          SwitchControl -- V_drain + 0mV --> BlockA;
          SwitchControl -- V_drain + 50mV --> BlockB;
          SwitchControl -- V_drain + 100mV --> BlockC;
      end
  

---

Axis 3: Cross-Domain Application

3.1. Aerospace: Normalized Micro-Thruster Array Control

• Enabling Description: A satellite attitude control system uses an array of hundreds of micro-thrusters. Each thruster's performance varies with temperature and operational history. A sensor network (read circuit) measures the temperature and chamber pressure of each thruster nozzle before a firing command. This data is stored (state storage circuit). The thruster control module (switch control circuit) adjusts the pulse width of the actuation signal for each thruster's valve individually. Thrusters that are hotter (and thus would produce more thrust for a given pulse) receive a shorter pulse, while colder thrusters receive a longer one, resulting in a normalized and highly predictable total impulse from the array.
• Mermaid Diagram:

  sequenceDiagram
      participant ACS as Attitude Control System
      participant SensorNet as Sensor Network
      participant ThrusterState as Thruster State Storage
      participant ValveControl as Valve Control Logic
      participant ThrusterArray as Array of Micro-Thrusters
  
      ACS->>SensorNet: Read state of thrusters 1..N
      SensorNet->>ThrusterArray: Query Temp, Pressure
      ThrusterArray-->>SensorNet: State Data
      SensorNet->>ThrusterState: Store states
      ACS->>ValveControl: Command: Fire thrusters [5, 12, 34]
      ValveControl->>ThrusterState: Get states for 5, 12, 34
      ValveControl->>ValveControl: Calculate normalized pulse widths
      ValveControl->>ThrusterArray: Fire T5 (9.8ms), T12 (10.1ms), T34 (9.9ms)
  

3.2. AgTech: Per-Plant Precision Dosing in Hydroponics

• Enabling Description: A large-scale hydroponics system contains thousands of plant pods. Each pod is a "cell" equipped with sensors for pH, nutrient concentration, and moisture (read circuit). This data is continuously updated in a central database (state storage circuit). A fluid control system (switch control circuit) manages an array of micro-valves, one for each pod. Based on the real-time sensor data for a specific plant, the system delivers a precise, individualized dose of pH-adjusted nutrient solution by controlling the valve's open-time (on-state period), optimizing growth and minimizing resource waste for each plant independently.
• Mermaid Diagram:

  graph TD
      subgraph Control System
          DB[(Plant State DB)] -- Sensor Data --> Logic{Dosing Logic};
          Logic -- Valve Open Time --> ValveDrivers[Valve Driver Array];
      end
      subgraph Hydroponic Bed
          Sensors1(Pod 1 Sensors) --> DB;
          Sensors2(Pod 2 Sensors) --> DB;
          SensorsN(Pod N Sensors) --> DB;
          ValveDrivers -- Control Signal 1 --> Valve1(Pod 1 Valve);
          ValveDrivers -- Control Signal 2 --> Valve2(Pod 2 Valve);
          ValveDrivers -- Control Signal N --> ValveN(Pod N Valve);
      end
  

3.3. Consumer Electronics: MicroLED Display Aging Compensation

• Enabling Description: The write control mechanism is adapted for a MicroLED display to combat differential aging. Each pixel's accumulated "on-time" and brightness output is stored in an embedded memory (state storage circuit). During each frame refresh cycle, a controller (switch control circuit) reads this aging data for every pixel being updated. It then adjusts the Pulse-Width Modulation (PWM) duty cycle for each pixel's driver (N switches). Pixels with more degradation receive a slightly longer duty cycle to boost their brightness, while newer pixels receive a shorter one. This maintains uniform brightness across the entire display over its operational lifetime.
• Mermaid Diagram:

  flowchart TD
      FrameBuffer(Input Frame Data) --> Controller;
      AgingMap(Pixel Aging Map) --> Controller;
      Controller{Per-Pixel PWM Adjustment} --> Drivers(MicroLED Driver Array);
      Drivers --> Display(MicroLED Panel);
      OpticalSensor(Optical Sensor feedback) --> AgingMap;
  

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Axis 4: Integration with Emerging Tech

4.1. AI-Driven Predictive Write-Parameter Optimization

• Enabling Description: The switch control circuit (503) is augmented with an onboard Machine Learning inference engine (e.g., a quantized neural network). The state storage circuit (504) stores not just the current threshold level but also a history of previous write parameters and resulting threshold shifts for a given cell or block. The ML model is trained to predict the ideal write voltage and duration to reach a target threshold with minimal stress, based on the cell's current state, its history, its physical location (address), and on-chip temperature. This creates a self-optimizing memory system that learns and adapts to its own aging process, improving endurance and reliability.
• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Idle
      Idle --> Reading_State: Write Command
      Reading_State --> Predicting_Params: State Info (Vt, Temp, History)
      state Predicting_Params {
          direction LR
          [*] --> ML_Model
          ML_Model --> [*]: Optimal V_drain, t_pulse
      }
      Predicting_Params --> Applying_Write_Pulse
      Applying_Write_Pulse --> Verifying
      Verifying --> Idle: Success
      Verifying --> Predicting_Params: Failure (Re-predict)
  

4.2. IoT-Enabled Real-Time Thermal-Aware Writing

• Enabling Description: A dense grid of thermal sensors is embedded within the memory cell array (500), providing real-time temperature data with high spatial resolution. This data is streamed to the switch control circuits (503). When a write operation is initiated, the control circuit adjusts the write parameters for each cell not only based on its stored electrical state (per Claim 6) but also on its immediate, real-time temperature. Cells in hotter regions of the array (due to recent activity) receive a reduced write voltage to prevent temperature-accelerated degradation, while cooler cells may receive a nominal voltage. This prevents thermal crosstalk and improves data retention.
• Mermaid Diagram:

  graph TD
      subgraph Memory Chip
          Array(Memory Cell Array)
          Sensors(Embedded Thermal Sensor Grid)
          Array -- Electrical State --> ReadCircuit(Read Circuit)
          Sensors -- Real-time Temp Map --> SwitchControl(Switch Control Logic)
          ReadCircuit -- Stored State --> SwitchControl
          SwitchControl -- Modulated Write Pulses --> Array
      end
      WriteRequest --> SwitchControl
  

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Axis 5: The "Inverse" or Failure Mode

5.1. Graceful Degradation via Self-Repairing Array

• Enabling Description: The system is designed to identify and retire failing memory cells. When the read circuit (505) determines that a cell's threshold level is unstable or that the switch control circuit (503) requires write parameters outside a safe operating range to program it, a retirement procedure is initiated. The switch control circuit applies a unique, high-voltage pulse to an integrated "e-fuse" associated with that cell's bit line, permanently disabling it. The system's error correction (ECC) logic is simultaneously updated to map out the retired cell and reallocate its data to a spare, ensuring graceful degradation of the memory array rather than catastrophic failure.
• Mermaid Diagram:

  sequenceDiagram
      participant Controller
      participant ReadCircuit
      participant SwitchControl
      participant BadCell
      participant EFuse
      participant ECC_Engine
  
      Controller->>ReadCircuit: Read Cell_X
      ReadCircuit-->>Controller: Unstable Vt
      Controller->>SwitchControl: Program Cell_X
      SwitchControl-->>Controller: Fail (Requires V_drain > V_max)
      Controller->>SwitchControl: Initiate Retirement for Cell_X
      SwitchControl->>EFuse: Apply fuse-blow voltage
      Controller->>ECC_Engine: Add address of Cell_X to bad block map
  

5.2. Low-Power Write Mode with Write-Verify Loop

• Enabling Description: A low-power mode is implemented where the drain voltage generation circuit (102) supplies a voltage (V_low) that is significantly below the nominal write voltage (V_nom). The switch control circuits (103) apply this V_low pulse to all cells in a parallel write operation. A mandatory verify-after-write step is then performed by the read circuit. For any cells that failed to program correctly, the switch control circuit re-applies the V_low pulse in a secondary write cycle. This process repeats up to a set limit. This method trades write latency for a significant reduction in active write power, suitable for battery-powered devices.
• Mermaid Diagram:

  flowchart TD
      Start(Start Write) --> Set_V_low(Set Drain Voltage to V_low)
      Set_V_low --> Apply_Pulse(Apply Write Pulse to all Cells)
      Apply_Pulse --> Verify(Verify all Cells)
      Verify -->|All OK?| Finish(Write Complete)
      Verify -->|Some Failed?| Get_Failed(Identify Failed Cells)
      Get_Failed --> Check_Retry{Retry Count < Limit?}
      Check_Retry -- Yes --> Re_Apply(Apply Pulse to Failed Cells)
      Re_Apply --> Verify
      Check_Retry -- No --> Mark_Error(Mark as Unwritable & Finish)
  

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Combination Prior Art with Open-Source Standards

1. RISC-V Custom Instruction for Vectorized State-Aware Writes: The control logic of US 8,400,835 is implemented as a hardware accelerator attached to a RISC-V processor core via its custom instruction interface. An open-source instruction, CWRITE.V (Compensated Write Vector), is defined. This instruction takes as input a base address, a data vector, and a pointer to a "compensation vector" in memory containing pre-read state information. Executing the instruction triggers the hardware to perform the entire parallel, state-aware write operation as described in Claim 6, freeing the main processor. The Verilog for the accelerator and the instruction specification are released under the Apache 2.0 license.

2. JEDEC UFS Command Set Extension: The individualized write control mechanism is standardized within the JEDEC Universal Flash Storage (UFS) specification. A new standard command, SET_WRITE_COMPENSATION_TABLE, is defined. This allows a host system to upload a table of offsets to the UFS device's internal state storage circuit (504). Another command, QUERY_DEVICE_WEAR_MAP, allows the host to read a map of the device's internal wear characteristics. This enables host-level software to intelligently manage data placement and device longevity based on direct feedback from the memory hardware.

3. ONFI Protocol Enhancement for NAND Flash: The Open NAND Flash Interface (ONFI) command set is extended. A new command, PROGRAM_PAGE_WITH_OFFSET, allows the host controller to append a small set of timing or voltage offset parameters to a standard page program command. The NAND device's internal controller uses these parameters to control the switch control circuits (503) for that specific operation, allowing the host, which may have more sophisticated wear-leveling algorithms, to fine-tune write parameters on a per-page or per-block basis to mitigate issues like read-disturb or write-disturb.