Prior art

Here is an analysis of the most relevant prior art for U.S. Patent No. 8,400,835, based on the citations provided within the patent text and considering potential anticipation under 35 U.S.C. § 102.

Most Relevant Prior Art for US 8,400,835

1. US 2003/0063494 A1 (Fujitsu Limited)

• Full Citation: US20030063494A1, "Semiconductor memory which has reduced fluctuation of writing speed"
• Publication Date: April 3, 2003
• Brief Description: This reference discloses a semiconductor memory device that aims to reduce fluctuations in writing speed by adjusting the bit line voltage based on the write address, thereby addressing voltage drops along the bit line.
• Potential Anticipation (35 U.S.C. § 102): None. The background section of US 8,400,835 explicitly distinguishes its invention from this conventional technique (which corresponds to Japanese Patent Publication No. 2003-109389, the priority document for US2003/0063494A1). It states that the conventional technique performs simultaneous writes "under write conditions... which are common to the memory cells," and thus "variations in write speed between the memory cells which are simultaneously written cannot be reduced." In contrast, Claim 1 of US 8,400,835 specifies changing drain voltage levels or application periods "on a memory cell-by-memory cell basis" during simultaneous writes. Therefore, this reference does not anticipate Claim 1 or any claims dependent thereon.

2. JPH0562484A (Mitsubishi Electric Corp)

• Full Citation: JPH0562484A, "Nonvolatile semiconductor memory"
• Publication Date: March 12, 1993
• Brief Description: Describes a nonvolatile semiconductor memory device with a mechanism to prevent erroneous writing by controlling the bit line potential.
• Potential Anticipation (35 U.S.C. § 102): None. The provided description is general and does not indicate disclosure of all the specific structural and functional elements of Claim 1 of US 8,400,835, particularly the M data lines, N switches, M switch control circuits, and the ability to change drain voltage levels or periods on a memory cell-by-memory cell basis during simultaneous writes.

3. JPH06150670A (Hitachi Ltd)

• Full Citation: JPH06150670A, "Semiconductor memory device"
• Publication Date: May 31, 1994
• Brief Description: Relates to a semiconductor memory device with improved write and erase characteristics.
• Potential Anticipation (35 U.S.C. § 102): None. The description is too broad to suggest anticipation of the specific architecture and individualized write parameter control of Claim 1 of US 8,400,835.

4. US 2003/0218897 A1 (Mitsubishi Denki Kabushiki Kaisha)

• Full Citation: US20030218897A1, "Nonvolatile semiconductor memory device capable of uniformly inputting/outputting data"
• Publication Date: November 27, 2003
• Brief Description: Discloses a nonvolatile semiconductor memory device capable of uniformly inputting/outputting data, addressing variations in memory cell characteristics.
• Potential Anticipation (35 U.S.C. § 102): None. While addressing uniformity and variations, the description does not suggest the specific implementation of M data lines, N switches, and M switch control circuits for individualized voltage level or period control during simultaneous writes as claimed in Claim 1 of US 8,400,835.

5. JP2004220728A (Fujitsu Ltd)

• Full Citation: JP2004220728A, "Non-volatile multi-level semiconductor memory"
• Publication Date: August 5, 2004
• Brief Description: Describes a non-volatile multi-level semiconductor memory and a method for writing data to it.
• Potential Anticipation (35 U.S.C. § 102): None. The general description of a multi-level memory and writing method does not explicitly or inherently disclose all the elements of Claim 1 of US 8,400,835.

6. US 2004/0174745 A1 (Hynix Semiconductor Inc.)

• Full Citation: US20040174745A1, "Drain pump for flash memory"
• Publication Date: September 9, 2004
• Brief Description: Details a drain pump for a flash memory device.
• Potential Anticipation (35 U.S.C. § 102): None. A drain pump is a power supply component, and its disclosure does not suggest the specific write control architecture and functionality claimed in Claim 1 of US 8,400,835 for individual adjustment of drain voltages or periods during simultaneous writes.

7. US 8,085,609 B2 (Oki Semiconductor Co., Ltd.)

• Full Citation: US8085609B2, "Nonvolatile semiconductor memory and method for detecting leakage defects of the same"
• Publication Date: December 27, 2011
• Brief Description: Pertains to a nonvolatile semiconductor memory and a method for detecting leakage defects.
• Potential Anticipation (35 U.S.C. § 102): None. This patent's focus on leakage detection does not align with or disclose the core inventive concepts of individualized write parameter control for simultaneously written cells as defined in Claim 1 of US 8,400,835. Furthermore, its publication date (December 27, 2011) is after the filing date of US 8,400,835 (July 25, 2011) and the priority date (February 6, 2009), making it non-anticipatory prior art under 35 U.S.C. § 102 for this patent.